CN109904069A - The forming method of ono dielectric layer - Google Patents
The forming method of ono dielectric layer Download PDFInfo
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- CN109904069A CN109904069A CN201910210573.XA CN201910210573A CN109904069A CN 109904069 A CN109904069 A CN 109904069A CN 201910210573 A CN201910210573 A CN 201910210573A CN 109904069 A CN109904069 A CN 109904069A
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- ono dielectric
- dielectric layer
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Abstract
The present invention provides a kind of forming method of ono dielectric layer.First, substrate is provided, the floating gate layer that the substrate surface is formed with tunnel oxide and is above the tunnel oxide layer, bottom oxide layer is formed on the floating gate layer, middle nitride layer is formed on the bottom oxide layer, then, top oxide layer is formed on the middle nitride silicon layer using ISSG method for oxidation.Compared to prior art, the forming method of ono dielectric layer provided by the invention can reduce by a step furnace process, reduce production cost.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of ono dielectric layer.
Background technique
Since coming out from first flash memory products of the 1980s, with the development of technology with each electronic product
Demand to storage, flash memory are widely used in the movement such as mobile phone, notebook, palm PC and U disk and communication apparatus, flash memory
For a kind of nonvolatile memory, operation principles are to control gate pole by changing the critical voltage of transistor or storage unit
The switch in channel makes data stored in memory not disappear because of power interruptions to achieve the purpose that storing data, dodges
A kind of special construction of electrically erasable and programmable read-only memory is saved as, nowadays flash memory, which has already taken up, non-volatile partly leads
Most of market share of body memory, becomes non-volatile semiconductor memory with fastest developing speed
Current flash memory be divided into according to the wherein difference of memory cell device structure gatestack (stacking gate) formula flash memory and
Splitting bar (separate gate) formula flash memory, the manufacture craft of flash memory include the production of control gate and the production of floating gate.Gatestack is usually such as
Shown in Fig. 1, tunnel oxide 11, floating gate 12, gate dielectric layer 13 and control gate 14 are sequentially formed on substrate 10.Wherein, grid
Pole dielectric layer 13 is usually ono dielectric layer (Oxide-Nitride-Oxide, ONO), with constantly subtracting for flush memory device size
Small, ono dielectric layer accordingly reduces as the gate-dielectric between floating gate and control gate, thickness, and traditional handicraft generally uses
Reduce the thickness of ono dielectric layer to realize, however the thickness of ono dielectric layer physically is thinned, and will cause the increase of leakage current, because
This, it is very necessary for studying the forming method of new ono dielectric layer.
Summary of the invention
The present invention provides a kind of forming method of ono dielectric layer, it is therefore intended that in the forming process for reducing ono dielectric layer
The number of furnace process, and then reduce production cost.
The present invention provides a kind of forming method of ono dielectric layer, comprising:,
Substrate, the floating gate layer that the substrate surface is formed with tunnel oxide and is above the tunnel oxide layer are provided；
Bottom oxide layer is formed on the floating gate layer；
Middle nitride layer is formed on the bottom oxide layer；And
Top oxide layer is formed on the middle nitride silicon layer, wherein the top oxide layer is in H2And O2's
It is formed in gaseous environment with ISSG method for oxidation.
Optionally, the top oxide is formed using middle nitride layer described in ISSG method for oxidation oxidized portion
Layer.
Optionally, the ISSG method for oxidation is carried out within the temperature range of 900 DEG C -1200 DEG C.
Optionally, the ISSG method for oxidation forms the reaction time of the top oxide layer as 25s-50s.
Optionally, the ISSG method for oxidation is carried out in RTP equipment.
Optionally, in H2And O2Gaseous environment in, O2And H2Ratio be 2:1-5:1.
Optionally, the bottom oxide layer is formed using thermal oxidation method.
Optionally, the middle nitride layer is formed using low pressure chemical phase method.
Optionally, the bottom oxide layer and the top oxide layer are silicon dioxide layer, the intervening nitride
Layer is silicon nitride layer.
Optionally, the bottom oxide layer with a thickness ofThe middle nitride layer with a thickness ofThe top oxide layer with a thickness of
Optionally, the ono dielectric layer is formed between floating gate and control gate.
Optionally, the ono dielectric layer is applied to the processing procedure of Flash 90shrink product.
The present invention provides a kind of forming method of ono dielectric layer.Firstly, providing substrate, the substrate surface is formed with tunnel
The floating gate layer wearing oxide layer and being above the tunnel oxide layer forms bottom oxide layer, described on the floating gate layer
Middle nitride layer is formed on bottom oxide layer, then, is formed on the middle nitride silicon layer using ISSG method for oxidation
Top oxide layer.Compared to prior art, the forming method of ono dielectric layer provided by the invention can reduce by a step boiler tube work
Skill reduces production cost.
Detailed description of the invention
Fig. 1 is the gate structure schematic diagram with ono dielectric layer；
Fig. 2 is the flow chart of ono dielectric layer forming method provided in an embodiment of the present invention；
Fig. 3 A- Fig. 3 G is structural schematic diagram corresponding to ono dielectric layer forming method provided in an embodiment of the present invention.
Specific embodiment
Gate dielectric layer as the spacer medium layer between control gate and floating gate, shape directly affect control gate and floating gate it
Between coupled capacitor, to influence the read or write speed or data holding ability (Data Retention) of data.In prior art
The method for forming gate dielectric layer (ono dielectric layer) generally forms bottom oxide and top layer oxide layer using thermal oxide, uses
Low pressure chemical phase method forms middle nitride layer, i.e., the formation of the described ono dielectric layer is needed by furnace process three times, technique
It is more complex.
The present invention provides a kind of forming method of ono dielectric layer, provides substrate, and the substrate surface is formed with tunnel oxide
Layer and the floating gate layer being above the tunnel oxide layer, form bottom oxide layer, in the bottom oxygen on the floating gate layer
Middle nitride layer is formed in compound layer, and top layer oxygen is then formed in the middle nitride layer using ISSG method for oxidation
Compound layer.Compared to prior art, the forming method of ono dielectric layer provided by the invention can reduce by a step furnace process, reduce
Production cost.
To keep the contents of the present invention more clear and easy to understand, below in conjunction with Figure of description, the contents of the present invention are done into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, and general replacement well known to those skilled in the art is also contained
Lid is within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, in detail that example of the present invention, for the ease of saying
Bright, schematic diagram is not partially enlarged in proportion to the general scale, should not be to this as restriction of the invention.
Fig. 2 is a kind of flow chart of the forming method of ono dielectric layer provided in this embodiment, as shown in Fig. 2, this implementation
A kind of forming method for ono dielectric layer that example provides, comprising the following steps:
S01: substrate, the floating gate that the substrate surface is formed with tunnel oxide and is above the tunnel oxide layer are provided
Layer；
S02: bottom oxide layer is formed on the floating gate layer；
S03: middle nitride layer is formed on the bottom oxide layer；
S04: top oxide layer is formed on the middle nitride silicon layer, wherein the top oxide layer is in H2
And O2Gaseous environment in formed with ISSG method for oxidation.
The forming method of ono dielectric layer provided in the embodiment of the present invention can be applied to 90 shrink of flash (
Two 90 nanometers of generation embedded flash memorys) product processing procedure, as the buffer layer between control gate and floating gate.Fig. 3 A to Fig. 3 G is
A kind of corresponding structural schematic diagram of forming method corresponding steps of ono dielectric layer provided in this embodiment, simultaneously below with reference to Fig. 2
The forming method of ono dielectric layer provided in this embodiment is described in detail in conjunction with Fig. 3 A to Fig. 3 G.
Firstly, executing step S01, substrate 100 is provided, 100 surface of substrate is formed with tunnel oxide 101 and position
Floating gate layer 102 on tunnel oxide 101.The as shown in Figure 3A substrate 100 can be silicon, silicon-on-insulator (SOI),
Be laminated on insulator silicon (SSOI), be laminated on insulator SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and
At least one of germanium on insulator (GeOI).Preferably, substrate 200 is silicon substrate in the present embodiment, it is herein only to show
Example, the present invention is not limited thereto.As shown in figs. 3 b and 3 c, tunnel oxide 101 and floating gate layer 102, institute are formed on a silicon substrate
Stating tunnel oxide 101 is silicon dioxide layer, and the floating gate layer 102 is polysilicon layer.
Then, step S02 is executed, as shown in Figure 3D, forms bottom oxide layer 103a on the floating gate layer 102.It can
To form bottom oxide on the floating gate layer 102 using thermal oxidation method (High-temperature oxidation, HTO)
Layer 103a, specifically can using boiler tube thermal oxide, ion implanting and thermal annealing and etc. formed bottom oxide layer, in hot oxygen
Change the silicon oxide layer surface formed by ion implanting and thermal annealing, or passes through boiler tube N2O high-temperature ammonolysis Surface Oxygen SiClx and heat
Annealing introduces Si-N key, improves the reliability of silica, and the bond strength with the middle nitride layer being subsequently formed.Institute
State bottom oxide layer with a thickness ofSuch asDeng.
The present embodiment forms ono dielectric layer 103 after forming floating gate layer 102 on the floating gate layer 102, as floating
Gate dielectric layer between grid and control gate.The ono dielectric layer 103 successively includes bottom oxide layer 103a, middle nitride
Nitride layer 103b and top oxide layer 103c.
Then, it executes step S03 and forms middle nitride layer on the bottom oxide layer 103a as shown in FIGURE 3 E
103b.The middle nitride layer is silicon nitride layer, using boiler tube Low Pressure Chemical Vapor Deposition (Low Pressure
Chemical Vapor Deposition, LPCVD) the deposit middle nitride silicon layer 103b, the preferable uniformity in order to obtain
With the middle nitride silicon layer 103b of controllability, it is general using increased temperature after low temperature nitride silicon technology silicon nitride densification process come
It realizes.Deposit formed the middle nitride layer 103b with a thickness ofSuch as
Deng.
Then, step S04 is executed, as illustrated in Figure 3 F, forms top oxide layer on the middle nitride layer 103b
103c, wherein the top oxide layer 103c is in H2And O2Gaseous environment in situ steam generate (in-situ
Steam generation, ISSG) method for oxidation formed.The ISSG oxidation for example can be in rapid thermal treatment (RTP) equipment
Middle progress.In ISSG oxidation technology, H2And O2Gaseous environment be set to oxygen-enriched gaseous environment, i.e. O2Amount be higher than H2
Amount, it is preferred that O2And H2Ratio in the range of 2:1 to 5:1, the ratio be gas volume ratio, the pressure of reaction chamber
Power is about 5Torr-15Torr.O in another embodiment of the invention2And H2Ratio be 2:1 to 3:1 in the range of.
Specifically, the substrate for being formed with middle nitride layer 103b is placed in the reaction chamber of rapid thermal treatment (RTP),
Range of the pressure of reaction chamber in about 5Torr-15Torr.Pass through the H being connected to reaction chamber2Source and O2Source is to reaction chamber
The mixture of hydrogen and oxygen, such as O are provided2And H2Ratio be 3:1, and to the middle nitride silicon layer 103b heat, make temperature
Degree reaches 900 DEG C to 1200 DEG C, O2And H2When being contacted with the middle nitride silicon layer 103b being heated, reaction in-situ occurs and generates
Gas-phase activity free radical, such as O*, OH*, the gas-phase activity free radical passes through absorption, diffusion and the middle nitride layer
The top layer portion of (silicon nitride) 103b, which reacts, generates top layer oxide layer 103c.The top layer oxide layer 103c is silica
Layer generates top layer oxide layer 103c and consumes certain thickness middle nitride layer 103b, therefore generates in step S03 of the present invention
The thickness of middle nitride layer 103b be considered as influence of the ISSG oxidizing process to its thickness, and increase accordingly intervening nitride
The thickness of layer 103b.In the present embodiment by ISSG oxidizing process generate top oxide layer 103c reaction time be 25s extremely
The thickness of 50s, the top oxide layer 103c of generation is aboutFor example, Deng.ISSG oxygen
Change method generates top oxide layer 103c and consumes a part of middle nitride layer 103b, the centre in the ono dielectric layer 103 of generation
Nitride layer 103b with a thickness ofFor example,Deng.
Bottom oxide layer 103a is generated by thermal oxidation method in the embodiment of the present invention, then, is deposited using LPCVD
Between silicon nitride layer 103b, then, utilize ISSG method for oxidation generate top oxide layer 103c.The embodiment of the present invention passes through control
The deposition thickness of middle nitride silicon layer 103b and the process conditions of ISSG method for oxidation, bottom in the ono dielectric layer 103 of formation
The thickness and prior art of oxide skin(coating) 103a, middle nitride layer 103b and top oxide layer 103c are using boiler tube work three times
The ono dielectric layer that skill is formed is consistent, but compared to prior art, forms top using ISSG method for oxidation in the embodiment of the present invention
Layer oxide skin(coating) 103c, reduces by a step furnace process, reduces production cost.And ISSG method for oxidation is used in the embodiment of the present invention
Top oxide layer 103c is formed, the uniformity of top oxide layer 103c has been correspondinglyd increase, has avoided due to top oxide layer
The inhomogeneities of 103c influences electrical uniformity, and then the read or write speed of flush memory device different location and data is avoided to keep energy
The otherness of power.
Finally, as shown in Figure 3 G, the deposit polycrystalline silicon layer on the top oxide layer 103c forms control grid layer 104.
Control gate can be used prior art and be formed, and details are not described herein.
In conclusion the present invention provides a kind of forming method of ono dielectric layer.Firstly, providing substrate, the substrate surface
The floating gate layer for being formed with tunnel oxide and being above the tunnel oxide layer forms bottom oxide on the floating gate layer
Layer, forms middle nitride layer on the bottom oxide layer, then, using ISSG method for oxidation in the middle nitride silicon
Top oxide layer is formed on layer.Compared to prior art, the forming method of ono dielectric layer provided by the invention can reduce one
Furnace process is walked, production cost is reduced.
Invention is illustrated through the foregoing embodiment, but it is to be understood that, above-described embodiment is only intended to lift
The purpose of example and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also make more kinds of changes
Type and modification, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention is by attached
Claims and its equivalent scope of category are defined.
Claims (12)
1. a kind of forming method of ono dielectric layer characterized by comprising
Substrate, the floating gate layer that the substrate surface is formed with tunnel oxide and is above the tunnel oxide layer are provided；
Bottom oxide layer is formed on the floating gate layer；
Middle nitride layer is formed on the bottom oxide layer；And
Top oxide layer is formed on the middle nitride silicon layer, wherein the top oxide layer is in H2And O2Gas
It is formed in environment with ISSG method for oxidation.
2. the forming method of ono dielectric layer according to claim 1, which is characterized in that aoxidized using ISSG method for oxidation
The part middle nitride layer and form the top oxide layer.
3. the forming method of ono dielectric layer according to claim 1, which is characterized in that the ISSG method for oxidation be
It is carried out within the temperature range of 900 DEG C -1200 DEG C.
4. the forming method of ono dielectric layer according to claim 3, which is characterized in that the ISSG method for oxidation is formed
The reaction time of the top oxide layer is 25s-50s.
5. the forming method of ono dielectric layer according to claim 1, which is characterized in that the ISSG method for oxidation be
It is carried out in RTP equipment.
6. the forming method of ono dielectric layer according to claim 1, which is characterized in that in H2And O2Gaseous environment in,
O2And H2Volume ratio be 2:1-5:1.
7. the forming method of ono dielectric layer according to claim 1, which is characterized in that the bottom oxide layer uses
Thermal oxidation method is formed.
8. the forming method of ono dielectric layer according to claim 1, which is characterized in that the middle nitride layer uses
Low pressure chemical phase method is formed.
9. the forming method of ono dielectric layer according to claim 1, which is characterized in that the bottom oxide layer and institute
Stating top oxide layer is silicon dioxide layer, and the middle nitride layer is silicon nitride layer.
10. according to claim 1 or the forming method of ono dielectric layer described in 9, which is characterized in that the bottom oxide layer
With a thickness ofThe middle nitride layer with a thickness ofThe top oxide layer with a thickness of
11. the forming method of ono dielectric layer according to claim 1, which is characterized in that the ono dielectric layer is formed in
Between floating gate and control gate.
12. the forming method of ono dielectric layer according to claim 1, which is characterized in that the ono dielectric layer is applied to
Flash 90shrink product processing procedure.
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Application publication date: 20190618 |