CN104465353A - Method for preparing ONO medium layer - Google Patents
Method for preparing ONO medium layer Download PDFInfo
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- CN104465353A CN104465353A CN201410714893.6A CN201410714893A CN104465353A CN 104465353 A CN104465353 A CN 104465353A CN 201410714893 A CN201410714893 A CN 201410714893A CN 104465353 A CN104465353 A CN 104465353A
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- ono dielectric
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- 238000000034 method Methods 0.000 title claims abstract description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 75
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 35
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 35
- 238000002360 preparation method Methods 0.000 claims abstract description 34
- 230000008569 process Effects 0.000 claims abstract description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 31
- 238000010926 purge Methods 0.000 claims description 28
- 239000002243 precursor Substances 0.000 claims description 16
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 6
- 239000010453 quartz Substances 0.000 abstract description 5
- 230000008901 benefit Effects 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010409 thin film Substances 0.000 abstract description 2
- 239000012495 reaction gas Substances 0.000 abstract 3
- 238000011065 in-situ storage Methods 0.000 abstract 2
- 230000008021 deposition Effects 0.000 abstract 1
- 238000005137 deposition process Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 230000005641 tunneling Effects 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 84
- 239000010410 layer Substances 0.000 description 39
- 239000010408 film Substances 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000003708 ampul Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000427 thin-film deposition Methods 0.000 description 2
- -1 as can be seen Substances 0.000 description 1
- 239000008280 blood Substances 0.000 description 1
- 210000004369 blood Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention relates to the field of semiconductor preparation, in particular to a method for preparing an ONO medium layer. The method is suitable for a nonvolatile NOR flash memorizer. The method includes the following steps of firstly, providing a silicon wafer, wherein a surface tunneling oxide layer and a floating gate layer formed at a preset position are sequentially arranged on a substrate of the silicon wafer; secondly, inputting first preset reaction gas through an in-situ vapor generation process, and forming bottom layer silicon oxide on the upper face of the floating gate layer; thirdly, inputting second preset reaction gas through a porous quartz tube, and forming silicon nitride on the upper side of the bottom layer silicon oxide through deposition; fourthly, inputting the first preset reaction gas through the in-situ vapor generation process, and oxidizing the surface of the silicon nitride to form top layer silicon oxide. The method has the advantages that the thickness uniformity of a thin film depositing on the surface of the silicon wafer is effectively improved, shells produced by the silicon wafer is remarkably reduced, N type dopes are not prone to being formed on contact faces of the silicon oxide and the silicon wafer, realizability is high, and the method can be widely applied to various deposition processes.
Description
Technical field
The present invention relates to semiconductor preparation field, be specifically related to a kind of preparation method of ono dielectric layer.
Background technology
Stacking ONO structure is widely used in chip fabrication processes.As the interlayer dielectric between floating boom (Floating Gate, FG) and control gate (Control Gate, CG) in nonvolatile flash memory (NOR FLASH) memory; Also can be used as the dielectric of dynamic memory (Dynamic RandomAccess Memory) and metal insulator (Metal insulatorMetal, MIM).
Stacking grid usually as shown in Figure 1, forms tunnel oxide 2, floating boom 3, ONO (Oxide-Nitride-Oxide) dielectric layer 4 and control gate 5 on substrate 1 successively.
When stacking ONO structure is as interlayer dielectric between floating boom and control gate, need the thickness uniformity of strict control ONO tri-layers.When integral thickness thickening or thinning time, the electric capacity (Capacitance) between floating boom and control gate can be affected, thus affect read or write speed or the data holding ability (Data Retention) of data.When thickness uniformity difference, electric field is concentrated in the thin place of ONO thickness, may produce medium breakdown phenomenon.In ono dielectric layer, during three-layer thin-film component not identical, the difference of electrical property being caused, such as when there will be trap (Trap) electric current containing during nitrogen in oxide layer film, affecting the reliability of its device.
At present, existing method adopts boiler tube low-pressure chemical vapor deposition (LPCVD) technique to carry out the preparation of ono dielectric layer, is divided into following three steps: 1, the preparation of bottom oxide layer; 2, the preparation of middle nitride silicon; 3, the preparation of top oxide layer.
The low-pressure chemical vapor deposition process apparatus sketch of boiler tube as shown in Figure 2, is placed with crystal-boat box 12 in reacting furnace, be placed with silicon chip 15 in crystal-boat box 12; Boiler tube cavity has two quartz ampoules in left and right; The reacting gas passed into is passed into in reacting furnace by forerunner's pipeline 16 of bottom and special air pipe 17, is diffused into around the silicon chip on brilliant boat, at high temperature forms film.Excessive gas is got rid of by gas exhaust piping 11 through inside and outside quartz ampoule 13,14.
But in the preparation process of ono dielectric layer, technical staff finds some problems, when the space width in crystal-boat box is 8 ㎜ to 11 ㎜, silicon chip 15 in crystal-boat box 12 is in trapezoidal profile, the distance of each position of two neighbouring silicon chips 15 is equal, cause the reacting gas concentration of silicon chip 15 upper surface center position to be less than the gas concentration at marginal position place, and then there is larger otherness in the oxide thickness that the oxide thickness causing silicon chip top surface edge position to grow and silicon chip upper surface center position grow.
Fig. 3 is the flowing gas state schematic diagram after reacting furnace of the prior art passes into reacting gas, as can be seen, gas is not easy to be circulated to silicon chip 15 center position in flow process, at silicon chip edge, then concentration is larger, cause silicon chip intermediate film thickness thinner relative to the film thickness at the edge of silicon chip, stack ONO interlayer dielectric is after three layers of LPCVD thin film deposition, difference in thickness on silicon chip can be amplified, the thick intermediate thin in edge, simultaneously, in the ONO preparation technology of traditional handicraft, when preparing middle silicon nitride, the technical scheme of general employing is that the gas directly simultaneously passed in order to the silicon nitride of preparation carries out reaction generation silicon nitride and covers on bottom oxide silicon, but in course of reaction, nitrogenous gas and the silicon-containing gas skewness in reacting furnace, and simultaneously due to the circulation of gas in reacting furnace as shown in Figure 3, exacerbate the phenomenon of distribution of gas inequality further, thus the silicon nitride thickness causing silicon chip surface to generate is uneven.The inhomogeneities of thickness can affect electrical uniformity, makes there are differences of the read or write speed of diverse location and data holding ability.
Summary of the invention
The invention provides a kind of ono dielectric layer preparation method, be applicable to non-volatile NORflash memory, wherein, comprise the steps:
S1, provide a substrate, this substrate surface is coated with a tunnel oxide and is positioned at the floating gate layer on tunnel oxide;
S2, employing original position moisture-generation process, form bottom silica above described floating gate layer;
S3, employing atomic layer deposition technique, form silicon nitride in described bottom silica disposed thereon;
S4, employing original position moisture-generation process, carry out oxidation operation to described silicon nitride surface, form top layer silica.
Preferably, in described step S3, step is comprised
S31, described silicon chip is placed in a crystal-boat box be provided with in the reacting furnace of precursor gas pipeline, special air pipe and purge gas lines,
S32, in described reacting furnace, input predetermined gas according to predetermined way, on described bottom silica, deposit one deck silicon nitride cover the upper surface being described bottom silica.
Preferably, in described S32, described predetermined gas comprises silicon-containing gas, nitrogenous gas, Purge gas, and described predetermined way comprises
Step S321, pass into described silicon-containing gas in reacting furnace by described precursor gas pipeline, and while passing into described silicon-containing gas, close other pipelines;
Step S322, close described precursor gas pipeline, open described purge gas lines and pass in described Purge gas to described reacting furnace;
Step S323, close described purge gas lines, open described special air pipe and pass into described nitrogenous gas in reacting furnace, the described nitrogenous gas passed into and described silicon-containing gas react and generate silicon nitride and be attached to described top layer silicon oxide surface;
Step S324, close described special air pipe and again open described purge gas lines and carry described Purge gas to reacting furnace.
Preferably, in the preparation process of carrying out described silicon nitride, using step S321, step S322, step S323 and step S324 as one-period, and carry out multiple cycle to complete the preparation technology of described silicon nitride.
Preferably, described silicon-containing gas is DCS, and described nitrogenous gas is NH3, and described Purge gas is N2.
Preferably, the thickness of described top layer silica is
the thickness of described silicon nitride is
the thickness of described bottom silica is
Preferably, in described step 1, the generation pressure limit of described original position moisture-generation process is 5torr ~ 15torr.
Preferably, in described step 1, the reaction temperature of described original position moisture-generation process is 1000 DEG C ~ 1050 DEG C.
Preferably, when carrying out the preparation of described top layer silica or described bottom silica, described first reacting gas is H
2and O
2.
Preferably, described precursor gas pipeline and special air pipe are the quartzy pipeline of porous, are vertically installed in described reacting furnace.
Compared with prior art, advantage of the present invention is: the present invention effectively can improve the thickness uniformity at silicon chip surface deposit film, obviously reduce the housing that silicon chip produces simultaneously, and the doping of N is not easily formed at silica and silicon chip contact-making surface, realisation comparatively strong, can be widely used in various depositing operation.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 is the grid structure schematic diagram with ono dielectric layer;
Fig. 2 is the schematic diagram of the vertical response stove carrying out depositing operation in prior art;
Fig. 3 is when carrying out depositing operation in prior art, and reacting gas flows to schematic diagram in reacting furnace;
Fig. 4 is that the present invention adopts cycle process to prepare the flow chart of the silicon nitride of ono dielectric layer;
Fig. 5 is precursor gas pipeline schematic diagram provided by the invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
The invention provides a kind of ono dielectric layer preparation method, comprise the steps:, a kind of ono dielectric layer preparation method, be applicable to non-volatile NOR flash memory, it is characterized in that, comprise the steps:
S1, provide a substrate, this substrate surface is coated with a tunnel oxide and is positioned at the floating gate layer on tunnel oxide;
S2, employing original position moisture-generation process, form bottom silica above described floating gate layer;
S3, employing atomic layer deposition technique, form silicon nitride in described bottom silica disposed thereon;
S4, employing original position moisture-generation process, carry out oxidation operation to described silicon nitride surface, form top layer silica.
Wherein, as shown in Figure 5, in described step S3, can be further refined as and comprise step
S31, described silicon chip 15 is placed in a crystal-boat box be provided with in the reacting furnace of precursor gas pipeline 16, special air pipe 17 and purge gas lines,
S32, in described reacting furnace, input predetermined gas according to predetermined way, on described bottom silica, deposit one deck silicon nitride cover the upper surface being described bottom silica.
Further, in described S32, described predetermined way comprises following concrete steps:
Step S321, pass into silicon-containing gas in reacting furnace by described precursor gas pipeline, and while passing into silicon-containing gas, close other pipelines;
Step S322, close described precursor gas pipeline, open described purge gas lines and pass into Purge gas in reacting furnace;
Step S323, close described purge gas lines, open described special air pipe and pass into nitrogenous gas in reacting furnace, the nitrogenous gas passed into and silicon-containing gas react and generate silicon nitride and be attached to described top silicon oxide surface;
Step S324, close described special air pipe again open purge gas lines delivery of purge gas to reacting furnace.One optional but the execution mode do not limited to is that above-mentioned silicon-containing gas is DCS (SiH
2cl
2) gas, nitrogenous gas is NH3.Described Purge gas is N2.
In the present invention, using step S321, step S322, step S323 and step S324 as one-period, and carry out multiple cycle to complete the preparation technology of described silicon nitride.Concrete, be further elaborated for one-period below.
When preparing the silicon nitride layer in the middle of ono dielectric layer, under reaction in-furnace temperature is the condition of 450 DEG C ~ 550 DEG C, first pass into DCS gas in reacting furnace by precursor gas pipeline, when the gas passed into arrives certain content, close this precursor gas pipeline, to stop conveying DCS gas to reacting furnace, and open purge gas lines, pass into nitrogen (N
2) gas in reacting furnace is purged, the DCS gas homogeneity of position in reacting furnace is improved in the process by passing into nitrogen; Close purge gas lines afterwards, open special air pipe and pass into NH
3to in reacting furnace, the DCS gas passed into and NH
3gas reaction generates silicon nitride and is attached to silicon chip surface, and the chemical equation of its reaction is:
DCS+NH
3→Si
3N
4+NH
4Cl+H
2；
Close special air pipe more afterwards, stop conveying NH
3gas, and again open purge gas lines, continue in reacting furnace and pass into N
2purge.
Carry out the aforesaid operations in multiple cycle afterwards, two cycles, three cycles ... until N number of cycle, and then generate the uniform silicon nitride of thickness at silicon chip surface.Meanwhile, in practical operation, technical staff by controlling to carry out the number of times of cycle production, and then realize controlling generate the thickness of silicon nitride.In general technology demand, such as need four cycles of employing thus complete the preparation of silicon nitride, but in order to improve the deposit thickness of this silicon nitride further, therefore can after the production carrying out four cycles, proceed the preparation technology in three cycles, and then the silicon nitride thickness generated is increased to some extent, and simultaneously silicon nitride thickness also can not carrying out and cause thickness uniformity to produce larger change with depositing operation, the thickness evenness of film is ensured by periodic production technology, and then the electric property of boost device.Simultaneously because NH3 is not easily through the silicon oxide layer of bottom, avoid the doping forming N at the contact-making surface of bottom silica and silicon chip.The electric property of further boost device.
In the present invention, when adopting original position moisture-generation process to prepare the bottom silica of ono dielectric layer, can under temperature be the condition of 1000 DEG C ~ 1050 DEG C, pressure limit is 5torr ~ 15torr.Pass into H
2and O
2gas; H
2with O
2volume ratio be 0.5% ~ 5%.By generating the active group O* of oxygen, generate SiO at silicon face
2as the top layer silica of ono dielectric layer, its course of reaction is as follows:
O
2+H
2→2O*
Si+2O*→SiO
2。
In the present invention, when adopting original position moisture-generation process to prepare the top layer silica of ono dielectric layer, by generating the active group O* of oxygen, the silicon nitride surface in intermediate layer generates SiO
2as the top layer silica of ono dielectric layer, adopt H
2with O
2as reacting gas, the particle that silicon chip surface produces significantly can be reduced.
As shown in Figure 5, precursor gas pipeline 16 of the present invention and special air pipe 17 are the quartzy pipeline of porous, traditional pipeline of simultaneously comparing extends length, therefore pass into after in gas to reacting furnace, react with silicon chip in the horizontal direction, and by unnecessary gas by quartz ampoule 13 in porous and the outer quartz ampoule 14 of porous, and discharge through blast pipe 11.Make the gas homogeneity in reacting furnace obtain effective lifting, this further improves the uniformity of the film thickness of silicon chip surface.
When wafer is placed in crystal-boat box, the cavity of a negotiable input gas is defined between upper and lower two silicon chips, this is conducive to the central region that gas is easily circulated to silicon chip, and adopt precursor gas pipeline and special air pipe to be the quartzy pipeline of porous as gas transfer pipeline, be vertically installed in reacting furnace, make the distribution of gas in reacting furnace more even, the present invention is simultaneously carrying out in thin film deposition processes, by uninterruptedly passing into reacting gas and Purge gas, the uniformity of film thickness also effectively can be improved.The present invention is realisation comparatively strong, can be widely used in the technique of each film preparation, suitable for large-scale promotion.
Adopt the ono dielectric layer that the present invention makes, the thickness of its top layer silica is
the thickness of described silicon nitride is
the thickness of described bottom silica is
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. an ono dielectric layer preparation method, is applicable to non-volatile NOR flash memory, it is characterized in that, comprise the steps:
S1, provide a substrate, this substrate surface is coated with a tunnel oxide and is positioned at the floating gate layer on tunnel oxide;
S2, employing original position moisture-generation process, form bottom silica above described floating gate layer;
S3, employing atomic layer deposition technique, form silicon nitride in described bottom silica disposed thereon;
S4, employing original position moisture-generation process, carry out oxidation operation to described silicon nitride surface, form top layer silica.
2. ono dielectric layer preparation method according to claim 1, is characterized in that, in described step S3, comprise step
S31, described silicon chip is placed in a crystal-boat box be provided with in the reacting furnace of precursor gas pipeline, special air pipe and purge gas lines;
S32, in described reacting furnace, input predetermined gas according to predetermined way, on described bottom silica, deposit one deck nitride, cover the upper surface being described bottom silica.
3. ono dielectric layer preparation method according to claim 2, is characterized in that, in described S32, described second predetermined gas comprises silicon-containing gas, nitrogenous gas, Purge gas, and described predetermined way comprises
Step S321, pass into described silicon-containing gas in reacting furnace by described precursor gas pipeline, and while passing into described silicon-containing gas, close other pipelines;
Step S322, close described precursor gas pipeline, open described purge gas lines and pass in described Purge gas to described reacting furnace;
Step S323, close described purge gas lines, open described special air pipe and pass into described nitrogenous gas in reacting furnace, the described nitrogenous gas passed into and described silicon-containing gas react and generate silicon nitride and be attached to described top layer silicon oxide surface;
Step S324, close described special air pipe and again open described purge gas lines and carry described Purge gas to reacting furnace.
4. ono dielectric layer preparation method according to claim 3, it is characterized in that, in the preparation process of carrying out described silicon nitride, using step S321, step S322, step S323 and step S324 as one-period, and carry out multiple cycle to complete the preparation technology of described silicon nitride.
5. ono dielectric layer preparation method according to claim 3, is characterized in that, described silicon-containing gas is DCS, and described nitrogenous gas is NH3, and described Purge gas is N
2.
6. ono dielectric layer preparation method according to claim 1, is characterized in that, the thickness of described top layer silica is
the thickness of described silicon nitride is
the thickness of described bottom silica is
7. ono dielectric layer preparation method according to claim 3, is characterized in that, in described step 1, the generation pressure limit of described original position moisture-generation process is 5torr ~ 15torr.
8. ono dielectric layer preparation method according to claim 3, is characterized in that, in described step 1, the reaction temperature of described original position moisture-generation process is 1000 DEG C ~ 1050 DEG C.
9. ono dielectric layer preparation method according to claim 1, is characterized in that, when carrying out the preparation of described top layer silica or described bottom silica, described first reacting gas is H
2and O
2.
10. ono dielectric layer preparation method according to claim 2, is characterized in that, described precursor gas pipeline and special air pipe are the quartzy pipeline of porous, are vertically installed in described reacting furnace.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109904069A (en) * | 2019-03-20 | 2019-06-18 | 上海华虹宏力半导体制造有限公司 | The forming method of ono dielectric layer |
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