CN109300904B - Method for forming 3D-NAND flash memory - Google Patents
Method for forming 3D-NAND flash memory Download PDFInfo
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- CN109300904B CN109300904B CN201811147897.5A CN201811147897A CN109300904B CN 109300904 B CN109300904 B CN 109300904B CN 201811147897 A CN201811147897 A CN 201811147897A CN 109300904 B CN109300904 B CN 109300904B
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
A method for forming a 3D-NAND flash memory comprises the following steps: providing a semiconductor substrate; forming a stacked structure and a channel structure penetrating through the stacked structure on a semiconductor substrate, wherein the channel structure comprises a channel layer extending along a direction vertical to the surface of the semiconductor substrate, and a drain doped region and an additional doped region which are positioned at the top of the channel structure; the additional doped region is located on the side portion of the drain doped region, the drain doped region and the additional doped region cover a portion of the channel layer, and the conductivity type of the additional doped region is opposite to that of the drain doped region. The method improves the performance of the 3D-NAND flash memory.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a 3D-NAND flash memory.
Background
Flash memories (also called Flash memories) are mainly characterized by being capable of maintaining stored information for a long time without power up and having the advantages of high integration level, high access speed, easy erasing and rewriting and the like, and thus, Flash memories are mainstream memories of non-volatile memories. Flash memories are classified into NOR Flash memories (NOR Flash memories) and NAND Flash memories (NAND Flash memories) according to their structures. Compared with NOR Flash Memory, NAND Flash Memory can provide high unit density, can achieve high storage density, and has faster writing and erasing speed.
With the development of planar flash memories, the manufacturing process of semiconductors has made great progress. However, the development of planar flash memories currently encounters various challenges: physical limits such as exposure technology limits, development technology limits, and storage electron density limits. In this context, three-dimensional (3D) flash memory applications, such as 3D-NAND flash memory, have been developed to address the difficulties encountered with planar flash memory and to pursue lower production costs per unit cell.
However, in the prior art, the performance of the 3D-NAND flash memory is poor.
Disclosure of Invention
The invention provides a method for forming a 3D-NAND flash memory, which aims to improve the performance of the 3D-NAND flash memory.
In order to solve the above problems, the present invention provides a method for forming a 3D-NAND flash memory, comprising: providing a semiconductor substrate; forming a stacked structure and a channel structure penetrating through the stacked structure on a semiconductor substrate, wherein the channel structure comprises a channel layer extending along a direction vertical to the surface of the semiconductor substrate, and a drain doped region and an additional doped region which are positioned at the top of the channel structure; the additional doped region is located on the side portion of the drain doped region, the drain doped region and the additional doped region cover a portion of the channel layer, and the conductivity type of the additional doped region is opposite to that of the drain doped region.
Optionally, the step of forming the stack structure, the channel structure, the drain doping region and the additional doping region includes: forming a composite dielectric layer on the semiconductor substrate, wherein the composite dielectric layer comprises a plurality of staggered and laminated sacrificial layers and insulating layers; forming a channel hole in the composite dielectric layer; forming the channel structure in the channel hole; after the channel structure is formed, removing the sacrificial layer to form an opening; forming a conductive layer in the opening, the stacked structure including an insulating layer and a conductive layer.
Optionally, the step of forming the channel structure in the channel hole includes: forming an initial channel structure in the channel hole, wherein the initial channel structure comprises a channel layer, a channel medium layer and a semiconductor connecting layer, the channel layer and the channel medium layer extend along the direction vertical to the surface of the semiconductor substrate, the semiconductor connecting layer is positioned on the top surface of the channel medium layer, and the channel layer is positioned on the outer sides of the channel medium layer and the semiconductor connecting layer; forming a drain doping region in a part of the semiconductor connecting layer and a part of the channel layer at the side part of the semiconductor connecting layer by adopting a first ion implantation process; and forming additional doped regions in a part of the semiconductor connecting layer and a part of the channel layer at the side part of the semiconductor connecting layer by adopting a second ion implantation process.
Optionally, the channel layer and the semiconductor connection layer are made of the same material.
Optionally, the semiconductor substrate has trap ions therein, and the conductivity type of the trap ions is the same as that of the drain doped region.
Optionally, when the type of the 3D-NAND flash memory is N-type, the conductivity type of the drain doped region is N-type, and the conductivity type of the additional doped region is P-type.
Optionally, when the type of the 3D-NAND flash memory is P-type, the conductivity type of the drain doped region is P-type, and the conductivity type of the additional doped region is N-type.
Optionally, the ratio of the area of the additional doped region projected on the surface of the semiconductor substrate to the area of the drain doped region projected on the surface of the semiconductor substrate is 4/5-6/5.
Optionally, the method further includes: forming a metal substrate; the metal substrate is located at the bottom of the semiconductor substrate.
Optionally, the channel structure further includes: and the metal silicide layer is positioned on the upper surfaces of the drain doping region and the additional doping region.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the 3D-NAND flash memory provided by the technical scheme of the invention, the top area in the channel structure is provided with a drain doping area and an additional doping area, the additional doping area is positioned on the side part of the drain doping area, the drain doping area and the additional doping area are both covered on part of the channel layer, and the conductivity type of the additional doping area is opposite to that of the drain doping area. When the 3D-NAND carries out erasing operation, the additional doping region can provide multi-photon injection to the channel layer, and then penetrates through the tunneling dielectric layer to enter the storage layer, and the electric charges stored in the storage layer are erased. Therefore, in the erasing process, the current is relatively large, and the erasing efficiency is high. Since there is no need to rely on the semiconductor substrate to implant majority carriers in the 3D-NAND flash in the erase operation, the choice of conductivity type of the semiconductor substrate is not limited. When the 3D-NAND flash memory is N-type, the conductivity type of the semiconductor substrate can be selected to be N-type, and when the 3D-NAND flash memory is P-type, the conductivity type of the semiconductor substrate can be selected to be P-type. Therefore, the read operation of the 3D-NAND flash memory is convenient, and the method is particularly represented by the following steps: in the reading operation, an inversion layer does not need to be formed in the semiconductor substrate, so that the operating voltage can be reduced, and the reading operation can be conveniently performed. In conclusion, the performance of the 3D-NAND flash memory is improved.
And secondly, during reading operation, an inversion layer does not need to be formed in the semiconductor substrate, and correspondingly, a source line doping layer does not need to be formed, so that the process steps are reduced, and the process cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a 3D-NAND flash memory;
FIGS. 2 to 9 are schematic structural diagrams illustrating a 3D-NAND flash memory formation process according to an embodiment of the present invention;
FIGS. 10 to 13 are schematic structural diagrams illustrating a 3D-NAND flash memory formation process according to another embodiment of the present invention.
Detailed Description
As described in the background, the prior art 3D-NAND flash memory has poor performance.
A 3D-NAND flash memory, the type of the 3D-NAND flash memory being N-type, the 3D-NAND flash memory comprising, with reference to fig. 1: a semiconductor substrate 120; a stack structure on the semiconductor substrate 120, the stack structure including alternately stacked insulating layers and control gates 130; a channel structure penetrating the stacked structure, the channel structure including a channel layer 150 and a memory layer 160 extending in a direction perpendicular to a surface of the semiconductor substrate 120, the memory layer 160 including a blocking dielectric layer, a storage layer, and a tunneling dielectric layer; and an N-type drain doped region 170 located in a top region of the channel structure.
There are two main ways to perform an erase operation in 3D-NAND, one is bulk erase and the other is GID L (gate-induced drain leakage) erase.
For the 3D-NAND flash memory, the substrate body erasing mode is as follows: voltages are respectively applied to the gate structure and the semiconductor substrate 120, so that holes enter the channel layer from the semiconductor substrate 120 and further enter the storage layer through the tunneling dielectric layer, and the holes and electrons in the storage layer are recombined.
For the 3D-NAND flash memory, the GID L is erased by applying voltages to the gate structure and the N-type drain doping region 170 respectively to make holes enter the channel layer from the N-type drain doping region 170, further penetrate through the tunneling dielectric layer to enter the memory layer, and the holes and electrons in the memory layer are recombined.
In general, the bulk erase of the substrate has an advantage over the GID L erase in that when the type of the 3D-NAND flash memory is N-type, the conductivity type of the semiconductor substrate 120 is P-type, and holes are majority in the P-type semiconductor substrate 120, so the semiconductor substrate 120 easily injects holes into the channel layer, and during the erase process, the current is relatively large and the erase efficiency is high.
On the basis, as the conductivity type of the semiconductor substrate 120 is P-type, there are many inconveniences to the read operation of the 3D-NAND flash memory, which are specifically shown in the following: in performing a read operation, an inversion layer needs to be formed in the semiconductor substrate, which requires a larger operation voltage to be supplied. In sum, the performance of the 3D-NAND flash memory is reduced.
On the basis, the invention provides a method for forming a 3D-NAND flash memory, which comprises the following steps: providing a semiconductor substrate; forming a stacked structure and a channel structure penetrating through the stacked structure on a semiconductor substrate, wherein the channel structure comprises a channel layer extending along a direction vertical to the surface of the semiconductor substrate, and a drain doped region and an additional doped region which are positioned at the top of the channel structure; the additional doped region is located on the side portion of the drain doped region, the drain doped region and the additional doped region cover a portion of the channel layer, and the conductivity type of the additional doped region is opposite to that of the drain doped region. The method improves the performance of the 3D-NAND flash memory.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 9 are schematic structural diagrams illustrating a 3D-NAND flash memory formation process according to an embodiment of the invention.
Referring to fig. 2, a semiconductor substrate 200 is provided.
The material of the semiconductor substrate 200 includes single crystal silicon or polycrystalline silicon.
The semiconductor substrate 200 has trap ions therein, and the conductivity type of the trap ions is the same as that of a subsequently formed drain doped region.
In this embodiment, the method further includes: forming a metal substrate 201, wherein the metal substrate 201 is located at the bottom of the semiconductor substrate 200.
The material of the metal substrate 201 includes a metal silicide material, such as WSi.
Next, a stack structure and a channel structure penetrating through the stack structure are formed on the semiconductor substrate 200, wherein the channel structure comprises a channel layer extending along a direction vertical to the surface of the semiconductor substrate 200, and a drain doped region and an additional doped region located at the top of the channel structure; the additional doped region is located on the side portion of the drain doped region, the drain doped region and the additional doped region cover a portion of the channel layer, and the conductivity type of the additional doped region is opposite to that of the drain doped region.
The steps of forming the stack structure, the channel structure, the drain doped region and the additional doped region are described in detail below.
With continued reference to fig. 2, a composite dielectric layer 210 is formed on the semiconductor substrate 200, wherein the composite dielectric layer 210 includes a plurality of alternately stacked sacrificial layers 211 and insulating layers 212, and both the top layer and the bottom layer of the composite dielectric layer 210 are the insulating layers 212.
Each layer in the composite dielectric layer 210 is stacked from bottom to top, and the stacking direction of each layer in the composite dielectric layer 210 is perpendicular to the surface of the semiconductor substrate 200.
In this embodiment, the insulating layer 212 is made of silicon oxide, and the sacrificial layer 211 is made of silicon nitride.
The process for forming the insulating layer 212 is a deposition process, such as a plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process, or a low pressure chemical vapor deposition process. The process of forming the sacrificial layer 211 is a deposition process, such as a plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process, or a low pressure chemical vapor deposition process.
Referring to fig. 3, a trench hole 220 is formed in the composite dielectric layer 210.
The process of forming the channel hole 220 includes an anisotropic dry etching process.
Referring to fig. 4, an initial channel structure is formed in the channel hole 220.
The initial channel structure comprises a memory layer 241, a channel layer 242, a channel medium layer 243 and a semiconductor connecting layer 244, wherein the channel layer 242 and the channel medium layer 243 both extend along a direction vertical to the surface of the semiconductor substrate 200, the semiconductor connecting layer 244 is positioned on the top surface of the channel medium layer 243, and the channel layer 242 is positioned on the outer side of the channel medium layer 243 and the semiconductor connecting layer 244; the memory layer 241 is located outside the channel layer 242.
The memory layer 241 extends in a direction perpendicular to the surface of the semiconductor substrate 200.
The memory layer 241 includes a blocking dielectric layer, a storage layer and a tunneling dielectric layer, which are sequentially stacked in a direction perpendicular to the sidewall of the channel structure and from the outside of the channel structure to the inside of the channel structure.
The blocking dielectric layer and the tunneling dielectric layer are made of silicon oxide, and the storage layer is made of silicon nitride.
The material of the channel layer 242 is polysilicon.
The channel layer 242 is made of the same material as the semiconductor connection layer 244.
Referring to fig. 5, a drain doped region 251 is formed in a portion of the semiconductor connection layer 244 and a portion of the channel layer 242 at a side of the semiconductor connection layer 244 using a first ion implantation process; a second ion implantation process is used to form additional doped regions 252 in portions of the semiconductor connecting layer 244 and portions of the channel layer 242 at the sides of the semiconductor connecting layer 244.
After the first ion implantation process is carried out, carrying out a second ion implantation process; or, after the second ion implantation process, the first ion implantation process is performed.
At this time, a channel structure is formed in the channel hole 220, and the drain doping region 251 and the additional doping region 252 are located at the top of the channel structure.
The channel structure includes a channel layer 242, a channel dielectric layer 243, a memory layer 241, and a drain doped region 251 and an additional doped region 252.
The additional doped region 252 is located at a side portion of the drain doped region 251, and the drain doped region 251 and the additional doped region 252 both cover a portion of the channel layer 242, and a conductivity type of the additional doped region 252 is opposite to a conductivity type of the drain doped region 251.
The drain doping region 251 constitutes a drain region of the 3D-NAND flash memory.
When the type of the 3D-NAND flash memory is N-type, the conductivity type of the drain doped region 251 is N-type, and the conductivity type of the additional doped region 252 is P-type.
When the type of the 3D-NAND flash memory is P-type, the conductivity type of the drain doped region 251 is P-type, and the conductivity type of the additional doped region 252 is N-type.
The additional doped region 252 has additional ions therein, the concentration of the additional ions being 10E18 atoms/cm3～10E21atom/cm3。
The ratio of the area of the additional doped region 252 projected on the surface of the semiconductor substrate 200 to the area of the drain doped region 251 projected on the surface of the semiconductor substrate 200 is 4/5-6/5.
The additional doped region 252 adjoins the drain doped region 251.
The additional doped region 252 functions to include: when the type of the 3D-NAND flash memory is N type, when the 3D-NAND flash memory performs an erasing operation, holes are injected into the channel layer 242 from the additional doping region 252, then penetrate through the tunneling dielectric layer and enter the memory layer, and the holes and electrons in the memory layer are compounded; when the type of the 3D-NAND flash memory is P-type, when the 3D-NAND flash memory performs an erase operation, electrons are injected into the channel layer 242 from the additional doped region 252, and then enter the memory layer through the tunneling dielectric layer, and the electrons and holes in the memory layer are recombined.
When the 3D-NAND performs an erase operation, the additional doped region 252 can provide multi-photon injection into the channel layer 242, and further through the tunnel dielectric layer into the memory layer, thereby implementing the erase of the charges stored in the memory layer. Therefore, in the erasing process, the current is relatively large, and the erasing efficiency is high.
Referring to fig. 6, a top dielectric layer 260 is formed on the channel structure and the composite dielectric layer 210.
The top dielectric layer 260 is made of silicon oxide, silicon oxynitride or silicon oxycarbide. The top dielectric layer 260 is formed by a deposition process, such as a plasma cvd process, an atomic layer deposition process, a low pressure cvd process, or a sub-atmospheric cvd process.
Referring to fig. 7, gate spacers 270 are formed through the top dielectric layer 260 and the composite dielectric layer 210.
In this embodiment, during the read operation, an inversion layer does not need to be formed in the semiconductor substrate 200, and correspondingly, a source line doping layer does not need to be formed in the semiconductor substrate 200 at the bottom of the gate spacer 270, thereby reducing the process steps and the process cost.
Referring to fig. 8, after the gate spacer 270 is formed, the sacrificial layer 211 is removed to form an opening 280.
Referring to fig. 9, a conductive layer 290 is formed in the opening 280 (refer to fig. 8).
The insulating layer 212 and the material layers between adjacent insulating layers 212 form a stacked structure 300. In the present embodiment, the stacked structure 300 includes an insulating layer 212 and a conductive layer 290.
Since there is no need to rely on the semiconductor substrate to implant majority carriers in the 3D-NAND flash in the erase operation, the choice of conductivity type of the semiconductor substrate 200 is not limited. The conductivity type of the semiconductor substrate 200 may be selected to be N-type when the 3D-NAND flash memory is N-type, and the conductivity type of the semiconductor substrate 200 may be selected to be P-type when the 3D-NAND flash memory is P-type. Therefore, the read operation of the 3D-NAND flash memory is convenient, and the method is particularly represented by the following steps: in the reading operation, an inversion layer does not need to be formed in the semiconductor substrate 200, and the operating voltage can be reduced, so that the reading operation can be performed more conveniently. In conclusion, the performance of the 3D-NAND flash memory is improved.
The present invention further provides a 3D-NAND flash memory formed by the above method, referring to fig. 9, including: a semiconductor substrate 200; a stack structure 300 on the semiconductor substrate 200; a channel structure penetrating the stacked structure 300, the channel structure including a channel layer 242 extending in a direction perpendicular to a surface of the semiconductor substrate 200, and a drain doped region 251 and an additional doped region 252 on top of the channel structure; the additional doped region 252 is located at a side portion of the drain doped region 251, and the drain doped region 251 and the additional doped region 252 both cover a portion of the channel layer, and a conductivity type of the additional doped region 252 is opposite to a conductivity type of the drain doped region 251.
When the type of the 3D-NAND flash memory is N-type, the conductivity type of the drain doped region 251 is N-type, and the conductivity type of the additional doped region 252 is P-type.
When the type of the 3D-NAND flash memory is P-type, the conductivity type of the drain doped region 251 is P-type, and the conductivity type of the additional doped region 252 is N-type.
The additional doped region 252 has additional ions therein, the concentration of the additional ions being 10E18 atoms/cm3～10E21atom/cm3。
The ratio of the area of the additional doped region 252 projected on the surface of the semiconductor substrate 200 to the area of the drain doped region 251 projected on the surface of the semiconductor substrate 200 is 4/5-6/5.
The additional doped region 252 adjoins the drain doped region 251.
The semiconductor substrate 200 has trap ions therein, and the conductivity type of the trap ions is the same as that of the drain doped region 251.
The channel structure further includes: a memory layer 241 extending in a direction perpendicular to the surface of the semiconductor substrate 200, the memory layer 241 being located outside the channel layer 242; the memory layer 241 includes a blocking dielectric layer, a storage layer and a tunneling dielectric layer, which are sequentially stacked in a direction perpendicular to the sidewall of the channel structure and from the outside of the channel structure to the inside of the channel structure.
The 3D-NAND flash memory further comprises: and the metal substrate 201 is positioned at the bottom of the semiconductor substrate 200.
The material of the metal substrate 201 comprises a metal silicide material, which comprises WSi.
The material of the semiconductor substrate 200 includes polycrystalline silicon or monocrystalline silicon.
In the 3D-NAND flash memory provided in this embodiment, since there is no need to rely on the semiconductor substrate 200 to inject majority carriers during the erase operation of the 3D-NAND flash memory, the selection of the conductivity type of the semiconductor substrate 200 is not limited. The conductivity type of the semiconductor substrate 200 may be selected to be N-type when the 3D-NAND flash memory is N-type, and the conductivity type of the semiconductor substrate 200 may be selected to be P-type when the 3D-NAND flash memory is P-type. Therefore, the read operation of the 3D-NAND flash memory is convenient, and the method is particularly represented by the following steps: in the reading operation, an inversion layer does not need to be formed in the semiconductor substrate 200, and the operating voltage can be reduced, so that the reading operation can be performed more conveniently. In conclusion, the performance of the 3D-NAND flash memory is improved.
When the 3D-NAND flash memory is of the N type, the conductivity type of the semiconductor substrate 200 may be selected to be the N type, and the resistivity of the semiconductor substrate 200 is lowered.
Another embodiment of the present invention further provides a method for forming a 3D-NAND flash memory, which is different from the previous embodiment in that: the formed channel structure also comprises a metal silicide layer positioned on the upper surfaces of the drain doping region and the additional doping region.
Referring to fig. 10, fig. 10 is a schematic view based on fig. 5, a metal silicide process is performed to form a metal silicide layer 310 on the upper surfaces of the drain doping region 251 and the additional doping region 252.
A plug is formed on the metal silicide layer 310 in the following, the metal silicide layer 310 can reduce the contact resistance between the plug and the drain doped region 251 and between the plug and the additional doped region 252; next, the plug is in contact with the metal silicide layer 310 to electrically connect the plug with the drain doped region 251 and the additional doped region 252, respectively, so that there is no need to consider the problem of contact position shift between the plug and the drain doped region 251 and the additional doped region 252.
The metal silicification process comprises the following steps: forming a metal layer on the upper surfaces of the drain doped region 251 and the additional doped region 252; the metal layer is annealed to react with a portion of the drain doping region 251 and a portion of the additional doping region 252, respectively, to form a metal silicide layer 310.
Referring to fig. 11, a top dielectric layer 360 is formed on the channel structure and the composite dielectric layer; gate spacers 370 are formed through the top dielectric layer 360 and the composite dielectric layer 210.
Referring to fig. 12, after the gate spacer 370 is formed, the sacrificial layer 211 is removed to form an opening 380.
Referring to fig. 13, a conductive layer 390 is formed in the opening 380.
Correspondingly, the embodiment also provides a 3D-NAND flash memory formed by the method, and the 3D-NAND flash memory of the embodiment is different from the 3D-NAND flash memory of the previous embodiment in that: the channel structure further includes: a metal silicide layer 310 on the upper surfaces of the drain doped region 251 and the additional doped region 252. The same portions in this embodiment as those in the previous embodiment will not be described in detail.
The invention also provides an operating method of the 3D-NAND flash memory, which is described by taking the 3D-NAND flash memory in fig. 9 as an example, and the operating method of the 3D-NAND flash memory includes: an erase operation is performed during which a multi-photon implant is provided into the channel layer 242 by the additional doped region 252.
Specifically, during the erase operation, the additional doped region 252 provides a multi-photon implant into the channel layer 242, and further through the tunnel dielectric layer into the memory layer to recombine with the charges stored in the memory layer.
It should be noted that during the erase operation, the majority carriers provided by the additional doped region 252 may bypass the drain doped region 251 during the implantation into the channel layer 242, i.e., the majority carriers provided by the additional doped region 252 may not flow through the drain doped region 251.
The working method of the 3D-NAND flash memory further comprises the following steps: carrying out programming operation; during a programming operation, a multi-photon implantation is provided from the drain doped region 251 into the channel layer 242, and further through the tunnel dielectric layer into the memory layer.
When the conductivity type of the semiconductor substrate is the same as that of the drain doped region 251, the semiconductor substrate also provides multi-photon injection into the channel layer 242 during the programming operation, and further passes through the tunneling dielectric layer and enters the memory layer.
It should be noted that during the programming operation, the majority carriers provided by the drain doped region 251 may bypass the additional doped region 252 during the implantation into the channel layer 242, i.e., the majority carriers provided by the drain doped region 251 may not flow through the additional doped region 252.
The working method of the 3D-NAND flash memory further comprises the following steps: performing a reading operation; during a read operation, a majority implant is provided to the channel by the drain dopant region 251.
In layer 242 and flows through semiconductor substrate 200. Specifically, during a read operation, a plurality of photons provided by the drain doped region 251 sequentially flow through the channel layer 242, the semiconductor substrate 200 and the metal substrate 201.
It should be noted that during the read operation, the majority carriers provided by the drain doped region 251 may bypass the additional doped region 252 during the implantation into the channel layer 242, i.e., the majority carriers provided by the drain doped region 251 may not flow through the additional doped region 252.
The operation method of the 3D-NAND flash memory in fig. 13 refers to the operation method of the 3D-NAND flash memory in fig. 9, and is not described in detail.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method for forming a 3D-NAND flash memory, comprising:
providing a semiconductor substrate;
forming a stacked structure and a channel structure penetrating through the stacked structure on a semiconductor substrate, wherein the channel structure comprises a channel layer extending along a direction vertical to the surface of the semiconductor substrate, and a drain doped region and an additional doped region which are positioned at the top of the channel structure;
the additional doped region is located on the side portion of the drain doped region, the drain doped region and the additional doped region cover a portion of the channel layer, and the conductivity type of the additional doped region is opposite to that of the drain doped region.
2. The method of claim 1, wherein the step of forming the stack structure, the channel structure, the drain doped region and the additional doped region comprises:
forming a composite dielectric layer on the semiconductor substrate, wherein the composite dielectric layer comprises a plurality of staggered and laminated sacrificial layers and insulating layers;
forming a channel hole in the composite dielectric layer;
forming the channel structure in the channel hole;
after the channel structure is formed, removing the sacrificial layer to form an opening;
forming a conductive layer in the opening, the stacked structure including an insulating layer and a conductive layer.
3. The method of claim 2, wherein the step of forming the channel structure in the channel hole comprises:
forming an initial channel structure in the channel hole, wherein the initial channel structure comprises a channel layer, a channel medium layer and a semiconductor connecting layer, the channel layer and the channel medium layer extend along the direction vertical to the surface of the semiconductor substrate, the semiconductor connecting layer is positioned on the top surface of the channel medium layer, and the channel layer is positioned on the outer sides of the channel medium layer and the semiconductor connecting layer;
forming a drain doping region in a part of the semiconductor connecting layer and a part of the channel layer at the side part of the semiconductor connecting layer by adopting a first ion implantation process;
and forming additional doped regions in a part of the semiconductor connecting layer and a part of the channel layer at the side part of the semiconductor connecting layer by adopting a second ion implantation process.
4. The method of claim 3, wherein the channel layer and the semiconductor connection layer are made of the same material.
5. The method of claim 1, wherein the semiconductor substrate has trap ions therein, and the trap ions have a conductivity type same as that of the drain doped region.
6. The method as claimed in claim 1, wherein when the 3D-NAND flash memory is N-type, the conductivity type of the drain doped region is N-type, and the conductivity type of the additional doped region is P-type.
7. The method as claimed in claim 1, wherein when the 3D-NAND flash memory is P-type, the conductivity type of the drain doped region is P-type, and the conductivity type of the additional doped region is N-type.
8. The method as claimed in claim 1, wherein the ratio of the area of the additional doped region projected on the surface of the semiconductor substrate to the area of the drain doped region projected on the surface of the semiconductor substrate is 4/5-6/5.
9. The method of claim 1, further comprising: forming a metal substrate; the metal substrate is located at the bottom of the semiconductor substrate.
10. The method of claim 1, wherein the channel structure further comprises: and the metal silicide layer is positioned on the upper surfaces of the drain doping region and the additional doping region.
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