CN109300904A - The forming method of 3D-NAND flash memory - Google Patents
The forming method of 3D-NAND flash memory Download PDFInfo
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- CN109300904A CN109300904A CN201811147897.5A CN201811147897A CN109300904A CN 109300904 A CN109300904 A CN 109300904A CN 201811147897 A CN201811147897 A CN 201811147897A CN 109300904 A CN109300904 A CN 109300904A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
A kind of forming method of 3D-NAND flash memory, comprising: semiconductor substrate is provided；Stacked structure and the channel structure through the stacked structure are formed on a semiconductor substrate, and the channel structure includes along the channel layer and leakage doped region and additional dopings area at the top of the channel structure extended perpendicular to semiconductor substrate surface direction；The additional dopings area is located at the side of the leakage doped region, and the leakage doped region and additional dopings area are covered on the channel layer of part, and the conduction type in the additional dopings area is opposite with the leakage conduction type of doped region.The method improves the performance of 3D-NAND flash memory.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of forming methods of 3D-NAND flash memory.
Background technique
Flash memory (Flash Memory) is also known as flash memory, and flash memory is mainly characterized by energy in the case where not powered
The long-term information for keeping storage, and have many advantages, such as that integrated level is high, access speed is fast, be easy to wipe and rewrite, therefore become non-
The mainstream memory of volatile storage.According to the difference of structure, flash memory be divided into NOT gate flash memory (NOR Flash Memory) and
NAND gate flash memory (NAND Flash Memory).Can be provided compared to NOR Flash Memory, NAND Flash Memory and
High cell density, can achieve high storage density, and be written and the speed of erasing also faster.
With the development of plane flash memory, the production technology of semiconductor achieves huge progress.But current plane
The development of flash memory encounters various challenges: physics limit, such as the exposure technique limit, the developing technique limit and storage electron density pole
Limit etc..In this context, to solve the difficulty that encounters of plane flash memory and pursue being produced into for lower unit storage unit
This, three-dimensional (3D) flash memory is applied and is given birth to, such as 3D-NAND flash memory.
However, in the prior art, the performance of 3D-NAND flash memory is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of 3D-NAND flash memory, to improve the property of 3D-NAND flash memory
Energy.
To solve the above problems, the present invention provides a kind of forming method of 3D-NAND flash memory, comprising: provide semiconductor lining
Bottom；It forms stacked structure on a semiconductor substrate and the channel structure through the stacked structure, the channel structure includes edge
The channel layer and leakage doped region at the top of the channel structure that extend perpendicular to semiconductor substrate surface direction and additional
Doped region；The additional dopings area is located at the side of the leakage doped region, and the leakage doped region and additional dopings area cover
On the channel layer of part, the conduction type in the additional dopings area is opposite with the leakage conduction type of doped region.
Optionally, the step of forming the stacked structure, channel structure, leakage doped region and additional dopings area includes: in institute
It states and forms compound medium layer in semiconductor substrate, the compound medium layer includes sacrificial layer and the insulation of several layers intersecting
Layer；Channel hole is formed in the compound medium layer；The channel structure is formed in the channel hole；Form the channel junction
After structure, sacrificial layer is removed, forms opening；Conductive layer is formed in said opening, and the stacked structure includes insulating layer and conduction
Layer.
Optionally, the step of forming the channel structure in the channel hole includes: to be formed just in the channel hole
Beginning channel structure, the original trench structure include channel layer, channel dielectric layer and semiconductor articulamentum, the channel layer and institute
It states channel dielectric layer to extend along perpendicular to semiconductor substrate surface direction, the semiconductor articulamentum is located at channel dielectric layer
Top surface, the channel layer are located at the outside of the channel dielectric layer and the semiconductor articulamentum；It is infused using the first ion
Enter technique formed in the semiconductor articulamentum of part and in the part channel layer of semiconductor articulamentum side leakage mix
Miscellaneous area；Using the second ion implantation technology in the semiconductor articulamentum of part and the part of semiconductor articulamentum side
Additional dopings area is formed in the channel layer.
Optionally, the channel layer is identical as the material of semiconductor articulamentum.
Optionally, there is trap ion, the conduction type of the trap ion and the leakage doped region in the semiconductor substrate
Conduction type it is identical.
Optionally, when the type of the 3D-NAND flash memory is N-type, the conduction type of the leakage doped region is N-type, institute
The conduction type for stating additional dopings area is p-type.
Optionally, when the type of the 3D-NAND flash memory is p-type, the conduction type of the leakage doped region is p-type, institute
The conduction type for stating additional dopings area is N-type.
Optionally, the additional dopings area is projected in the area of semiconductor substrate surface and the leakage doped region is projected in half
The area ratio value of conductor substrate surface is 4/5~6/5.
Optionally, further includes: form metal substrate；The metal substrate is located at the bottom of the semiconductor substrate.
Optionally, the channel structure further include: positioned at the metallic silicon of the leakage doped region and additional dopings area upper surface
Compound layer.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the 3D-NAND flash memory that technical solution of the present invention provides, top area has in the channel structure
There is a leakage doped region and additional dopings area, the additional dopings area is located at the side of the leakage doped region, the leakage doped region and attached
Doped region is added to be covered on the channel layer of part, the conduction type in the additional dopings area is led with the leakage doped region
Electric type is opposite.When 3D-NAND executes erasing operation, additional dopings area is capable of providing more sons and is injected into channel layer, and then wears
It crosses tunneling medium layer to enter in accumulation layer, realizes the erasing to stored charge in accumulation layer.Therefore, in erase process,
Electric current is relatively large, and efficiency of erasing is high.It is more without relying on semiconductor substrate injection since 3D-NAND flash memory is in erasing operation
Son, therefore the selection of the conduction type of semiconductor substrate is unrestricted.When 3D-NAND flash memory is N-type, semiconductor substrate is led
Electric type may be selected to be N-type, and when 3D-NAND flash memory is p-type, the conduction type of semiconductor substrate may be selected to be p-type.Make in this way
The read operation for obtaining 3D-NAND flash memory is convenient, is in particular in: anti-without being formed in the semiconductor substrate when read operation
Type layer, operation voltage can reduce, so that the more convenient execution of read operation.To sum up, the performance of 3D-NAND flash memory is improved.
Secondly, when read operation, without forming inversion layer in the semiconductor substrate, correspondingly, not necessarily forming source line
Doped layer reduces processing step in this way, reduces process costs.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of 3D-NAND flash memory；
Fig. 2 to Fig. 9 is the structural schematic diagram of 3D-NAND flash memory forming process in one embodiment of the invention；
Figure 10 to Figure 13 is the structural schematic diagram of 3D-NAND flash memory forming process in another embodiment of the present invention.
Specific embodiment
As described in background, the performance of the 3D-NAND flash memory of the prior art is poor.
The type of a kind of 3D-NAND flash memory, 3D-NAND flash memory is N-type, and with reference to Fig. 1,3D-NAND flash memory includes: semiconductor
Substrate 120；Stacked structure in semiconductor substrate 120, the stacked structure include insulating layer and the control of intersecting
Grid 130；Through the channel structure of the stacked structure, the channel structure includes along perpendicular to 120 surface side of semiconductor substrate
To the channel layer 150 and memory layer 160 of extension, the memory layer 160 includes block media layer, accumulation layer and Tunnel dielectric
Layer；The N-type of top area leaks doped region 170 in the channel structure.
There are mainly two types of the modes of 3D-NAND execution erasing operation, one kind is that substrate body is wiped, and another kind is GIDL
(gate induced drain leakage, gate-induced drain leakage) erasing.
For above-mentioned 3D-NAND flash memory, the mode of substrate body erasing are as follows: divide on gate structure and semiconductor substrate 120
Not Shi Jia voltage, so that hole is entered channel layer from semiconductor substrate 120, and then pass through tunneling medium layer and enter in accumulation layer, it is empty
Electronics in cave and accumulation layer is compound.
For above-mentioned 3D-NAND flash memory, the mode of GIDL erasing are as follows: on gate structure and N-type leakage doped region 170 respectively
Apply voltage, so that hole is entered channel layer from N-type leakage doped region 170, and then pass through tunneling medium layer and enter in accumulation layer, hole
It is compound with the electronics in accumulation layer.
In general, the erasing of substrate body has advantage than GIDL erasing, show: when the type of 3D-NAND flash memory is N-type,
The conduction type of the semiconductor substrate 120 is p-type, and hole is mostly sub in the semiconductor substrate 120 of p-type, therefore is partly led
Body substrate 120 is easy to inject hole in channel layer, and in erase process, electric current is relatively large, and efficiency of erasing is high.
On this basis, since the conduction type of the semiconductor substrate 120 is p-type, lead to 3D-NAND flash memory
There are inconveniences for read operation, are in particular in: during executing read operation, needing to form transoid in the semiconductor substrate
Layer, needs to provide so biggish operation voltage.To sum up, lead to the reduced performance of 3D-NAND flash memory.
On this basis, the present invention provides a kind of forming method of 3D-NAND flash memory, comprising: provides semiconductor substrate；?
Form stacked structure and the channel structure through the stacked structure in semiconductor substrate, the channel structure include along perpendicular to
The channel layer and leakage doped region and additional dopings at the top of the channel structure that semiconductor substrate surface direction extends
Area；The additional dopings area is located at the side of the leakage doped region, and the leakage doped region and additional dopings area are covered in portion
Divide on the channel layer, the conduction type in the additional dopings area is opposite with the leakage conduction type of doped region.The side
Method improves the performance of 3D-NAND flash memory.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Fig. 9 is the structural schematic diagram of 3D-NAND flash memory forming process in one embodiment of the invention.
With reference to Fig. 2, semiconductor substrate 200 is provided.
The material of the semiconductor substrate 200 includes monocrystalline silicon or polysilicon.
There is trap ion, the conduction type of the trap ion is adulterated with the leakage being subsequently formed in the semiconductor substrate 200
The conduction type in area is identical.
In the present embodiment, further includes: form metal substrate 201, the metal substrate 201 is located at the semiconductor substrate
200 bottom.
The material of the metal substrate 201 includes metal silicide materials, such as WSi.
Then, stacked structure and the channel structure through the stacked structure, the ditch are formed on semiconductor substrate 200
Road structure includes along the channel layer extended perpendicular to 200 surface direction of semiconductor substrate and being located at the top of the channel structure
Leakage doped region and additional dopings area；The additional dopings area be located at it is described leakage doped region side, and the leakage doped region with
Additional dopings area is covered on the channel layer of part, the conduction type in the additional dopings area and the leakage doped region
Conduction type is opposite.
Lower mask body introduces the step of forming the stacked structure, channel structure, leakage doped region and additional dopings area.
With continued reference to Fig. 2, compound medium layer 210 is formed on semiconductor substrate 200, and the compound medium layer 210 includes
The sacrificial layer 211 and insulating layer 212 of several layers intersecting, the top layer and bottom of compound medium layer 210 are insulating layer 212.
Each layer is laminated from bottom to top in the compound medium layer 210, and the direction of each layer stackup is vertical in compound medium layer 210
In the surface of semiconductor substrate 200.
In the present embodiment, the material of the insulating layer 212 is silica, and the material of the sacrificial layer 211 is silicon nitride.
The technique for forming insulating layer 212 is depositing operation, such as plasma activated chemical vapour deposition technique, sub-atmospheric pressure chemistry
Gas-phase deposition or low-pressure chemical vapor deposition process.The technique for forming sacrificial layer 211 is depositing operation, such as plasma
Chemical vapor deposition process, sub-atmospheric pressure chemical vapor deposition process or low-pressure chemical vapor deposition process.
With reference to Fig. 3, channel hole 220 is formed in the compound medium layer 210.
The technique for forming the channel hole 220 includes anisotropy dry carving technology.
With reference to Fig. 4, original trench structure is formed in the channel hole 220.
The original trench structure includes memory layer 241, channel layer 242, channel dielectric layer 243 and semiconductor articulamentum
244, the channel layer 242 and the channel dielectric layer 243 extend along perpendicular to 200 surface direction of semiconductor substrate, described
Semiconductor articulamentum 244 is located at the top surface of channel dielectric layer 243, and the channel layer 242 is located at the channel dielectric layer 243
With the outside of the semiconductor articulamentum 244；The memory layer 241 is located at the outside of the channel layer 242.
The memory layer 241 extends along perpendicular to 200 surface direction of semiconductor substrate.
The memory layer 241 includes block media layer, accumulation layer and tunneling medium layer, the block media layer, storage
Layer and tunneling medium layer are stacked gradually perpendicular to channel structure side wall and from outside channel structure to the direction in channel structure.
The block media layer and the material of the tunneling medium layer are silica, and the material of the accumulation layer is nitridation
Silicon.
The material of the channel layer 242 is polysilicon.
The channel layer 242 is identical as the material of semiconductor articulamentum 244.
With reference to Fig. 5, using the first ion implantation technology in the semiconductor articulamentum 244 of part and semiconductor connect
It connects and forms leakage doped region 251 in the part channel layer 242 of 244 side of layer；Using the second ion implantation technology in part institute
State in semiconductor articulamentum 244 and the part of 244 side of the semiconductor articulamentum channel layer 242 in form additional dopings
Area 252.
After carrying out the first ion implantation technology, the second ion implantation technology is carried out；Alternatively, carrying out the second ion implantation technology
Afterwards, the first ion implantation technology is carried out.
At this point, channel structure is formd in the channel hole 220, the leakage doped region 251 and 252, additional dopings area
In the top of channel structure.
The channel structure includes channel layer 242, channel dielectric layer 243, memory layer 241 and leakage 251 and of doped region
Additional dopings area 252.
The additional dopings area 252 is located at the side of the leakage doped region 251, and the leakage doped region 251 is mixed with additional
Miscellaneous area 252 is covered on the channel layer 242 of part, and the conduction type in the additional dopings area 252 and the leakage are adulterated
The conduction type in area 251 is opposite.
The leakage doped region 251 constitutes the drain region of 3D-NAND flash memory.
When the type of the 3D-NAND flash memory is N-type, the conduction type of the leakage doped region 251 is N-type, described attached
The conduction type for adding doped region 252 is p-type.
When the type of the 3D-NAND flash memory is p-type, the conduction type of the leakage doped region 251 is p-type, described attached
The conduction type for adding doped region 252 is N-type.
There are additional ions, the concentration of the additional ions is 10E18atom/cm in the additional dopings area 2523~
10E21atom/cm3。
The additional dopings area 252 is projected in the area on 200 surface of semiconductor substrate and the leakage doped region 251 is projected in
The area ratio value on 200 surface of semiconductor substrate is 4/5~6/5.
The additional dopings area 252 and the leakage doped region 251 are adjacent.
The effect in the additional dopings area 252 includes: when the type of the 3D-NAND flash memory is N-type, in 3D-NAND
When executing erasing operation, hole is injected into channel layer 242 by additional dopings area 252, and then passes through tunneling medium layer and enter storage
In layer, the electronics in hole and accumulation layer is compound；When the type of the 3D-NAND flash memory is p-type, wiping is executed in 3D-NAND
When except operation, electronics is injected into channel layer 242 by additional dopings area 252, and then passes through tunneling medium layer and enter in accumulation layer, electricity
Hole-recombination in son and accumulation layer.
When 3D-NAND executes erasing operation, additional dopings area 252 is capable of providing more sons and is injected into channel layer 242, in turn
Enter in accumulation layer across tunneling medium layer, realizes the erasing to the charge stored in accumulation layer.Therefore, in erase process,
Electric current is relatively large, and efficiency of erasing is high.
With reference to Fig. 6, top layer dielectric layer 260 is formed on the channel structure and the compound medium layer 210.
The material of the top layer dielectric layer 260 is silica, silicon oxynitride or silicon oxide carbide.Form the top layer dielectric layer
260 technique is depositing operation, as plasma activated chemical vapour deposition technique, atom layer deposition process, low pressure chemical phase are heavy
Product technique or sub- aumospheric pressure cvd technique.
With reference to Fig. 7, the grid separate slot 270 for running through top layer dielectric layer 260 and the compound medium layer 210 is formed.
In the present embodiment, when read operation, without forming inversion layer in semiconductor substrate 200, correspondingly, being not necessarily to
Line doped layer in source is formed in the semiconductor substrate 200 of 270 bottom of grid separate slot, is reduced processing step in this way, is reduced work
Skill cost.
With reference to Fig. 8, after forming the grid separate slot 270, sacrificial layer 211 is removed, forms opening 280.
With reference to Fig. 9, conductive layer 290 is formed in the opening 280 (referring to Fig. 8).
Material layer between the insulating layer 212 and isolated from adjacent layer 212 constitutes stacked structure 300.In the present embodiment,
Stacked structure 300 includes insulating layer 212 and conductive layer 290.
It is mostly sub without relying on semiconductor substrate injection since 3D-NAND flash memory is in erasing operation, therefore semiconductor substrate
The selection of 200 conduction type is unrestricted.When 3D-NAND flash memory is N-type, the conduction type of semiconductor substrate 200 is optional
It is selected as N-type, when 3D-NAND flash memory is p-type, the conduction type of semiconductor substrate 200 may be selected to be p-type.Make 3D- in this way
The read operation of nand flash memory is convenient, is in particular in: when read operation, without forming transoid in semiconductor substrate 200
Layer, operation voltage can reduce, so that the more convenient execution of read operation.To sum up, the performance of 3D-NAND flash memory is improved.
The present invention also provides a kind of 3D-NAND flash memories formed using the above method, referring to FIG. 9, including: semiconductor lining
Bottom 200；Stacked structure 300 in semiconductor substrate 200；Through the channel structure of the stacked structure 300, the channel
Structure includes along the channel layer 242 extended perpendicular to 200 surface direction of semiconductor substrate and being located at the top of the channel structure
Leakage doped region 251 and additional dopings area 252；The additional dopings area 252 is located at the side of the leakage doped region 251, and institute
It states leakage doped region 251 and additional dopings area 252 is covered on the channel layer of part, the additional dopings area 252 is led
Electric type is opposite with the leakage conduction type of doped region 251.
When the type of the 3D-NAND flash memory is N-type, the conduction type of the leakage doped region 251 is N-type, described attached
The conduction type for adding doped region 252 is p-type.
When the type of the 3D-NAND flash memory is p-type, the conduction type of the leakage doped region 251 is p-type, described attached
The conduction type for adding doped region 252 is N-type.
There are additional ions, the concentration of the additional ions is 10E18atom/cm in the additional dopings area 2523~
10E21atom/cm3。
The additional dopings area 252 is projected in the area on 200 surface of semiconductor substrate and the leakage doped region 251 is projected in
The area ratio value on 200 surface of semiconductor substrate is 4/5~6/5.
The additional dopings area 252 and the leakage doped region 251 are adjacent.
There is trap ion, the conduction type of the trap ion and the leakage doped region 251 in the semiconductor substrate 200
Conduction type is identical.
The channel structure further include: along the memory layer 241 extended perpendicular to 200 surface direction of semiconductor substrate, institute
State the outside that memory layer 241 is located at the channel layer 242；The memory layer 241 includes block media layer, accumulation layer and tunnel
Dielectric layer is worn, the block media layer, accumulation layer and tunneling medium layer are perpendicular to channel structure side wall and from outside channel structure
Direction in channel structure stacks gradually.
The 3D-NAND flash memory further include: the metal substrate 201 positioned at 200 bottom of semiconductor substrate.
The material of the metal substrate 201 includes metal silicide materials, and the metal silicide materials include WSi.
The material of the semiconductor substrate 200 includes polysilicon or monocrystalline silicon.
In 3D-NAND flash memory provided in this embodiment, since 3D-NAND flash memory is in erasing operation, partly led without relying on
The injection of body substrate 200 is mostly sub, therefore the selection of the conduction type of semiconductor substrate 200 is unrestricted.When 3D-NAND flash memory is N
When type, the conduction type of semiconductor substrate 200 may be selected to be N-type, when 3D-NAND flash memory is p-type, semiconductor substrate 200
Conduction type may be selected to be p-type.Make the read operation of 3D-NAND flash memory convenient in this way, be in particular in: read operation when
It waits, without forming inversion layer in semiconductor substrate 200, operation voltage can be reduced, so that the more convenient execution of read operation.It is comprehensive
On, improve the performance of 3D-NAND flash memory.
When 3D-NAND flash memory is N-type, the conduction type of semiconductor substrate 200 may be selected to be N-type, semiconductor substrate 200
Resistivity reduce.
Another embodiment of the present invention also provides a kind of forming method of 3D-NAND flash memory, the present embodiment and previous embodiment
Difference be: the channel structure of formation further include positioned at it is described leakage doped region and additional dopings area upper surface metal silicide
Layer.
It is schematic diagram on the basis of Fig. 5 with reference to Figure 10, Figure 10, carries out silication technique for metal processing, is adulterated in the leakage
Area 251 and 252 upper surface of additional dopings area form metal silicide layer 310.
Extended meeting forms plug on metal silicide layer 310 afterwards, and the metal silicide layer 310 can reduce plug and leakage
The contact resistance between contact resistance and reduction plug and additional dopings area 252 between doped region 251；Secondly, plug with
Metal silicide layer 310 contacts, to realize that plug is electrically connected with leakage doped region 251 and additional dopings area 252 respectively, therefore
It is deviated without considering the problems of plug and leaking the contact position between doped region 251 and additional dopings area 252.
The silication technique for metal processing includes: to form metal in leakage doped region 251 and 252 upper surface of additional dopings area
Layer；Metal layer is made annealing treatment, reacts metal layer with part leakage doped region 251 and part additional dopings area 252 respectively,
Form metal silicide layer 310.
With reference to Figure 11, top layer dielectric layer 360 is formed on channel structure and compound medium layer；It is formed and runs through top layer dielectric layer
360 and the compound medium layer 210 grid separate slot 370.
With reference to Figure 12, after forming the grid separate slot 370, sacrificial layer 211 is removed, forms opening 380.
With reference to Figure 13, conductive layer 390 is formed in the opening 380.
Correspondingly, the present embodiment also provides a kind of 3D-NAND flash memory formed using the above method, the 3D- of the present embodiment
The difference of the 3D-NAND flash memory of nand flash memory and previous embodiment is: the channel structure further include: is located at the leakage and adulterates
The metal silicide layer 310 of 252 upper surface of area 251 and additional dopings area.It closes identical with previous embodiment in this present embodiment
Part, be no longer described in detail.
The present invention also provides the working methods of above-mentioned 3D-NAND flash memory, carry out by example of the 3D-NAND flash memory in Fig. 9
Illustrate, the working method of 3D-NAND flash memory includes: carry out erasing operation, during erasing operation, by the additional dopings
Area 252 provides more sons and is injected into channel layer 242.
Specifically, providing more sons during erasing operation by the additional dopings area 252 and being injected into channel layer 242
In, and then pass through tunneling medium layer and enter in accumulation layer, it is compound with stored charge in accumulation layer.
It should be noted that more sons that the additional dopings area 252 provides are being injected into ditch during erasing operation
Can be around open-drain doped region 251 during in channel layer 242, i.e. additional dopings area 252 provides more sons and does not flow through leakage doped region
251。
The working method of the 3D-NAND flash memory further include: be programmed operation；During programming operation, by institute
It states leakage doped region 251 more sons are provided to be injected into channel layer 242, and then passes through tunneling medium layer and enter in accumulation layer.
When the conduction type of semiconductor substrate is consistent with the leakage conduction type of doped region 251, it is being programmed operation
In the process, semiconductor substrate can also provide more sons and be injected into channel layer 242, and then passes through tunneling medium layer and enter accumulation layer
In.
It should be noted that more sons that the leakage doped region 251 provides are being injected into channel during programming operation
Additional dopings area 252 can be got around during in floor 242, i.e., leakage doped region 251 provides more sons and do not flow through additional dopings area
252。
The working method of the 3D-NAND flash memory further include: be read；During read operation, by institute
Leakage doped region 251 is stated more sons are provided to be injected into channel.
In layer 242, and flow through semiconductor substrate 200.Specifically, during read operation, by the leakage doped region
251 provide more sons followed by channel layer 242, semiconductor substrate 200 and metal substrate 201.
It should be noted that more sons that the leakage doped region 251 provides are being injected into channel during read operation
Additional dopings area 252 can be got around during in floor 242, i.e., leakage doped region 251 provides more sons and do not flow through additional dopings area
252。
The working method of 3D-NAND flash memory is no longer described in detail referring to the working method of 3D-NAND flash memory in Fig. 9 in Figure 13.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (10)
1. a kind of forming method of 3D-NAND flash memory characterized by comprising
Semiconductor substrate is provided；
It forms stacked structure on a semiconductor substrate and the channel structure through the stacked structure, the channel structure includes edge
The channel layer and leakage doped region at the top of the channel structure that extend perpendicular to semiconductor substrate surface direction and additional
Doped region；
The additional dopings area is located at the side of the leakage doped region, and the leakage doped region and additional dopings area are covered in portion
Divide on the channel layer, the conduction type in the additional dopings area is opposite with the leakage conduction type of doped region.
2. the forming method of 3D-NAND flash memory according to claim 1, which is characterized in that form the stacked structure, ditch
Road structure, leakage doped region and the step of additional dopings area include:
Compound medium layer is formed on the semiconductor substrate, and the compound medium layer includes the sacrificial layer of several layers intersecting
And insulating layer；
Channel hole is formed in the compound medium layer；
The channel structure is formed in the channel hole；
After forming the channel structure, sacrificial layer is removed, forms opening；
Conductive layer is formed in said opening, and the stacked structure includes insulating layer and conductive layer.
3. the forming method of 3D-NAND flash memory according to claim 2, which is characterized in that formed in the channel hole
The step of channel structure includes:
Original trench structure is formed in the channel hole, the original trench structure includes channel layer, channel dielectric layer and half
Conductor articulamentum, the channel layer and the channel dielectric layer extend along perpendicular to semiconductor substrate surface direction, and described half
Conductor articulamentum is located at the top surface of channel dielectric layer, and the channel layer is located at the channel dielectric layer and the semiconductor connects
Connect the outside of layer；
Using the first ion implantation technology in the semiconductor articulamentum of part and the part institute of semiconductor articulamentum side
It states and forms leakage doped region in channel layer；
Using the second ion implantation technology in the semiconductor articulamentum of part and the part institute of semiconductor articulamentum side
State formation additional dopings area in channel layer.
4. the forming method of 3D-NAND flash memory according to claim 3, which is characterized in that the channel layer and semiconductor
The material of articulamentum is identical.
5. the forming method of 3D-NAND flash memory according to claim 1, which is characterized in that have in the semiconductor substrate
There is trap ion, the conduction type of the trap ion is identical as the leakage conduction type of doped region.
6. the forming method of 3D-NAND flash memory according to claim 1, which is characterized in that when the 3D-NAND flash memory
When type is N-type, the conduction type of the leakage doped region is N-type, and the conduction type in the additional dopings area is p-type.
7. the forming method of 3D-NAND flash memory according to claim 1, which is characterized in that when the 3D-NAND flash memory
When type is p-type, the conduction type of the leakage doped region is p-type, and the conduction type in the additional dopings area is N-type.
8. the forming method of 3D-NAND flash memory according to claim 1, which is characterized in that the additional dopings area projection
It is 4/5~6/ in the area ratio value that the area of semiconductor substrate surface and the leakage doped region are projected in semiconductor substrate surface
5。
9. the forming method of 3D-NAND flash memory according to claim 1, which is characterized in that further include: form metal liner
Bottom；The metal substrate is located at the bottom of the semiconductor substrate.
10. the forming method of 3D-NAND flash memory according to claim 1, which is characterized in that the channel structure also wraps
It includes: positioned at the metal silicide layer of the leakage doped region and additional dopings area upper surface.
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| CN201811147897.5A CN109300904B (en) | 2018-09-29 | 2018-09-29 | Method for forming 3D-NAND flash memory |
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| CN201811147897.5A CN109300904B (en) | 2018-09-29 | 2018-09-29 | Method for forming 3D-NAND flash memory |
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| CN106847819A (en) * | 2015-12-03 | 2017-06-13 | 上海复旦微电子集团股份有限公司 | Nand flash memory memory cell, nand flash memory and forming method thereof |
| CN108520881A (en) * | 2018-04-25 | 2018-09-11 | 长江存储科技有限责任公司 | Three-dimensional storage and its data manipulation method |
| CN108565265A (en) * | 2018-04-17 | 2018-09-21 | 长江存储科技有限责任公司 | A kind of three-dimensional storage and its data manipulation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106847819A (en) * | 2015-12-03 | 2017-06-13 | 上海复旦微电子集团股份有限公司 | Nand flash memory memory cell, nand flash memory and forming method thereof |
| CN108565265A (en) * | 2018-04-17 | 2018-09-21 | 长江存储科技有限责任公司 | A kind of three-dimensional storage and its data manipulation method |
| CN108520881A (en) * | 2018-04-25 | 2018-09-11 | 长江存储科技有限责任公司 | Three-dimensional storage and its data manipulation method |
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