CN105990092B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
- Publication number
- CN105990092B CN105990092B CN201510051526.7A CN201510051526A CN105990092B CN 105990092 B CN105990092 B CN 105990092B CN 201510051526 A CN201510051526 A CN 201510051526A CN 105990092 B CN105990092 B CN 105990092B
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor substrate
- floating gate
- polysilicon layer
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of forming methods of semiconductor structure, including：After forming tunnel layer on a semiconductor substrate, the first polysilicon layer doped with N-type ion is formed on the tunnel layer；The first polysilicon layer on the memory area is etched later, forms floating gate layer；Then, after forming the first insulating layer on the floating gate layer, the second polysilicon layer formed on the semiconductor substrate, second polysilicon layer covers the floating gate layer；Second polysilicon layer is etched, forms control grid layer on the floating gate layer, the selection grid layer for being located at the floating gate layer side is formed in the semiconductor substrate of the memory area, is formed with gap between the floating gate layer and selection grid layer.Compared to prior art, the present invention effectively simplifies the manufacturing process of the gate-division type flash memory of superficial face trench transistor structure, to reduce manufacture difficulty and process costs.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of forming methods of semiconductor structure.
Background technique
Gate-division type flash memory is a kind of common nonvolatile semiconductor memory, without erasure effect, circuit design excessively
Relatively easy and low pressure, high speed operational characteristics have become the mainstream technology of memory device, be widely used in such as intelligent
In the electronic products such as card, SIM card, microcontroller, mobile phone.
Refering to what is shown in Fig. 1, gate-division type flash memory semiconductor substrate 10；Tunnel layer 11 in semiconductor substrate 10 is located at
Floating gate 21 on the tunnel layer 11, the insulating layer 22 on floating gate 21, the control gate 23, Yi Jiwei on the insulating layer 22
In the selection grid 24 on the tunnel layer 11, and positioned at 23 side of the floating gate 21 and control gate.
In previous processes, the gate-division type flash memory is mostly buried layer channel transistor (Burried channel MOS) knot
Structure comprising：N hydrazine, N-type floating gate and N-type select grid structure；So as what gate-division type flash memory number device read or write speed was required mentions
It rises, develops a kind of gate-division type flash memory of shallow surface channel transistor (Surface channel MOS) structure now, wrap
It includes：N hydrazine, N-type floating gate and p-type selection grid, so that the threshold voltage of selection grid 24 is effectively reduced, to improve the reading of gate-division type flash memory
Writing rate.
In addition, in gate-division type flash memory in use, peripheral circuit (Periphery would generally can be arranged around it
Circuit).The peripheral circuit is mainly logic circuit, including：High voltage transistor and logic transistor, wherein the high pressure
The threshold voltage of transistor is greater than the threshold voltage of the logic transistor.The logic circuit to introduce different voltage,
It controls the gate-division type flash memory and carries out the operation such as data write-in, erasing and reading.Thus, work is manufactured in existing gate-division type flash memory
In skill, gate-division type flash memory and high threshold voltage transistors and logic transistor are often carried out simultaneously on the same semiconductor substrate
Manufacturing process.Its step that improves increases the difficulty of the gate-division type flash memory manufacture of superficial face trench transistor structure.
Fig. 2~7 are the manufacture structural schematic diagram of the gate-division type flash memory of existing superficial face trench transistor structure, existing shallow
The manufacturing method of the gate-division type flash memory of surface channel transistor structure includes：
Referring initially to Fig. 2, semiconductor substrate 100 is provided.
The semiconductor substrate 100 includes for manufacturing the first area I of gate-division type flash memory, for manufacturing high voltage transistor
Second area II, and the third region III for manufacturing logic transistor；
It is injected with N-type ion in the semiconductor substrate of the first area I, is formed with N trap (not shown)；Institute
It states and is formed with the P trap for being used to form p-type high voltage transistor in the semiconductor substrate of second area II, and be used to form N-type height
The N trap (not shown) of piezoelectric crystal；
With continued reference to Fig. 2, after forming insulating layer 110 in the semiconductor substrate 100, in the second area II and the
Form the first mask 120 on three region III and part first area I, and to the storage for not covering first mask 120
Injecting p-type ion in the I of device region forms floating gate region 101, for adjusting the control being subsequently formed above the floating gate region
The threshold voltage of grid；
It is covered referring next to Fig. 3 after forming the second mask 121 on the second area II and third region III with second
Mould 121 is that mask re-injects P-type ion into the semiconductor substrate 100 of first area I, forms memory area 102, is used for
Further adjust the threshold voltage of the floating gate being subsequently formed and selection grid；
With reference to Fig. 4, after removing the insulating layer on the memory area 102, in partly leading for the memory area 102
Tunnel layer 112 is formed in body substrate 100, retains the insulating layer 111 on the second area II and third region III.
In conjunction with reference Fig. 5, after forming intrinsically polysilicon layer 130 in the semiconductor substrate 100, in the intrinsic polycrystalline
Third mask 122 is formed on silicon layer 130, exposes the intrinsically polysilicon layer of the upper side of floating gate region 101, and to the intrinsic of exposing
Injecting p-type ion in polysilicon layer 130 forms selection grid polysilicon region 131.
It is formed on the selection grid polysilicon region 131 after removing the third mask 122 in conjunction with reference Fig. 6
4th mask 123, and be that mask injects N type ion into remaining polysilicon layer with the 4th mask 123, it is formed in not
With region doped with the polysilicon layer 132 of different type ion；
It is formed after etching is doped with the polysilicon layer 132 of ion doped with N type ion in conjunction with reference Fig. 6 and Fig. 7
Floating gate 134 and selection grid 133 doped with P-type ion, while forming on the second area II grid doped with N-type ion
Pole structure 135, the gate structure 135 are used to form high voltage transistor；
After forming selection grid 133, insulating layer is formed on the floating gate 134 and selection grid 133, and on floating gate 134
Insulating layer on form the structures such as control gate；
And then in forming another layer of polysilicon layer (not shown) in the semiconductor substrate 100, then etch described
Polysilicon layer forms logical device on the III of third region.
As described above, in the existing work for the floating gate and selection grid for forming the gate-division type flash memory of superficial face trench transistor structure
In skill, with reference to Fig. 5 and Fig. 6, because needing after forming intrinsically polysilicon layer 130 on a semiconductor substrate to intrinsically polysilicon layer
Repeatedly different types of ion implanting step is carried out in different zones, is subsequently used for forming the N-type doped with different type ion
Floating gate and p-type selection grid, and in multiple ion implanting step, it is also necessary to the shape of multiple masks is carried out in intrinsically polysilicon layer
At with removal step, the manufacturing process of the gate-division type flash memory of existing superficial face trench transistor structure is complicated, and process costs are big.
For this purpose, the manufacturing process for how simplifying the gate-division type flash memory of superficial face trench transistor structure is those skilled in the art
The problem of member's urgent need to resolve.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of semiconductor structure, to simplify shallow surface channel crystal
The gate-division type flash memory manufacturing process of pipe structure.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure,
Semiconductor substrate is provided, the semiconductor substrate includes being used to form the first area of gate-division type flash memory；
Tunnel layer is formed on the semiconductor substrate；
The first polysilicon layer doped with N-type ion is formed on the tunnel layer；
The first polysilicon layer on the first area is etched, floating gate layer is formed；
The first insulating layer is formed on the floating gate layer；
The second polysilicon layer is covered on first insulating layer and semiconductor substrate；
Second polysilicon layer is etched, forms control grid layer on the floating gate layer, and in the floating gate layer side
Selection grid layer is formed in the semiconductor substrate of first area；
The doped p-type ion into the selection grid layer.
Optionally, it after etching first polysilicon layer and forming floating gate layer, is formed before first insulating layer, institute
The forming method for stating semiconductor structure further includes：The tunnel layer that removal is located at the floating gate layer periphery exposes the semiconductor substrate
Surface forms second insulating layer on the semiconductor substrate surface of exposing later in the first area；
Include in the step of forming the first insulating layer on the floating gate layer：First insulating layer is set also to be covered on described
On two insulating layers.
Optionally, the second insulating layer is silicon oxide layer.
Optionally, the technique for forming the second insulating layer is thermal oxidation technology.
Optionally, the second insulating layer with a thickness of
Optionally, the step of the first insulating layer of formation includes：The first silicon oxide layer, nitrogen are sequentially formed on the floating gate layer
SiClx layer and the second silicon oxide layer.
Optionally, second polysilicon layer is etched, forming the step of selecting grid layer includes：
Second polysilicon layer is etched, forms control grid layer on the floating gate layer, while on the first area,
Form the third polysilicon layer for being located at the side of the floating gate layer；Between being formed between the third polysilicon layer and the floating gate layer
Gap；
The third polysilicon layer is etched, the selection grid layer is formed.
Optionally, second polysilicon layer is etched, after forming the control grid layer and third polysilicon layer, described the
First insulating layer described in one exposed portion on region；
Before etching the third polysilicon layer, the forming method further includes：
First insulating layer exposed on the first area and corresponding second insulating layer are removed, to expose described half
Conductor substrate；
Third insulating layer is formed in the semiconductor substrate surface of exposing.
Optionally, the material of the third insulating layer is silica.
Optionally, the third insulating layer with a thickness of
Optionally, the forming method of the third insulating layer is thermal oxidation technology.
Optionally, the semiconductor substrate further includes second area, is used to form the first device；
Before forming first polysilicon layer, the forming method further includes that the 4th is formed on the second area
Insulating layer；
The step of forming first polysilicon layer further include：First polysilicon layer is also covered on the second area
On；
Etching the step of first polysilicon layer is to form floating gate layer further includes：Etch first on the second area
Polysilicon layer forms first grid layer；
Include in the step of forming the first insulating layer on the floating gate layer：First insulating layer is set also to be covered on described
On one grid layer；
The step of forming the second polysilicon layer on the semiconductor substrate include：Make the second polysilicon layer covering institute
Second area is stated, and second polysilicon layer covers the first grid layer；
Etching the step of second polysilicon layer forms control grid layer further includes：It etches on the second area simultaneously
Second polysilicon layer forms the second polycrystal layer on the first grid layer.
Optionally, the semiconductor substrate further includes third region, is used to form logical device；
After forming the floating gate layer, before forming the second polysilicon layer, the forming method of the semiconductor structure further includes：
Semiconductor substrate surface in the third region forms the 5th insulating layer；
The step of forming the second polysilicon layer on the semiconductor substrate include：Make the second polysilicon layer covering institute
State third region；
Etching the step of second polysilicon layer forms selection grid layer further includes：It etches on the third region simultaneously
Second polysilicon layer forms second grid layer.
Optionally, include the step of doped p-type ion into the selection grid layer：
The injecting p-type ion into the selection grid layer, while injecting p-type in the semiconductor substrate into the first area
Ion is to form source electrode and drain electrode in the semiconductor substrate of the floating gate layer two sides.
Optionally, first device includes the first transistor, and into the selection grid layer, the step of doped p-type ion is wrapped
It includes：
The injecting p-type ion into the selection grid layer, while the doped p-type ion into the semiconductor substrate form the
The source electrode and drain electrode of one transistor.
Optionally, the logical device includes logic transistor, and into the selection grid layer, the step of doped p-type ion is wrapped
It includes：
The injecting p-type ion into the selection grid layer, while the doped p-type ion into the semiconductor substrate, formation are patrolled
Collect the source electrode and drain electrode of transistor.
Compared with prior art, technical solution of the present invention has the following advantages that：
After forming tunnel layer on the first area of semiconductor substrate, the doped with N-type ion is formed on the tunneling layer
One polysilicon layer, the floating gate layer of formation doping N type ion after etching the first polysilicon layer on the first area, and
After forming the first insulating layer on the floating gate layer, the second polysilicon layer, the second polysilicon are formed on the memory area
Layer covers the floating gate layer；After etching second polysilicon layer, control grid layer is formed on the floating gate layer, described floating
Grid layer side forms selection grid layer；The injecting p-type ion into the selection grid layer again later, is used to form doped with P-type ion
Selection grid layer, and then be used to form the gate-division type flash memory of superficial face trench transistor structure.
Compared to the manufacturing process of the gate-division type flash memory of existing superficial face trench transistor structure, the present invention provides semiconductor
In the forming method of structure, during forming the floating gate and P-type ion selection grid doped with N-type ion, eliminate to this
It levies and carries out repeatedly different types of ion implanting step in polysilicon layer different zones, and in multiple ion implantation process,
The formation and removal step that multiple masks are carried out in intrinsically polysilicon layer, to effectively simplify superficial face trench transistor structure
Gate-division type flash memory manufacturing process, reduce process costs.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of gate-division type flash memory；
Fig. 2 to Fig. 7 is the semiconductor in each step in the existing gate-division type flash memory technique for forming surface gate structure
The schematic diagram of the section structure of structure；
Fig. 8 to Figure 19 is cuing open for the semiconductor structure in each step of one embodiment of forming method of semiconductor structure of the present invention
Face structural schematic diagram.
Specific embodiment
As stated in the background art, compared to the gate-division type flash memory of buried layer trench transistor structure, shallow surface channel transistor
The gate-division type flash memory of structure can effectively reduce the threshold voltage of the control gate of gate-division type flash memory, to improve the reading of gate-division type flash memory
Writing rate.
But in the manufacturing process of the gate-division type flash memory of existing superficial face trench transistor structure, this is formed in semiconductor substrate
After levying polysilicon layer, need to carry out repeatedly different types of ion implanting step into intrinsically polysilicon layer different zones, it is subsequent
It is used to form the N-type floating gate and p-type selection grid doped with different type ion；And in multiple ion implanting step, it is also necessary to
The formation and removal step, above steps very complicated that multiple masks are carried out in intrinsically polysilicon layer increase superficial face
The manufacture difficulty and cost of the gate-division type flash memory of trench transistor structure.
For this purpose, superficial face trench transistor structure can be simplified the present invention provides a kind of forming method of semiconductor structure
Gate-division type flash memory manufacturing process, reduce process costs.
The forming method of semiconductor structure provided by the invention, including：
Semiconductor substrate is provided, the semiconductor substrate includes being used to form the first area of gate-division type flash memory；Described
Tunnel layer is formed in semiconductor substrate, and the first polysilicon doped with N-type ion is formed on the tunnel layer；It etches later
The first polysilicon layer on the first area forms floating gate layer；
Then, the first insulating layer, and the shape on first insulating layer and semiconductor substrate are formed on the floating gate layer
At the second polysilicon layer；Second polysilicon layer is etched, forms control grid layer on the floating gate layer, and in the floating gate
Selection grid layer is formed in the first area semiconductor substrate of layer side；The doped p-type ion into the selection grid layer again later.
In the present invention, after the first polysilicon layer of etching doped N-type ion forms floating gate layer, in being formed in semiconductor substrate
Second polysilicon layer, and etch second polysilicon layer and form selection grid layer, the backward selection grid layer in doped p-type from
Son.
Compared to prior art, in the forming method of semiconductor structure provided by the invention, formed doped with N-type ion
Floating gate and P-type ion selection grid during, eliminate and carry out multiple different type into intrinsically polysilicon layer different zones
Ion implanting step, and in multiple ion implantation process, carried out in intrinsically polysilicon layer multiple masks formation and
Step is removed, to effectively simplify the manufacturing process of the gate-division type flash memory of superficial face trench transistor structure, reduces process costs.
To make the above purposes, features and advantages of the invention more obvious and understandable, shallow to have with reference to the accompanying drawing
Gate-division type flash memory, high voltage transistor (HV Device) and the logical device (Logic Device) of surface channel transistor structure
Manufacturing method be embodiment detailed process of the invention is described in detail.
Fig. 8 to Figure 19 is the section knot schematic diagram of the forming process of the semiconductor structure of the embodiment of the present invention.
Referring initially to Fig. 8, semiconductor substrate 200 is provided.
In the present embodiment, the semiconductor substrate 200 is silicon substrate.But in the other embodiments in addition to the present embodiment, institute
Stating semiconductor substrate 200 can also be germanium substrate, silicon-Germanium substrate or insulator substrates.Semiconductor substrate 200 in this field is equal
Suitable for the present invention, the present invention to the type of the semiconductor substrate 200 without limitation.
In the present embodiment, the semiconductor substrate 200 includes first area I, second area II and the third being set side by side
Region III.The first area I is the gate-division type flash memory for being used to form superficial face trench transistor structure, and second area II is used
In forming the first device, the third region III is the logical device region for being used to form logical device.
In the present embodiment, first device includes the first transistor, and the logical device includes logic transistor.Institute
Stating the first transistor can be used as high voltage transistor, and the threshold voltage of the first transistor is greater than the threshold value electricity of the logic transistor
Pressure.
In the present embodiment, it is formed in the semiconductor substrate 200 of first area I first well region (not indicated in figure), it is described
First well region is the N-type well region for being injected with the N-type ions such as phosphorus (P)；It is formed in the semiconductor substrate 200 of the second area II
There are multiple N-type well regions and P type trap zone, respectively to form N-type high voltage transistor and p-type high voltage transistor；The third region
Well region has had not yet been formed in II at this time.
In the present embodiment, fleet plough groove isolation structure (Shallow Trench is formed in the semiconductor substrate 200
Isolation, STI) (unlabeled in figure), the adjacent well region for being isolated in each different region and each region, with
Realize the electric isolution being subsequently formed between each semiconductor devices in the semiconductor substrate 200.Fleet plough groove isolation structure is filled out
Filling material can be one or more of silica, silicon nitride, silicon oxynitride.
In other embodiments in addition to the present embodiment, can also it be equipped in addition to STI structure in the semiconductor substrate 200
Other isolation structures, to realize the electric isolution being subsequently formed between each semiconductor devices.Type of the present invention to the isolation structure
And without limitation.
In addition, being additionally provided with the classes of semiconductors member device such as transistor and metal interconnection structure in the semiconductor substrate 200
Part, above structure do not influence protection scope of the present invention, and the present invention does not limit the structure of the semiconductor substrate 200
It is fixed.
With continued reference to Fig. 8, is formed in the semiconductor substrate 200 and cover the first area I, second area II and the
The 4th insulating layer 210 of three region III, the 4th insulating layer 210 are used to form grid and semiconductor in the first transistor and serve as a contrast
Gate dielectric layer between bottom 200.
Later, the first ion range 201 is formed in the first well region of the first area I, and is located at described first
The second ion range 202 in ion range 201；
In the present embodiment, the forming step of first ion range 201 and the second ion range 202 includes：
The injecting p-type ion into first well region, to form second ion range 202, second ion area
Domain 202 is used to adjust the threshold voltage of control gate；Later, re-inject P-type ion into first well region, formed first from
Subregion 201, first ion range 201 is for further adjusting the control gate of gate-division type flash memory and the threshold value electricity of selection grid
Pressure.
In the present embodiment, the 4th insulating layer 210 is silicon oxide layer, and forming method is chosen as thermal oxidation technology, chemistry
The methods of vapor deposition or atomic layer deposition.The present invention to the forming method of the 4th insulating layer 210 without limitation.
Optionally, the 4th insulating layer 210 with a thickness of
Referring next to Fig. 9, later, the 4th insulating layer 210 on the first area I is removed, expose the first area I
The surface of semiconductor substrate 200；And tunnel layer 211 is formed on the surface of the first area I semiconductor substrate 200.
In the present embodiment, the tunnel layer 211 is silicon oxide layer, and forming method is thermal oxidation technology
Optionally, the tunnel layer 211 with a thickness of
With reference to Figure 10, after forming the tunnel layer 211, the first polysilicon is formed on the surface of the semiconductor substrate 200
Layer 300, first polysilicon layer 300 is doped with N-type ion.
In the present embodiment, the N-type ion includes phosphorus (P) ion.But it is described in the other embodiments in addition to the present embodiment
N-type ion can also be other ions such as arsenic (As), and the present invention is specifically chosen without limitation the N-type ion.
In the present embodiment, first polysilicon layer 300 covers the first area I, second area II and third region
III。
In the present embodiment, the method for first polysilicon layer 300 is chemical vapor deposition (Chemical Vapor
Deposition, abbreviation CVD).
The forming process of first polysilicon layer 300 may include, while be passed through silicon source gas and phosphorus source gas, thus shape
At the first polysilicon layer doped with phosphorus.
It, can also be by being initially formed intrinsically polysilicon layer, later by the methods of ion implanting in institute but in addition to the present embodiment
It states and injects phosphonium ion in intrinsically polysilicon layer, to form the first polysilicon layer doped with phosphorus.Above-mentioned simple change is at this
In the protection scope of invention.
With reference to Figure 11, first polysilicon layer 300 is etched, forms floating gate layer 310 on the first area I.
In the present embodiment, floating gate layer 310 is located at 202 top of the second ion range.
In the present embodiment, while etching first polysilicon layer 300 to form floating gate layer 310, institute is etched
The first polysilicon layer 300 on second area II is stated, forms first grid layer 320 on the second area II.
The first grid layer 320 is used to form the grid of the first transistor.
In the present embodiment, doped with N-type ion in the floating gate layer 310 and first grid layer 320.
1 is continued to refer to figure 1, after etching first polysilicon layer 300 to form the floating gate layer 310, exposed portion institute
Tunnel layer is stated, which is damaged when etching first polysilicon layer 300, and then influences point being subsequently formed
The performance of gate flash memory.
For this purpose, after forming the floating gate layer 310, exposing on the etching removal first area II in the present embodiment
Tunnel layer 211, to expose 200 surface of semiconductor substrate.
Referring again to Figure 12, the surface for the semiconductor substrate 200 exposed on the first area I forms second insulating layer
212。
In the present embodiment, the second insulating layer 212 is silicon oxide layer.
Optionally, the forming method of the second insulating layer 212 is thermal oxidation technology.
Still optionally further, the second insulating layer 212 with a thickness of
It is worth noting that, can be formed on the first area I multiple floating after etching first polysilicon layer 300
Grid layer 310, it is subsequent to form multiple gate-division type flash memories；Multiple first grids are formed on the second area II
Layer, to form each transistor (including N-type high voltage transistor and p-type high voltage transistor) of multiple first devices, but this implementation
Example illustrates only the first grid layer and floating gate layer for ease of description, but the floating gate layer and first grid layer
Simultaneously the scope of protection of the present invention is not limited for quantity.
With reference to Figure 13, after forming the floating gate layer 310, the first insulating layer 400 is formed on the floating gate layer 310.It is described
First insulating layer 400 is as the insulating layer in the gate-division type flash memory being subsequently formed, between floating gate and control gate.
In the present embodiment, first insulating layer 400 is covered on the second insulating layer 212, the 4th insulating layer 210 and institute
It states on first grid layer 320.
In the present embodiment, the forming step of first insulating layer 400 includes：
Sequentially formed in the semiconductor substrate 200 first silicon oxide layer (oxide), silicon nitride layer (nitride) with
And second silicon oxide layer (oxide).First silicon oxide layer, silicon nitride layer and the second silicon oxide layer form the first insulating layer
400, make 400 ONO of the first insulating layer (oxide- nitride-oxide) the layer structure.
Optionally, first oxide skin(coating) with a thickness ofLeft and right, nitride layer with a thickness ofLeft and right, the
Dioxide layer with a thickness ofLeft and right；The formation side of first oxide skin(coating), nitride layer and the second oxide skin(coating)
Method is chemical vapor deposition.The structure and forming method of the ONO layer are the mature technology of this field, and details are not described herein.
It optionally, can be to the difference of the semiconductor substrate 200 of third region III after forming first insulating layer 400
N-type ion and P-type ion are injected separately into region, so that multiple N-type well regions and P type well region are formed with, respectively to form N
Type logic transistor and p-type logic transistor.Above structure is that details are not described herein for this field mature technology.
Then, with reference to Figure 14, removal is located at the first insulating layer 400 and the 4th insulating layer on the third region III, dew
The semiconductor substrate 200 of the third region III out；And the 200 surface shape of semiconductor substrate exposed in the third region III
At the 5th insulating layer 220.5th insulating layer 220 can be used as the gate dielectric layer in the logic transistor being subsequently formed.
In the present embodiment, the 5th insulating layer 220 is silicon oxide layer.
Still optionally further, the forming method of the 5th insulating layer 220 is thermal oxidation technology.
With reference to Figure 15, later, the second polysilicon layer 500 is formed in the semiconductor substrate 200.
In the present embodiment, second polysilicon layer 500 is intrinsically polysilicon layer, and forming method is chemical vapor deposition.
In the present embodiment, second polysilicon layer 500 covers the floating gate layer 310, the first grid layer 320, with
And the surface of the semiconductor substrate 200 of the first area I, second area II and third region III.
Later, in conjunction with reference Figure 16~Figure 18, second polysilicon layer is etched, forms control on the floating gate layer 310
Grid layer 511 processed forms the selection grid layer for being located at 310 side of floating gate layer in the semiconductor substrate 200 of the first area I
512, gap 601 is formed between the floating gate layer 310 and selection grid layer 512.
In the present embodiment, forms the control grid layer 511 and include the step of selecting grid layer 512：
Referring initially to Figure 16, second polysilicon layer 500 is etched, forms control grid layer 511 on the floating gate layer 310,
Simultaneously on the first area I, the third polysilicon layer 510 for being located at the side of the floating gate layer 310 is formed, in the third
Gap 601 is formed between polysilicon layer 510 and the floating gate layer 310.
In the present embodiment, while etching second polysilicon layer 500 forms control grid layer 511, described
Form the second polycrystal layer 520 on first grid layer 320, second polycrystal layer 520 is subsequent to can be used to form electrical connection described the
The interconnecting construction of one grid layer 320；Moreover, forming the 4th polysilicon layer 530 also on the third region III.
6 are continued to refer to figure 1, after forming the control grid layer 511, is etched in the first area I, the first of exposing is absolutely
Second insulating layer 212 below edge layer 400, and the first insulating layer 400 of exposing, to expose the semiconductor substrate 200.
In conjunction with reference Figure 17, third insulating layer 230 is formed on 200 surface of the semiconductor substrate of exposing.
In the present embodiment, the third insulating layer 230 is silicon oxide layer.
Optionally, the third insulating layer 230 with a thickness of
Still optionally further, the forming method of the third insulating layer 230 is thermal oxidation technology.
It etches after second polysilicon layer 500 forms the control grid layer 511, the I semiconductor substrate 200 in first area
First insulating layer described in upper exposed portion, the first insulating layer which exposes are etching 500 process of the second polysilicon layer
In be damaged, and then will affect the performance for the semiconductor devices being subsequently formed.
For this purpose, in the present embodiment, the first insulating layer exposed in the first area I semiconductor substrate 200 and right is removed
It is exhausted to form third after exposing the semiconductor substrate 200 in the semiconductor substrate 200 of exposing for the second insulating layer 212 answered
The performance for the semiconductor devices being subsequently formed can be improved in edge layer 230.
In addition, in the thermal oxidation technology for being used to form the third insulating layer 230, while to positioned at the third polycrystalline
The first of 511 lower section of side wall and control grid layer that the second insulating layer 212 of 510 lower section of silicon layer and the first insulating layer 400 expose
The side wall and the second area that insulating layer 400, the tunnel layer 211 of 310 lower section of floating gate layer and second insulating layer 212 are exposed
The 4th insulating layer 210 expose side wall repaired, to further increase the performance for the semiconductor devices being subsequently formed.
Then, in conjunction with reference Figure 18, the third polysilicon layer 510 is etched, forms selection on the first area I
Grid layer 512, the selection grid layer 512 are used to form the selection grid of gate-division type flash memory.
In the present embodiment, when etching the third polysilicon layer 510, while the institute on the third region III is etched
The 4th polysilicon layer 530 is stated, second grid layer 531 is formed.The logic that the second grid layer 531 is used to form logical device is brilliant
Body pipe.
It is worth noting that, can be formed on the third region III more after etching the 4th polysilicon layer 530
A second grid layer 531, to form transistor (including N-type logic transistor and the p-type logic crystal of multiple logical devices
Pipe), but the present embodiment illustrates only the second grid layer, the number of the second grid layer 531 for ease of description
And the scope of protection of the present invention is not limited.
After forming the selection grid layer 512, the doped p-type ion into the selection grid layer 512.Adulterate the choosing of P type ion
The floating gate layer 310 for selecting grid layer 512 and doped N-type ion is used to form the gate-division type flash memory of superficial face trench transistor structure.
With reference to Figure 19, in the present embodiment, before the doped p-type ion into the selection grid layer 512, first in the selection grid
The first side wall 610 is formed on 512 side wall, forms the second side wall on the side wall of the floating gate layer 310 and control grid layer 511
620, third side wall 630 is formed on the side wall of the first grid layer 320 and the second polycrystal layer 520, and in second grid layer
531 side wall forms the 4th side wall 640.
Later, while the doped p-type ion into the selection grid layer 512, to the semiconductor of the first area I
Injecting p-type ion is in substrate 200 to form source electrode and drain electrode (in figure not in the semiconductor substrate of 310 two sides of floating gate layer
Display)；
Or while the doped p-type ion into the selection grid layer 512, to described the half of the second area II
Doped p-type ion in conductor substrate 200, to form source electrode and the leakage of the first transistor in 320 two sides of first grid layer
Pole (not shown)；
Or it is, while the doped p-type ion into the selection grid layer 512, to the semiconductor of third region III
Doped p-type ion in substrate 200, to form the source electrode and drain electrode of logic transistor in 531 two sides of second grid layer.
It is above-mentioned into the selection grid layer 512 doped p-type ion simultaneously, formed gate-division type flash memory source electrode and drain electrode,
Or the source electrode and drain electrode of the first transistor, or it is the source electrode and drain electrode of logic transistor, to simplify semiconductor devices
Formation process reduces process costs.
In the present embodiment, doped with N-type ion in the floating gate layer 310, the selection grid layer 512 it is interior doped with p-type from
Son, the floating gate layer 310, control grid layer 511 and selection grid layer 512 are used to form the sub-gate of superficial face trench transistor structure
Flash memory；The first grid layer 320 is used to form the first device；The second grid layer 531 is used to form logical device.
In the present embodiment, after forming tunnel layer on a semiconductor substrate, formed on the tunnel layer doped with N-type ion
The first polysilicon layer；The first polysilicon layer on the first area is etched later, forms floating gate layer；Then, described floating
After forming the first insulating layer in grid layer, the second polysilicon layer formed on the semiconductor substrate, second polysilicon layer
Cover the floating gate layer；Second polysilicon layer is etched, forms control grid layer on the floating gate layer, in the first area
Semiconductor substrate on formed be located at the floating gate layer side selection grid layer, the floating gate layer and selection grid layer between be formed with
Gap, later the injecting p-type ion into the selection grid layer again.
Compared to the technique of the existing gate-division type flash memory for forming superficial face trench transistor structure, in conjunction with reference Fig. 5~figure
7, technical solution provided by the invention eliminates, in prior art, in order to formed doped N-type ion floating gate and doped p-type from
The selection grid of son, so that the different zones in intrinsically polysilicon layer inject different types of ion, and in intrinsically polysilicon layer
Different zones inject in the technique of different types of ion, the formation and removal of multiple masks of progress, including：
After forming intrinsically polysilicon layer 130 in the semiconductor substrate 100, the first is formed in the polysilicon layer 130
Three masks 122, and the injecting p-type ion into the intrinsically polysilicon layer 130 of 101 upper side of floating gate region, it is more to form selection grid
Polysilicon regions 131；
The third mask 122 is removed again later, in the 4th mask of formation on the selection grid polysilicon region 131
123, and be mask to except the outer intrinsically polysilicon layer 130 of the selection grid polysilicon region 131 is injected with the 4th mask 123
N-type ion；Etch the polysilicon layer 132 doped with ion again, formed doped with N-type ion floating gate 134 and doped with p-type from
The selection grid 133 of son.
What the forming method of semiconductor structure provided by the invention can effectively simplify superficial face trench transistor structure divides grid
The manufacturing process of formula flash memory reduces process costs.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (15)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate includes being used to form the first area of gate-division type flash memory；
Tunnel layer is formed on the semiconductor substrate；
The first polysilicon layer doped with N-type ion is formed on the tunnel layer；
The first polysilicon layer on the first area is etched, floating gate layer is formed；
The first insulating layer is formed on the floating gate layer；
The second polysilicon layer is covered on first insulating layer and semiconductor substrate；
Second polysilicon layer is etched, forms control grid layer on the floating gate layer, while on the first area, is formed
Third polysilicon layer positioned at the side of the floating gate layer；Gap is formed between the third polysilicon layer and the floating gate layer；
The third polysilicon layer is etched, selection grid layer is formed；
The doped p-type ion into the selection grid layer.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that
After etching first polysilicon layer and forming floating gate layer, formed before first insulating layer, the semiconductor junction
The forming method of structure further includes：The tunnel layer that removal is located at the floating gate layer periphery exposes the semiconductor substrate surface, later
In the first area, second insulating layer is formed on the semiconductor substrate surface of exposing；
Include in the step of forming the first insulating layer on the floating gate layer：First insulating layer is set also to be covered on described second absolutely
In edge layer.
3. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the second insulating layer is silica
Layer.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that form the work of the second insulating layer
Skill is thermal oxidation technology.
5. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the second insulating layer with a thickness of
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the step of forming the first insulating layer is wrapped
It includes：The first silicon oxide layer, silicon nitride layer and the second silicon oxide layer are sequentially formed on the floating gate layer.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that etching second polysilicon layer,
After forming the control grid layer and third polysilicon layer, the first insulating layer described in exposed portion on the first area；
Before etching the third polysilicon layer, the forming method further includes：
First insulating layer exposed on the first area and corresponding second insulating layer are removed, to expose the semiconductor
Substrate；
Third insulating layer is formed in the semiconductor substrate surface of exposing.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the material of the third insulating layer is
Silica.
9. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the third insulating layer with a thickness of
10. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that the formation of the third insulating layer
Method is thermal oxidation technology.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that the semiconductor substrate further includes
Second area is used to form the first device；
Before forming first polysilicon layer, the forming method further includes that the 4th insulation is formed on the second area
Layer；
The step of forming first polysilicon layer further include：First polysilicon layer is also covered on the second area；
Etching the step of first polysilicon layer is to form floating gate layer further includes：Etch the first polycrystalline on the second area
Silicon layer forms first grid layer；
Include in the step of forming the first insulating layer on the floating gate layer：First insulating layer is set also to be covered on the first grid
On the layer of pole；
The step of forming the second polysilicon layer on the semiconductor substrate include：Make second polysilicon layer covering described the
Two regions, and second polysilicon layer covers the first grid layer；
Etching the step of second polysilicon layer forms control grid layer further includes：Second on the second area is etched simultaneously
Polysilicon layer forms the second polycrystal layer on the first grid layer.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that the semiconductor substrate further includes
Third region, is used to form logical device；
After forming the floating gate layer, before forming the second polysilicon layer, the forming method of the semiconductor structure further includes：Institute
The semiconductor substrate surface for stating third region forms the 5th insulating layer；
The step of forming the second polysilicon layer on the semiconductor substrate include：Make second polysilicon layer covering described the
Three regions；
Etching the step of second polysilicon layer forms selection grid layer further includes：Second on the third region is etched simultaneously
Polysilicon layer forms second grid layer.
13. such as the forming method of the described in any item semiconductor structures of claim 1~12, which is characterized in that the selection
The step of doped p-type ion, includes in grid layer：
The injecting p-type ion into the selection grid layer, while injecting p-type ion in the semiconductor substrate into the first area
To form source electrode and drain electrode in the semiconductor substrate of the floating gate layer two sides.
14. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that first device includes first
Transistor, into the selection grid layer the step of doped p-type ion include：
It is brilliant to form first for the injecting p-type ion into the selection grid layer, while the doped p-type ion into the semiconductor substrate
The source electrode and drain electrode of body pipe.
15. the forming method of semiconductor structure as claimed in claim 12, which is characterized in that the logical device includes logic
Transistor, into the selection grid layer the step of doped p-type ion include：
It is brilliant to form logic for the injecting p-type ion into the selection grid layer, while the doped p-type ion into the semiconductor substrate
The source electrode and drain electrode of body pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510051526.7A CN105990092B (en) | 2015-01-30 | 2015-01-30 | The forming method of semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510051526.7A CN105990092B (en) | 2015-01-30 | 2015-01-30 | The forming method of semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105990092A CN105990092A (en) | 2016-10-05 |
| CN105990092B true CN105990092B (en) | 2018-11-16 |
Family
ID=57035673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510051526.7A Active CN105990092B (en) | 2015-01-30 | 2015-01-30 | The forming method of semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105990092B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113113415B (en) * | 2021-03-31 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Floating gate type split gate flash memory device structure and manufacturing process thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1670961A (en) * | 2004-03-17 | 2005-09-21 | 阿克特兰斯系统公司 | Self-aligned split-gate nand flash memory and fabrication process |
| CN101197263A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of high voltage transistor and memory device |
| CN102122662A (en) * | 2011-01-17 | 2011-07-13 | 上海宏力半导体制造有限公司 | P-type metal oxide semiconductor (MOS) memory unit |
-
2015
- 2015-01-30 CN CN201510051526.7A patent/CN105990092B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1670961A (en) * | 2004-03-17 | 2005-09-21 | 阿克特兰斯系统公司 | Self-aligned split-gate nand flash memory and fabrication process |
| CN101197263A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of high voltage transistor and memory device |
| CN102122662A (en) * | 2011-01-17 | 2011-07-13 | 上海宏力半导体制造有限公司 | P-type metal oxide semiconductor (MOS) memory unit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105990092A (en) | 2016-10-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106298793B (en) | Autoregistration grid flash memory device and its manufacturing method | |
| CN102315252B (en) | Flash cell of shared source line and forming method thereof | |
| TWI720350B (en) | Split-gate type non-volatile memory and manufacturing method thereof | |
| CN106158755B (en) | Semiconductor structure and forming method thereof | |
| CN104882447A (en) | Semi-floating gate transistor of drain region embedding inversion layer and manufacturing method thereof | |
| CN106328654A (en) | Semiconductor device and forming method thereof | |
| CN108447866B (en) | Floating-gate device and preparation method thereof | |
| KR100654559B1 (en) | Nor-type flash memory cell array and manufacturing method thereof | |
| CN102945832B (en) | The forming method of flush memory device | |
| CN103380489A (en) | Process margin engineering in charge trapping field effect transistors | |
| CN104617048B (en) | Flash memory and forming method thereof | |
| KR100806787B1 (en) | Method of Manufacturing Flash Semiconductor Device | |
| US9825185B1 (en) | Integrated circuits and methods for fabricating integrated circuits with non-volatile memory structures | |
| KR100752192B1 (en) | Single-poly structure of flash memory device and manufacturing method thereof | |
| CN105990092B (en) | The forming method of semiconductor structure | |
| CN104425500B (en) | SONOS non-volatility memorizers and its manufacturing method | |
| CN104638018B (en) | A kind of half floating-gate device and preparation method thereof | |
| CN110277399B (en) | SONOS memory and manufacturing method thereof | |
| CN107994025B (en) | Increase the method and floating gate type flash memory structure of floating gate type flash memory lateral wall width | |
| CN102693905B (en) | The formation method of flash cell and floating boom thereof | |
| CN106611796A (en) | A P-type MOS flash memory memory cell, a memory and a manufacturing method thereof | |
| CN105826272A (en) | Semiconductor device and forming method thereof | |
| CN105990244B (en) | The forming method of semiconductor structure | |
| CN103972179A (en) | Method for improving durability of B4-Flash device | |
| CN108766970A (en) | A kind of SONOS memories and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |