CN105990092A - Method of forming semiconductor structure - Google Patents
Method of forming semiconductor structure Download PDFInfo
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- CN105990092A CN105990092A CN201510051526.7A CN201510051526A CN105990092A CN 105990092 A CN105990092 A CN 105990092A CN 201510051526 A CN201510051526 A CN 201510051526A CN 105990092 A CN105990092 A CN 105990092A
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Abstract
The invention provides a method of forming a semiconductor structure, comprising the following steps: after a tunneling layer is formed on a semiconductor substrate, forming a first polycrystalline silicon layer doped with N-type ions on the tunneling layer; etching the first polycrystalline silicon layer on a memory area to form a floating gate layer; after a first insulating layer is formed on the floating gate layer, forming a second polycrystalline silicon layer on the semiconductor substrate, wherein the semiconductor second polycrystalline silicon layer covers the floating gate layer; and etching the second polycrystalline silicon layer, forming a control gate layer on the floating gate layer, and forming a selection gate layer at one side of the floating gate layer on the semiconductor substrate in the memory area, wherein there is a gap between the floating gate layer and the selection gate layer. Compared with the prior art, the manufacturing process of a split-gate flash memory of a shallow surface channel transistor structure is simplified effectively, and the manufacture difficulty and the process cost are reduced.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the forming method of a kind of semiconductor structure.
Background technology
Gate-division type flash memory is a kind of conventional nonvolatile semiconductor memory, its with without cross erasure effect,
Circuit design is relatively easy, and the operational characteristics of low pressure, high speed has become the mainstream technology of memory device,
It is widely used in the electronic products such as such as smart card, SIM, microcontroller, mobile phone.
With reference to shown in Fig. 1, gate-division type flash memory Semiconductor substrate 10；It is positioned at the tunnel layer in Semiconductor substrate 10
11, it is positioned at the floating boom 21 on described tunnel layer 11, insulating barrier 22 on floating boom 21, is positioned at described insulating barrier
Control gate 23 on 22, and be positioned on described tunnel layer 11, and it is positioned at described floating boom 21 and control gate 23
The selection grid 24 of side.
In previous processes, described gate-division type flash memory mostly is buried regions channel transistor (Burried channel MOS)
Structure, comprising: N hydrazine, N-type floating boom and N-type select grid structure；So along with for gate-division type flash memory number
The lifting that device read or write speed requires, develops a kind of shallow surface channel transistor (Surface channel now
MOS) gate-division type flash memory of structure, comprising: N hydrazine, N-type floating boom and p-type selection grid, thus effectively
Reduce the threshold voltage selecting grid 24, to improve the read or write speed of gate-division type flash memory.
Additionally, when gate-division type flash memory uses, it will usually peripheral circuit (Periphery can be set about
Circuit).Described peripheral circuit is mainly logic circuit, including: high voltage transistor and logic transistor,
The threshold voltage of wherein said high voltage transistor is more than the threshold voltage of described logic transistor.Described logic
Circuit, in order to introduce different voltage, controls described gate-division type flash memory and carries out data write, wipes and read
Deng operation.Thus, in existing gate-division type flash memory manufacturing process, the most often
Carry out gate-division type flash memory and high threshold voltage transistors and logic transistor manufacturing process simultaneously.It is progressive
One step adds the difficulty that the gate-division type flash memory of shallow surface channel transistor structure manufactures.
Fig. 2～7, for the manufacture structural representation of the gate-division type flash memory of existing shallow surface channel transistor structure,
The manufacture method of the gate-division type flash memory of existing shallow surface channel transistor structure includes:
Referring initially to Fig. 2, it is provided that Semiconductor substrate 100.
Described Semiconductor substrate 100 includes the first area I for manufacturing gate-division type flash memory, for manufacturing high pressure
The second area II of transistor, and for manufacturing the 3rd region III of logic transistor；
In the Semiconductor substrate of described first area I, it is injected with N-type ion, is formed with N trap and (figure does not shows
Show)；The P for forming p-type high voltage transistor it is formed with in the Semiconductor substrate of described second area II
Trap, and for forming the N trap (not shown) of N-type high voltage transistor；
With continued reference to Fig. 2, after described Semiconductor substrate 100 forms insulating barrier 110, in described secondth district
The first mask 120 is formed on territory II and the 3rd region III, and part first area I, and described to not covering
Implanting p-type ion in the memory area I of the first mask 120, forms floating gate region 101, is used for adjusting follow-up
It is formed at the threshold voltage of control gate above described floating gate region；
Referring next to Fig. 3, after described second area II and the 3rd region III forms the second mask 121, with
Second mask 121 is that mask re-injects p-type ion in the Semiconductor substrate 100 of first area I, and formation is deposited
Reservoir region 102, for adjusting the floating boom being subsequently formed further and selecting the threshold voltage of grid；
With reference to Fig. 4, after removing the insulating barrier on described memory area 102, at described memory area 102
Semiconductor substrate 100 on form tunnel layer 112, retain on described second area II and the 3rd region III is exhausted
Edge layer 111.
In conjunction with reference to Fig. 5, after described Semiconductor substrate 100 forms intrinsically polysilicon layer 130, described
Form the 3rd mask 122 in intrinsically polysilicon layer 130, expose the intrinsic polycrystalline at the upper side of floating gate region 101
Silicon layer, and implanting p-type ion in the intrinsically polysilicon layer 130 exposed, formed and select gate polysilicon region
131。
In conjunction with reference to Fig. 6, after removing described 3rd mask 122, in described selection gate polysilicon region 131
Upper formation the 4th mask 123, and in remaining polysilicon layer, inject N with described 4th mask 123 for mask
Type ion, is formed at the zones of different polysilicon layer 132 doped with dissimilar ion；
In conjunction with reference to Fig. 6 and Fig. 7, after etching is doped with the polysilicon layer 132 of ion, formed doped with N
The floating boom 134 of type ion and the selection grid 133 doped with p-type ion, simultaneously shape on described second area II
Becoming the grid structure 135 doped with N-type ion, described grid structure 135 is used for forming high voltage transistor；
Formed after selecting grid 133, on described floating boom 134 and selection grid 133, form insulating barrier, and in floating
The structures such as control gate are formed on insulating barrier on grid 134；
Afterwards, in described Semiconductor substrate 100, form another layer of polysilicon layer (not shown),
Etch described polysilicon layer again, the 3rd region III is formed logical device.
As it has been described above, formed shallow surface channel transistor structure gate-division type flash memory floating boom and select grid
Existing technique in, with reference to Fig. 5 and Fig. 6, because after forming intrinsically polysilicon layer 130 on a semiconductor substrate,
Need in intrinsically polysilicon layer zones of different, carry out the most different types of ion implanting step, follow-up use
In forming the N-type floating boom doped with dissimilar ion and p-type selection grid, and in repeatedly ion implanting step
In, in addition it is also necessary in intrinsically polysilicon layer, carry out formation and the removal step of multiple mask, existing shallow table
The manufacturing process of the gate-division type flash memory of face trench transistor structure is complicated, and process costs is big.
To this end, the manufacturing process how simplifying the gate-division type flash memory of shallow surface channel transistor structure is ability
The problem that field technique personnel need solution badly.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor structure, thus simplifies shallow surface
The gate-division type flash memory manufacturing process of trench transistor structure.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor structure,
Thering is provided Semiconductor substrate, described Semiconductor substrate includes the first area for forming gate-division type flash memory；
Form tunnel layer on the semiconductor substrate；
Described tunnel layer is formed the first polysilicon layer doped with N-type ion；
Etch the first polysilicon layer on described first area, form floating gate layer；
Described floating gate layer is formed the first insulating barrier；
Described first insulating barrier and Semiconductor substrate cover the second polysilicon layer；
Etch described second polysilicon layer, described floating gate layer is formed control grid layer, and at described floating boom
Formed in the first area Semiconductor substrate of layer side and select gate layer；
Doped p-type ion in described selection gate layer.
Alternatively, after described first polysilicon layer of etching forms floating gate layer, form described first insulation
Before Ceng, the forming method of described semiconductor structure also includes: remove the tunnel being positioned at described floating gate layer periphery
Wear layer and expose described semiconductor substrate surface, afterwards in described first area, the Semiconductor substrate exposed
The second insulating barrier is formed on surface；
The step forming the first insulating barrier on described floating gate layer includes: make described first insulating barrier also cover
On described second insulating barrier.
Alternatively, described second insulating barrier is silicon oxide layer.
Alternatively, the technique forming described second insulating barrier is thermal oxidation technology.
Alternatively, the thickness of described second insulating barrier is
Alternatively, the step forming the first insulating barrier includes: sequentially form the first oxygen on described floating gate layer
SiClx layer, silicon nitride layer and the second silicon oxide layer.
Alternatively, etch described second polysilicon layer, formed and select the step of gate layer to include:
Etch described second polysilicon layer, described floating gate layer forms control grid layer, simultaneously described the
On one region, form the 3rd polysilicon layer of the side being positioned at described floating gate layer；Described 3rd polysilicon layer
And between described floating gate layer, form gap；
Etch described 3rd polysilicon layer, form described selection gate layer.
Alternatively, etch described second polysilicon layer, after forming described control grid layer and the 3rd polysilicon layer,
The first insulating barrier described in exposed portion on described first area；
Before etching described 3rd polysilicon layer, described forming method also includes:
Remove described first insulating barrier exposed on described first area and the second corresponding insulating barrier, with dew
Go out described Semiconductor substrate；
The 3rd insulating barrier is formed at the described semiconductor substrate surface exposed.
Alternatively, the material of described 3rd insulating barrier is silicon oxide.
Alternatively, the thickness of described 3rd insulating barrier is
Alternatively, the forming method of described 3rd insulating barrier is thermal oxidation technology.
Alternatively, described Semiconductor substrate also includes second area, for forming the first device；
Before forming described first polysilicon layer, described forming method also includes, on described second area
Form the 4th insulating barrier；
The step forming described first polysilicon layer also includes: described first polysilicon layer also covers described
On second area；
Etch described first polysilicon layer also to include with the step forming floating gate layer: etch described second area
On first polysilicon layer formed first grid layer；
The step forming the first insulating barrier on described floating gate layer includes: make described first insulating barrier also cover
On described first grid layer；
The step forming the second polysilicon layer on the semiconductor substrate includes: make described second polysilicon
Layer covers described second area, and described second polysilicon layer covers described first grid layer；
The step etching described second polysilicon layer formation control grid layer also includes: etch described second simultaneously
The second polysilicon layer on region, forms the second polycrystal layer on described first grid layer.
Alternatively, described Semiconductor substrate also includes the 3rd region, is used for forming logical device；
After forming described floating gate layer, before forming the second polysilicon layer, the formation side of described semiconductor structure
Method also includes: the semiconductor substrate surface in described 3rd region forms the 5th insulating barrier；
The step forming the second polysilicon layer on the semiconductor substrate includes: make described second polysilicon
Layer covers described 3rd region；
Etching described second polysilicon layer formation selects the step of gate layer also to include: etch the described 3rd simultaneously
The second polysilicon layer on region, forms second grid layer.
Alternatively, in described selection gate layer, the step of doped p-type ion includes:
Implanting p-type ion in described selection gate layer, the simultaneously Semiconductor substrate in described first area
Interior implanting p-type ion is to form source electrode and drain electrode in the Semiconductor substrate of described floating gate layer both sides.
Alternatively, described first device includes the first transistor, in described selection gate layer doped p-type from
The step of son includes:
Implanting p-type ion in described selection gate layer, simultaneously in described Semiconductor substrate doped p-type from
Son, the source electrode of the first transistor and drain electrode.
Alternatively, described logical device includes logic transistor, in described selection gate layer doped p-type from
The step of son includes:
Implanting p-type ion in described selection gate layer, simultaneously in described Semiconductor substrate doped p-type from
Son, forms source electrode and the drain electrode of logic transistor.
Compared with prior art, technical scheme has the advantage that
After the first area of Semiconductor substrate forms tunnel layer, formed on the tunneling layer doped with N-type
First polysilicon layer of ion, forms doping N after the first polysilicon layer etched on described first area
The floating gate layer of type ion, and after forming the first insulating barrier on described floating gate layer, then at described memory areas
Forming the second polysilicon layer on territory, the second polysilicon layer covers described floating gate layer；In etching described more than second
After crystal silicon layer, described floating gate layer forms control grid layer, formed in described floating gate layer side and select gate layer；
Implanting p-type ion in described selection gate layer the most again, for forming the selection grid doped with p-type ion
Layer, and then for forming the gate-division type flash memory of shallow surface channel transistor structure.
Compared to the manufacturing process of the gate-division type flash memory of existing shallow surface channel transistor structure, the present invention carries
For in the forming method of semiconductor structure, forming the floating boom doped with N-type ion and the selection of p-type ion
During grid, eliminate in intrinsically polysilicon layer zones of different, carry out the most different types of ion note
Enter step, and in repeatedly ion implantation process, intrinsically polysilicon layer carries out the shape of multiple mask
Become and removal step, thus effectively simplify the manufacture work of the gate-division type flash memory of shallow surface channel transistor structure
Skill, reduces process costs.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of gate-division type flash memory；
Fig. 2 to Fig. 7 is in the gate-division type flash memory technique of existing formation surface gate structure, in each step
The cross-sectional view of semiconductor structure；
Fig. 8 to Figure 19 is the quasiconductor in the forming method one each step of embodiment of semiconductor structure of the present invention
The cross-sectional view of structure.
Detailed description of the invention
As stated in the Background Art, compared to the gate-division type flash memory of buried regions trench transistor structure, shallow surface ditch
The gate-division type flash memory of road transistor arrangement can effectively reduce the threshold voltage of the control gate of gate-division type flash memory, from
And improve the read or write speed of gate-division type flash memory.
But in the manufacturing process of the gate-division type flash memory of existing shallow surface channel transistor structure, Semiconductor substrate
After upper formation intrinsically polysilicon layer, needs carry out the most dissimilar in intrinsically polysilicon layer zones of different
Ion implanting step, be subsequently used for being formed and select doped with the N-type floating boom of dissimilar ion and p-type
Grid；And in repeatedly ion implanting step, in addition it is also necessary in intrinsically polysilicon layer, carry out the shape of multiple mask
Become and removal step, above steps very complicated, add point grid of shallow surface channel transistor structure
The manufacture difficulty of formula flash memory and cost.
To this end, the invention provides the forming method of a kind of semiconductor structure, shallow surface channel can be simplified brilliant
The manufacturing process of the gate-division type flash memory of body tubular construction, reduces process costs.
The forming method of the semiconductor structure that the present invention provides, including:
Thering is provided Semiconductor substrate, described Semiconductor substrate includes the first area for forming gate-division type flash memory；
Form tunnel layer on the semiconductor substrate, and formed doped with N-type ion on described tunnel layer
First polysilicon；Etch the first polysilicon layer on described first area afterwards, form floating gate layer；
Then, described floating gate layer forms the first insulating barrier, and at described first insulating barrier and quasiconductor
The second polysilicon layer formed on substrate；Etch described second polysilicon layer, described floating gate layer is formed
Control grid layer, and in the first area Semiconductor substrate of described floating gate layer side, form selection gate layer；It
After doped p-type ion in described selection gate layer again.
In the present invention, after the first polysilicon layer of etching doped N-type ion forms floating gate layer, in quasiconductor
Form the second polysilicon layer on substrate, and etch described second polysilicon layer and formed and select gate layer, backward
Doped p-type ion in described selection gate layer.
Compared to existing technique, in the forming method of the semiconductor structure that the present invention provides, forming doping
During having floating boom and the p-type Ion selecting grid of N-type ion, eliminate to intrinsically polysilicon layer different
The most different types of ion implanting step is carried out in region, and in repeatedly ion implantation process,
Carry out formation and the removal step of multiple mask in intrinsically polysilicon layer, thus effectively simplify shallow surface channel
The manufacturing process of the gate-division type flash memory of transistor arrangement, reduces process costs.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
There is the gate-division type flash memory of shallow surface channel transistor structure, high voltage transistor (HV Device) and patrol
The manufacture method collecting device (Logic Device) is that the detailed process of the present invention is done specifically by embodiment
Bright.
Fig. 8 to Figure 19 is the section knot schematic diagram of the forming process of the semiconductor structure of the embodiment of the present invention.
Referring initially to Fig. 8, it is provided that Semiconductor substrate 200.
In the present embodiment, described Semiconductor substrate 200 is silicon substrate.But other in addition to the present embodiment are real
Executing in example, described Semiconductor substrate 200 can be also germanium substrate, silicon-Germanium substrate or insulator substrates.This
Semiconductor substrate 200 in field is all applicable to the present invention, and the present invention is to described Semiconductor substrate 200
Type does not limits.
In the present embodiment, described Semiconductor substrate 200 includes first area I, the second area being set up in parallel
II and the 3rd region III.Described first area I is point grid for forming shallow surface channel transistor structure
Formula flash memory, second area II is for forming the first device, and described 3rd region III is for being used for forming logic device
The logical device region of part.
In the present embodiment, described first device includes the first transistor, and described logical device includes logic
Transistor.Described the first transistor can be as high voltage transistor, and the threshold voltage of the first transistor is more than institute
State the threshold voltage of logic transistor.
In the present embodiment, it is formed with the first well region in the Semiconductor substrate 200 of first area I and (figure is not marked
Show), described first well region is the N-type well region being injected with the N-type ions such as phosphorus (P)；Described second area
Multiple N-type well region and P type trap zone it is formed with, respectively in order to form N-type in the Semiconductor substrate 200 of II
High voltage transistor and p-type high voltage transistor；Well region has now been had not yet been formed in described 3rd region II.
In the present embodiment, in described Semiconductor substrate 200, it is formed with fleet plough groove isolation structure (Shallow
Trench Isolation, STI) (non-label in figure), for isolating each different region, and each
Adjacent well region in region, to realize being subsequently formed each semiconductor device in described Semiconductor substrate 200
Electric isolution between part.The packing material of fleet plough groove isolation structure can be silicon oxide, silicon nitride, nitrogen oxidation
One or more in silicon.
In other embodiments in addition to the present embodiment, also can be provided with except STI in described Semiconductor substrate 200
Other isolation structures outside structure, to realize being subsequently formed the electric isolution between each semiconductor device.The present invention
The type of described isolation structure is not limited.
Additionally, be additionally provided with transistor and metal interconnection structure etc. all kinds of half in described Semiconductor substrate 200
Conductor components and parts, said structure does not the most affect protection scope of the present invention, and described quasiconductor is served as a contrast by the present invention
The structure at the end 200 does not limit.
With continued reference to Fig. 8, in described Semiconductor substrate 200 formed cover described first area I, second
Region II and the 4th insulating barrier 210 of the 3rd region III, described 4th insulating barrier 210 is for formation first
Gate dielectric layer between grid and Semiconductor substrate 200 in transistor.
Afterwards, in first well region of described first area I, form the first ion range 201, and be positioned at institute
State the second ion range 202 in the first ion range 201；
In the present embodiment, the forming step of described first ion range 201 and the second ion range 202 includes:
Implanting p-type ion in described first well region, to form described second ion range 202, described
Two ion range 202 are for adjusting the threshold voltage of control gate；Afterwards, again note in described first well region
Entering p-type ion, form the first ion range 201, described first ion range 201 divides for adjusting further
The control gate of gate flash memory and the threshold voltage of selection grid.
In the present embodiment, described 4th insulating barrier 210 is silicon oxide layer, and forming method is chosen as thermal oxide work
The methods such as skill, chemical gaseous phase deposition or ald.The present invention shape to described 4th insulating barrier 210
One-tenth method does not limits.
Alternatively, the thickness of described 4th insulating barrier 210 is
Referring next to Fig. 9, afterwards, remove the 4th insulating barrier 210 on described first area I, expose institute
State the surface of first area I Semiconductor substrate 200；And in described first area I Semiconductor substrate 200
Surface forms tunnel layer 211.
In the present embodiment, described tunnel layer 211 is silicon oxide layer, and forming method is thermal oxidation technology
Alternatively, the thickness of described tunnel layer 211 is
With reference to Figure 10, after forming described tunnel layer 211, formed on the surface of described Semiconductor substrate 200
First polysilicon layer 300, described first polysilicon layer 300 is doped with N-type ion.
In the present embodiment, described N-type ion includes phosphorus (P) ion.But other in addition to the present embodiment are real
Executing in example, described N-type ion can be also other ions such as arsenic (As), and the present invention is to described N-type ion
Specifically chosen do not limit.
In the present embodiment, described first polysilicon layer 300 covers described first area I, second area II
With the 3rd region III.
In the present embodiment, the method for described first polysilicon layer 300 is that chemical gaseous phase deposits (Chemical
Vapor Deposition, is called for short CVD).
The forming process of described first polysilicon layer 300 can include, is passed through silicon source gas and phosphorus source gas simultaneously
Body, thus form the first polysilicon layer doped with phosphorus.
But in addition to the present embodiment, also by being initially formed intrinsically polysilicon layer, afterwards by ion implanting etc.
Method injects phosphonium ion in described intrinsically polysilicon layer, to form the first polysilicon layer doped with phosphorus.
Above-mentioned simple change is the most within the scope of the present invention.
With reference to Figure 11, etch described first polysilicon layer 300, described first area I is formed floating gate layer
310。
In the present embodiment, floating gate layer 310 is positioned at above described second ion range 202.
In the present embodiment, etching described first polysilicon layer 300 to form the same of described floating gate layer 310
Time, etch the first polysilicon layer 300 on described second area II, described second area II is formed
First grid layer 320.
Described first grid layer 320 is for forming the grid of the first transistor.
In the present embodiment, all doped with N-type ion in described floating gate layer 310 and first grid layer 320.
With continued reference to Figure 11, etch described first polysilicon layer 300 to be formed after described floating gate layer 310,
Tunnel layer described in exposed portion, this part tunnel layer is damaged when etching described first polysilicon layer 300
Wound, and then affect the performance of the gate-division type flash memory being subsequently formed.
To this end, in the present embodiment, after forming described floating gate layer 310, etching removes described first area
The tunnel layer 211 exposed on II, to expose described Semiconductor substrate 200 surface.
Referring again to Figure 12, the surface of the Semiconductor substrate 200 exposed on described first area I forms the
Two insulating barriers 212.
In the present embodiment, described second insulating barrier 212 is silicon oxide layer.
Alternatively, the forming method of described second insulating barrier 212 is thermal oxidation technology.
Still optionally further, the thickness of described second insulating barrier 212 is
After it should be noted that described first polysilicon layer 300 of etching, can shape on described first area I
Become multiple floating gate layer 310, follow-up in order to form multiple gate-division type flash memory；Shape on described second area II
Become to have multiple described first grid layer, (include that N-type is high in order to form each transistor of multiple first device
Piezoelectric crystal and p-type high voltage transistor), but the present embodiment illustrate only one described for the ease of describing
One grid layer and floating gate layer, but the quantity of described floating gate layer and first grid layer does not limit the present invention's
Protection domain.
With reference to Figure 13, after forming described floating gate layer 310, described floating gate layer 310 forms the first insulation
Layer 400.Described first insulating barrier 400 as in the gate-division type flash memory being subsequently formed, floating boom and control gate it
Between insulating barrier.
In the present embodiment, described first insulating barrier 400 covers in described second insulating barrier the 212, the 4th insulation
On layer 210 and described first grid layer 320.
In the present embodiment, the forming step of described first insulating barrier 400 includes:
Described Semiconductor substrate 200 sequentially forms the first silicon oxide layer (oxide), silicon nitride layer
And the second silicon oxide layer (oxide) (nitride).Described first silicon oxide layer, silicon nitride layer and
Silicon dioxide layer forms the first insulating barrier 400, and making described first insulating barrier 400 is ONO (oxide-
Nitride-oxide) Rotating fields.
Alternatively, the thickness of described first oxide skin(coating) isLeft and right, the thickness of nitride layer is
Left and right, the thickness of the second oxide skin(coating) isLeft and right；Described first oxide skin(coating), nitride layer and
The forming method of the second oxide skin(coating) is chemical gaseous phase deposition.The structure of described ONO layer and forming method
For the mature technology of this area, do not repeat them here.
Alternatively, after forming described first insulating barrier 400, can be to the Semiconductor substrate 200 of the 3rd region III
Zones of different in be injected separately into N-type ion and p-type ion, thus be formed with multiple N-type well region and P
Type well region, respectively in order to form N-type logic transistor and p-type logic transistor.Said structure is ability
Territory mature technology does not repeats them here.
Then, with reference to Figure 14, the first insulating barrier 400 and the 4th being positioned on described 3rd region III is removed
Insulating barrier, exposes the Semiconductor substrate 200 of described 3rd region III；And expose in described 3rd region III
Semiconductor substrate 200 surface formed the 5th insulating barrier 220.Described 5th insulating barrier 220 can be as follow-up
Gate dielectric layer in the logic transistor formed.
In the present embodiment, described 5th insulating barrier 220 is silicon oxide layer.
Still optionally further, the forming method of described 5th insulating barrier 220 is thermal oxidation technology.
With reference to Figure 15, afterwards, described Semiconductor substrate 200 forms the second polysilicon layer 500.
In the present embodiment, described second polysilicon layer 500 is intrinsically polysilicon layer, and forming method is chemistry
Vapour deposition.
In the present embodiment, described second polysilicon layer 500 covers described floating gate layer 310, described first grid
Layer 320, and described first area I, second area II and the Semiconductor substrate 200 of the 3rd region III
Surface.
Afterwards, in conjunction with reference to Figure 16～Figure 18, described second polysilicon layer is etched, at described floating gate layer 310
Upper formation control grid layer 511, is formed in the Semiconductor substrate 200 of described first area I and is positioned at described floating
The selection gate layer 512 of gate layer 310 side, between being formed between described floating gate layer 310 and selection gate layer 512
Gap 601.
In the present embodiment, form described control grid layer 511 and select the step of gate layer 512 to include:
Referring initially to Figure 16, etch described second polysilicon layer 500, described floating gate layer 310 is formed control
Gate layer 511 processed, simultaneously on described first area I, forms the of the side being positioned at described floating gate layer 310
Three polysilicon layers 510, form gap between described 3rd polysilicon layer 510 and described floating gate layer 310
601。
In the present embodiment, form the same of described control grid layer 511 etching described second polysilicon layer 500
Time, described first grid layer 320 is formed the second polycrystal layer 520, described second polycrystal layer 520 is follow-up
Can be used for forming the interconnecting construction electrically connecting described first grid layer 320；And, also the described 3rd
The 4th polysilicon layer 530 is formed on the III of region.
With continued reference to Figure 16, after forming described control grid layer 511, etch in described first area I,
The second insulating barrier 212 below the first insulating barrier 400 exposed, and the first insulating barrier 400 exposed, with
Expose described Semiconductor substrate 200.
In conjunction with reference to Figure 17, form the 3rd insulating barrier on described Semiconductor substrate 200 surface exposed
230。
In the present embodiment, described 3rd insulating barrier 230 is silicon oxide layer.
Alternatively, the thickness of described 3rd insulating barrier 230 is
Still optionally further, the forming method of described 3rd insulating barrier 230 is thermal oxidation technology.
Etching after described second polysilicon layer 500 forms described control grid layer 511, in first area, I partly leads
First insulating barrier described in exposed portion on body substrate 200, the first insulating barrier that this part is exposed is in etching institute
Sustain damage during stating the second polysilicon layer 500, and then the semiconductor device that is subsequently formed can be affected
Performance.
To this end, in the present embodiment, remove first exposed in described first area I Semiconductor substrate 200 exhausted
Edge layer and the second corresponding insulating barrier 212, after exposing described Semiconductor substrate 200, partly lead expose
Form the 3rd insulating barrier 230 on body substrate 200 and can improve the performance of the semiconductor device being subsequently formed.
Additionally, in the thermal oxidation technology for forming described 3rd insulating barrier 230, be pointed to institute simultaneously
State the second insulating barrier 212 below the 3rd polysilicon layer 510 and sidewall that the first insulating barrier 400 exposes,
And the first insulating barrier 400 below control grid layer 511, the tunnel layer 211 below floating gate layer 310 and
The sidewall that two insulating barriers 212 expose, and the sidewall that the 4th insulating barrier 210 of described second area exposes
Repaired, with the performance of the semiconductor device that further raising is subsequently formed.
Then, in conjunction with reference to Figure 18, described 3rd polysilicon layer 510 is etched, at described first area I
Upper formation selects gate layer 512, and described selection gate layer 512 is for forming the selection grid of gate-division type flash memory.
In the present embodiment, when etching described three polysilicon layer 510, etch described 3rd region simultaneously
Described 4th polysilicon layer 530 on III, forms second grid layer 531.Described second grid layer 531 is used
In the logic transistor forming logical device.
After it should be noted that described 4th polysilicon layer 530 of etching, can be on described 3rd region III
It is formed with multiple second grid layer 531, (includes that N-type is patrolled in order to form the transistor of multiple logical device
Volume transistor and p-type logic transistor), but the present embodiment illustrate only one described for the ease of describing
Two grid layers, the number of described second grid layer 531 does not limit protection scope of the present invention.
After forming described selection gate layer 512, doped p-type ion in described selection gate layer 512.Doping P
It is brilliant that the selection gate layer 512 of type ion and the floating gate layer 310 of doped N-type ion are used for forming shallow surface channel
The gate-division type flash memory of body tubular construction.
With reference to Figure 19, in the present embodiment, before doped p-type ion in described selection gate layer 512, first
The sidewall of described selection grid 512 forms the first side wall 610, at described floating gate layer 310 and control grid layer
The second side wall 620 is formed, at described first grid layer 320 and the second polycrystal layer 520 on the sidewall of 511
The 3rd side wall 630 is formed on sidewall, and at sidewall formation the 4th side wall 640 of second grid layer 531.
Afterwards, while doped p-type ion in described selection gate layer 512, to described first area I
Semiconductor substrate 200 in implanting p-type ion with in the Semiconductor substrate of described floating gate layer 310 both sides
Form source electrode and drain electrode (not shown)；
Or, while doped p-type ion in described selection gate layer 512, to described second area
Doped p-type ion in the described Semiconductor substrate 200 of II, thus in described first grid layer 320 both sides,
Form source electrode and the drain electrode (not shown) of the first transistor；
Or it is, while doped p-type ion in described selection gate layer 512, to the 3rd region III
Semiconductor substrate 200 in doped p-type ion, thus in described second grid layer 531 both sides, formed
The source electrode of logic transistor and drain electrode.
Above-mentioned doped p-type ion in described selection gate layer 512 while, form the source of gate-division type flash memory
Pole and drain electrode or the source electrode of the first transistor and drain electrode, or it is source electrode and the drain electrode of logic transistor,
Thus simplify the formation process of semiconductor device, reduce process costs.
In the present embodiment, doped with N-type ion in described floating gate layer 310, in described selection gate layer 512
Doped with p-type ion, described floating gate layer 310, control grid layer 511 and select gate layer 512 to be used for being formed shallow
The gate-division type flash memory of surface channel transistor structure；Described first grid layer 320 is for forming the first device；
Described second grid layer 531 is used for forming logical device.
In the present embodiment, after forming tunnel layer on a semiconductor substrate, described tunnel layer forms doping
There is the first polysilicon layer of N-type ion；Etch the first polysilicon layer on described first area, shape afterwards
Become floating gate layer；Then, after described floating gate layer is formed the first insulating barrier, on the semiconductor substrate
The second polysilicon layer formed, described second polysilicon layer covers described floating gate layer；Etch described more than second
Crystal silicon layer, forms control grid layer, shape in the Semiconductor substrate of described first area on described floating gate layer
Become to be positioned at the selection gate layer of described floating gate layer side, between described floating gate layer and selection gate layer, be formed with gap,
Implanting p-type ion in described selection gate layer the most again.
Compared to the technique of the gate-division type flash memory of existing formation shallow surface channel transistor structure, in conjunction with reference
Fig. 5～Fig. 7, the technical scheme that the present invention provides eliminates, in existing technique, in order to form doped N-type
The floating boom of ion and the selection grid of doped p-type ion, thus in the zones of different injection of intrinsically polysilicon layer
Different types of ion, and the work of the zones of different different types of ion of injection in intrinsically polysilicon layer
In skill, the step such as the formation of the multiple masks carried out and removal, including:
After described Semiconductor substrate 100 forms intrinsically polysilicon layer 130, first at described polysilicon layer
130 form note in the 3rd mask 122, and the intrinsically polysilicon layer 130 at the upper side of floating gate region 101
Enter p-type ion, formed and select gate polysilicon region 131；
Remove described 3rd mask 122 the most again, in forming the on described selection gate polysilicon region 131
Four masks 123, and with described 4th mask 123 for mask in addition to described selection gate polysilicon region 131
Intrinsically polysilicon layer 130 injects N-type ion；Etch the polysilicon layer 132 doped with ion again, formed
Floating boom 134 doped with N-type ion and the selection grid 133 doped with p-type ion.
The forming method of the semiconductor structure that the present invention provides can effectively simplify shallow surface channel transistor structure
The manufacturing process of gate-division type flash memory, reduce process costs.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (16)
1. the forming method of a semiconductor structure, it is characterised in that including:
Thering is provided Semiconductor substrate, described Semiconductor substrate includes the first area for forming gate-division type flash memory；
Form tunnel layer on the semiconductor substrate；
Described tunnel layer is formed the first polysilicon layer doped with N-type ion；
Etch the first polysilicon layer on described first area, form floating gate layer；
Described floating gate layer is formed the first insulating barrier；
Described first insulating barrier and Semiconductor substrate cover the second polysilicon layer；
Etch described second polysilicon layer, described floating gate layer is formed control grid layer, and at described floating gate layer
Formed in the first area Semiconductor substrate of side and select gate layer；
Doped p-type ion in described selection gate layer.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that
After described first polysilicon layer of etching forms floating gate layer, before forming described first insulating barrier, institute
The forming method stating semiconductor structure also includes: removal is positioned at the tunnel layer of described floating gate layer periphery and exposes
Described semiconductor substrate surface, afterwards in described first area, on the semiconductor substrate surface exposed
Form the second insulating barrier；
The step forming the first insulating barrier on described floating gate layer includes: make described first insulating barrier also cover
On described second insulating barrier.
3. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that described second insulation
Layer is silicon oxide layer.
4. the forming method of semiconductor structure as claimed in claim 3, it is characterised in that form described second
The technique of insulating barrier is thermal oxidation technology.
5. the forming method of semiconductor structure as claimed in claim 2, it is characterised in that described second insulation
The thickness of layer is
6. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that form the first insulation
The step of layer includes: sequentially form the first silicon oxide layer, silicon nitride layer and the on described floating gate layer
Silicon dioxide layer.
7. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that etch described second
Polysilicon layer, is formed and selects the step of gate layer to include:
Etch described second polysilicon layer, described floating gate layer forms control grid layer, simultaneously described first
On region, form the 3rd polysilicon layer of the side being positioned at described floating gate layer；Described 3rd polysilicon layer
And between described floating gate layer, form gap；
Etch described 3rd polysilicon layer, form described selection gate layer.
8. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that etch described second
Polysilicon layer, after forming described control grid layer and the 3rd polysilicon layer, exposes on described first area
Described first insulating barrier of part；
Before etching described 3rd polysilicon layer, described forming method also includes:
Remove described first insulating barrier exposed on described first area and the second corresponding insulating barrier, to expose
Described Semiconductor substrate；
The 3rd insulating barrier is formed at the described semiconductor substrate surface exposed.
9. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that described 3rd insulation
The material of layer is silicon oxide.
10. the forming method of semiconductor structure as claimed in claim 8, it is characterised in that described 3rd insulation
The thickness of layer is
The forming method of 11. semiconductor structures as claimed in claim 8, it is characterised in that described 3rd insulation
The forming method of layer is thermal oxidation technology.
The forming method of 12. semiconductor structures as claimed in claim 1, it is characterised in that described quasiconductor serves as a contrast
The end, also includes second area, for forming the first device；
Before forming described first polysilicon layer, described forming method also includes, shape on described second area
Become the 4th insulating barrier；
The step forming described first polysilicon layer also includes: described first polysilicon layer also covers described
On two regions；
Etch described first polysilicon layer also to include with the step forming floating gate layer: etch on described second area
First polysilicon layer formed first grid layer；
The step forming the first insulating barrier on described floating gate layer includes: make described first insulating barrier also cover
On described first grid layer；
The step forming the second polysilicon layer on the semiconductor substrate includes: make described second polysilicon layer
Cover described second area, and described second polysilicon layer covers described first grid layer；
The step etching described second polysilicon layer formation control grid layer also includes: etch described secondth district simultaneously
The second polysilicon layer on territory, forms the second polycrystal layer on described first grid layer.
The forming method of 13. semiconductor structures as claimed in claim 1, it is characterised in that described quasiconductor serves as a contrast
The end, also includes the 3rd region, is used for forming logical device；
After forming described floating gate layer, before forming the second polysilicon layer, the forming method of described semiconductor structure
Also include: the semiconductor substrate surface in described 3rd region forms the 5th insulating barrier；
The step forming the second polysilicon layer on the semiconductor substrate includes: make described second polysilicon layer
Cover described 3rd region；
Etching described second polysilicon layer formation selects the step of gate layer also to include: etch described 3rd district simultaneously
The second polysilicon layer on territory, forms second grid layer.
The forming method of 14. semiconductor structures as described in any one of claim 1～13, it is characterised in that to institute
State and select the step of doped p-type ion in gate layer to include:
Implanting p-type ion in described selection gate layer, simultaneously in the Semiconductor substrate in described first area
Implanting p-type ion is to form source electrode and drain electrode in the Semiconductor substrate of described floating gate layer both sides.
The forming method of 15. semiconductor structures as claimed in claim 12, it is characterised in that described first device
Including the first transistor, in described selection gate layer, the step of doped p-type ion includes:
Implanting p-type ion in described selection gate layer, simultaneously doped p-type ion in described Semiconductor substrate,
The source electrode of the first transistor and drain electrode.
16. the forming method of semiconductor structure as claimed in claim 13, it is characterised in that described logical device
Including logic transistor, in described selection gate layer, the step of doped p-type ion includes:
Implanting p-type ion in described selection gate layer, simultaneously doped p-type ion in described Semiconductor substrate,
Form source electrode and the drain electrode of logic transistor.
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| CN113113415A (en) * | 2021-03-31 | 2021-07-13 | 华虹半导体(无锡)有限公司 | Floating gate type split gate flash memory device structure and manufacturing process thereof |
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| CN1670961A (en) * | 2004-03-17 | 2005-09-21 | 阿克特兰斯系统公司 | Self-aligned split-gate nand flash memory and fabrication process |
| CN101197263A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of high voltage transistor and memory device |
| CN102122662A (en) * | 2011-01-17 | 2011-07-13 | 上海宏力半导体制造有限公司 | P-type metal oxide semiconductor (MOS) memory unit |
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| CN1670961A (en) * | 2004-03-17 | 2005-09-21 | 阿克特兰斯系统公司 | Self-aligned split-gate nand flash memory and fabrication process |
| CN101197263A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method of high voltage transistor and memory device |
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| CN113113415B (en) * | 2021-03-31 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Floating gate type split gate flash memory device structure and manufacturing process thereof |
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