CN113113415A - Floating gate type split gate flash memory device structure and manufacturing process thereof - Google Patents
Floating gate type split gate flash memory device structure and manufacturing process thereof Download PDFInfo
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Abstract
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a floating gate type split gate flash memory device structure and a manufacturing process thereof. Wherein the structure includes: a substrate layer, and a gate structure grown on the substrate layer; forming source and drain regions in the substrate layers positioned at two sides of the grid structure; the grid structure comprises a first split grid structure and a second split grid structure which are spaced; the first gate dividing structure and the second gate dividing structure respectively comprise a floating gate structure and a control gate structure which are sequentially stacked from bottom to top; a selection gate structure is arranged between the first gate dividing structure and the second gate dividing structure at intervals; the control gate structure includes a P-type doped control gate polysilicon layer. The process is used for forming the floating gate type split gate flash memory device structure. The structure and the manufacturing process thereof can solve the problem that in the related art, in order to adapt to device shrinkage and reduce device leakage, the ion implantation dosage of the first P-type region is increased, so that the junction breakdown voltage of the device is reduced.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a floating gate type split gate flash memory device structure and a manufacturing process thereof.
Background
The floating gate type split gate flash memory is widely applied to various embedded electronic products such as financial IC cards, automotive electronics and the like because the floating gate type split gate flash memory is beneficial to saving chip area and improving storage integration density.
Fig. 1 is a schematic cross-sectional view illustrating a floating gate type split-gate flash memory device in the related art, and referring to fig. 1, the floating gate type split-gate flash memory device includes a first P-type region 17 formed in a P-type substrate 11, and the first P-type region 17 is used for preventing device punch-through. A drain region 25 and a source region 24 are respectively formed in the P-type substrate 11 at two sides of the first P-type region 17, and the LDD region 22 is formed in the P-type substrate 11 at one side of the first P-type region 17 adjacent to the drain region 25 and the source region 24. A gate structure is formed on the first P-type region 17, the gate structure includes a first gate dividing structure a and a second gate dividing structure B, a select gate structure C is formed between the first gate dividing structure a and the second gate dividing structure B, and dielectric layers 16, 18, and 19 are respectively isolated between the first gate dividing structure a and the select gate structure C, and between the second gate dividing structure B and the select gate structure C. A second P-type region 117 is formed in the first P-type region 17 under the select gate structure C, and the second P-type region 117 is used to increase the threshold voltage of the device.
In addition, the first gate dividing structure a and the second gate dividing structure B both include a floating gate dielectric layer 12, a floating gate polysilicon layer 13, an inter-polysilicon dielectric layer 14 and a control gate polysilicon layer 15 which are sequentially stacked from bottom to top. The selection gate structure C comprises a selection gate dielectric layer 19, a selection gate polycrystalline silicon layer 20 and a selection gate protective layer 21 which are sequentially stacked from bottom to top.
However, as flash memory devices are continuously scaled, control gates are also continuously scaled, so that control of the control gates to channels is weaker and weaker, and the threshold voltage of the flash memory devices is reduced after the flash memory devices are programmed. The reduction of the threshold voltage of the device may cause leakage problems of the device. If the ion implantation dosage of the first P-type region is increased in order to reduce the leakage of the device, the increase of the ion implantation dosage of the first P-type region also reduces the junction breakdown voltage of the device.
Disclosure of Invention
The application provides a floating gate type split gate flash memory device structure and a manufacturing process thereof, which can solve the problem that in the related art, in order to adapt to device shrinkage and reduce device electric leakage, the ion implantation dosage of a first P type area is increased, so that the junction breakdown voltage of the device is reduced.
In order to improve the threshold voltage of the micro device and improve the junction breakdown voltage of the flash memory device as much as possible, a first aspect of the present application provides a floating gate type split gate flash memory device structure, which includes: a substrate layer, and a gate structure grown on the substrate layer; forming source and drain regions in the substrate layers positioned at two sides of the grid structure;
the grid structure comprises a first split grid structure and a second split grid structure which are spaced;
the first gate dividing structure and the second gate dividing structure respectively comprise a floating gate structure and a control gate structure which are sequentially stacked from bottom to top;
a selection gate structure is arranged between the first gate dividing structure and the second gate dividing structure at intervals;
the control gate structure includes a P-type doped control gate polysilicon layer.
Optionally, the select gate structure includes an N-type doped select gate polysilicon layer.
Optionally, a first injection region is formed at a position of the substrate layer in contact with the select gate structure; the first implantation region extends downwards from the upper surface of the substrate layer and is used for adjusting the threshold voltage of a selection device.
Optionally, the impurity implantation dose of the P-type doped control gate polysilicon layer is 5e14cm-2～5e15 cm-2。
Optionally, the impurity implantation energy of the P-type doped control gate polysilicon layer is 2KeV to 20 KeV.
Optionally, the gate structure is grown in a flash memory cell area, and a second injection area is formed in the substrate layer at the position of the flash memory cell area; the second injection region extends downwards from the upper surface of the substrate layer and is used for adjusting the threshold voltage of the floating gate storage transistor and preventing the floating gate storage transistor from being penetrated.
In a second aspect of the present application, a manufacturing process of a floating gate type split gate flash memory device structure is provided, the manufacturing process includes the following steps:
providing a substrate layer with a floating gate structure and a control gate structure deposited on the upper surface in sequence; the control gate structure comprises a control gate intrinsic polycrystalline silicon layer;
defining a flash memory cell area through the mask layer;
injecting P-type impurity ions, so that the P-type impurity ions enter the control gate intrinsic silicon layer at the position of the flash memory cell region to form a P-type doped control gate polycrystalline silicon layer;
forming two first side walls on the P-type doped control gate polycrystalline silicon layer and attached to two side edges of the mask layer respectively;
etching to remove the control gate structure which is not covered with the first side wall at the position of the flash memory cell region, so that the floating gate structure of the layer is exposed;
two second side walls are respectively formed on the exposed floating gate structure and attached to the side edges of the two first side walls;
etching to remove the floating gate structure of the flash memory cell region without covering the first side wall and the second side wall, so that the substrate layer is exposed;
manufacturing a selection gate structure, so that the selection gate structure is in contact with the exposed substrate layer, and the first side wall and the second side wall which are positioned at two different side edges are separated;
and manufacturing and forming source and drain regions on two sides of the flash memory cell region.
Optionally, in the step of performing P-type impurity ion implantation to make the P-type impurity ion enter the control gate polysilicon layer at the location of the flash memory cell region, the implantation dosage for performing P-type impurity ion implantation is: 5e14cm-2～5e15 cm-2。
Optionally, in the step of performing P-type impurity ion implantation to make the P-type impurity ion enter the control gate polysilicon layer at the location of the flash memory cell region, implantation energy for performing P-type impurity ion implantation is: 2KeV to 20 KeV.
The technical scheme at least comprises the following advantages: according to the method and the device, the doping concentration of the first injection region can be guaranteed to be unchanged, so that the threshold voltage of the programmed flash memory cell is improved and the leakage current of the flash memory cell is reduced on the premise that the breakdown voltage BV of the junction is not affected by the shadow.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic cross-sectional structural view showing a floating gate type split gate flash memory device in the related art;
fig. 2 is a schematic cross-sectional structural diagram illustrating a floating gate type split-gate flash memory device structure according to an embodiment of the present application;
FIG. 3 is a flow chart of a process for fabricating a floating gate type split gate flash memory device structure according to an embodiment of the present disclosure;
fig. 4a is a schematic cross-sectional structural diagram of a device after completion of step S1 in a manufacturing process according to an embodiment of the present application;
fig. 4b is a schematic cross-sectional structural diagram of the device after completion of step S2 in the manufacturing process provided by the embodiment of the present application;
fig. 4c is a schematic cross-sectional structural diagram of the device after completion of step S3 in the manufacturing process provided by the embodiment of the present application;
FIG. 4d is a schematic cross-sectional diagram of a device formed by a second implantation region in accordance with an embodiment of the present disclosure;
fig. 4e shows a schematic cross-sectional structure diagram of the device after the completion of step S3 in the manufacturing process provided by the embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 2 is a schematic cross-sectional structural diagram illustrating a floating gate type split-gate flash memory device structure according to an embodiment of the present application, and referring to fig. 2, the floating gate type split-gate flash memory device structure includes:
a substrate layer 101, and a gate structure grown on the substrate layer 101. Source and drain regions 114 are formed in the substrate layer on either side of the gate structure. The area where the gate structure is formed is a flash memory cell area.
The gate structure comprises a first gate-splitting structure 21 and a second gate-splitting structure 22 which are spaced apart. The first gate-splitting structure 21 and the second gate-splitting structure 22 are respectively located at two opposite sides of the flash memory cell area.
The first gate dividing structure 21 and the second gate dividing structure 22 both include a floating gate structure 31 and a control gate structure 32 stacked in sequence from bottom to top. The floating gate structure 31 comprises a floating gate dielectric layer 102 and a floating gate polysilicon layer 103 which are sequentially stacked on a substrate layer 101 of the flash memory cell region from bottom to top; the control gate structure 32 includes an interpoly dielectric layer 104 and a control gate polysilicon layer 105 sequentially stacked on the floating gate polysilicon layer 103 from bottom to top.
In this embodiment, the control gate structure 32 of the first gate dividing structure 21 and the control gate structure 32 of the second gate dividing structure 22 respectively cover the side portions corresponding to the floating gate structure 31. The control gate structure 32 of the first gate dividing structure 21 and the control gate structure 32 of the second gate dividing structure 22 are covered with first sidewalls 106. The outer edges of the first sidewalls 106 of the first gate structures 21 and the outer edges of the first sidewalls 106 of the second gate structures 21 are respectively formed with second sidewalls 108. The second sidewall spacers 108 are located at the portion of the floating gate structure 31 not covered with the control gate structure 32.
A selection gate structure is arranged between the first gate dividing structure 21 and the second gate dividing structure 22. In this embodiment, the select gate structure includes a select gate dielectric layer 109 and a select gate polysilicon layer 110 sequentially stacked from bottom to top. The select gate dielectric layer 109 covers the exposed surfaces of the first sidewall 106, the second sidewall 108, and the substrate layer 101 in the flash memory cell region. The select gate dielectric layer 109 surrounds a space formed for filling a select gate polysilicon layer, and a select gate polysilicon layer 110 is filled in the space, so that the select gate structure spaces the first gate runner structure 21 and the second gate runner structure 22.
The control gate structure includes a P-type doped control gate polysilicon layer. In this embodiment, the P-type doped control gate polysilicon layer may be formed in long shape during the manufacture of the control gate structureForming a control gate intrinsic polycrystalline silicon layer, and then injecting low-energy P-type impurity ions to dope the control gate polycrystalline silicon layer at the position of the flash memory cell region with the P-type impurity ions to form a P-type doped control gate polycrystalline silicon layer. Wherein, the impurity implantation dosage of the P-type doped control gate polysilicon layer is 5e14cm-2～5e15 cm-2The impurity implantation energy is 2 KeV-20 KeV. In other embodiments, in-situ doping may be used to form a P-type doped control gate polysilicon layer when the control gate polysilicon layer of the control gate structure is fabricated.
Work function difference of P-type control grid polycrystalline silicon layer
Work function of polysilicon layer compared with other control gates
The threshold voltage of the formed flash memory unit cell is high, so that the leakage current of the flash memory unit cell is greatly reduced, and meanwhile, the doping concentration of the first injection region is unchanged, so that the breakdown voltage BV of the junction is not influenced.
Fig. 3 is a flowchart illustrating a process for manufacturing a floating gate type split-gate flash memory device structure according to an embodiment of the present application, and referring to fig. 3, the process for manufacturing the floating gate type split-gate flash memory device structure includes the following steps:
step S1: providing a substrate layer with a floating gate structure and a control gate structure deposited on the upper surface in sequence; the control gate structure includes a control gate intrinsic polysilicon layer.
Wherein the substrate may be a P-type substrate layer doped with P-type impurity ions. When the floating gate structure and the control gate structure are manufactured on the substrate layer, a floating gate dielectric layer and a floating gate polycrystalline silicon layer can be manufactured on the upper surface of the substrate layer in sequence to form the floating gate structure, and the floating gate dielectric layer can be made of silicon dioxide; and then sequentially manufacturing an inter-polysilicon dielectric layer and a control gate intrinsic polysilicon layer on the floating gate structure to form a control gate structure, wherein the inter-polysilicon dielectric layer can be a composite structure of a silicon oxide layer and a silicon nitride layer, such as a lower silicon oxide layer, a silicon nitride layer and an upper silicon oxide layer which are sequentially stacked from bottom to top. In addition, the control gate intrinsic polysilicon layer is a polysilicon layer which is not doped.
Referring to fig. 4a, which shows a schematic cross-sectional structure of the device after step S1 is completed, as can be seen from fig. 4a, a floating gate dielectric layer 102, a floating gate polysilicon layer 103, an inter-polysilicon dielectric layer 104 and a control gate intrinsic polysilicon layer 105 are formed on the upper surface of the substrate layer 101, which are sequentially stacked from bottom to top.
Step S2: and defining a flash memory cell area through the mask layer.
In this embodiment, step S2 may include: a mask layer is deposited on the control gate intrinsic polysilicon layer formed in step S1, and the mask layer is etched by a photolithography process, so that the flash memory cell region is defined by the mask layer, i.e., the control gate intrinsic polysilicon layer in the flash memory cell region is exposed. The material of the mask layer can be silicon nitride.
Referring to fig. 4b, which shows a schematic cross-sectional structure of the device after step S2 is completed, as can be seen from fig. 4b, the mask layer 501 covers the control gate intrinsic polysilicon layer 105, and the mask layer 501 has openings to define the flash memory cell region 10, and the upper surface of the control gate intrinsic polysilicon layer 501 at the position of the flash memory cell region 10 is exposed.
Step S3: and injecting P-type impurity ions, so that the P-type impurity ions enter the control gate intrinsic silicon layer at the position of the flash memory cellular region to form a P-type doped control gate polycrystalline silicon layer.
After step S2, since the mask layer defines the flash memory cell region, the upper surface of the control gate intrinsic polysilicon layer at the position of the flash memory cell region is exposed, so that in the process of injecting P-type impurity ions in step S3, the mask layer is used as a mask to make the P-type impurity ions enter the control gate intrinsic polysilicon layer at the position of the flash memory cell region, thereby forming a P-type doped control gate polysilicon layer.
In this embodiment, the P-type impurity ions may be any one or a combination of boron ions, boron fluoride ions, or indium ions. When boron ions are used as the P-type impurity ions,the implantation energy can be made to be 2KeV to 20KeV, so that the implantation dose is: 5e14cm-2～5e15 cm-2It should be noted that, when the P-type impurity ion implantation is performed to form the P-type doped control gate polysilicon layer, the implantation energy is low, so that the implantation does not penetrate through the control gate and the floating gate structure, and only enters the control gate intrinsic silicon layer at the position of the flash memory cell region.
When the P-type doped control gate polysilicon layer is formed, the energy of the implantation is 50 KeV-150 KeV, and the dosage is 2e12 cm-2～1.5e13cm-2The boron impurity ions can sequentially penetrate through the control gate structure and the floating gate structure from top to bottom and enter the substrate layer due to the high injection energy, so that a first injection region is formed in the substrate layer at the position of the flash memory cell region and extends downwards from the upper surface of the substrate layer to control the threshold voltage of the floating gate structure and prevent punch-through.
Referring to fig. 4c, a schematic cross-sectional structural view of the device after step S3 is completed is shown. As can be seen from fig. 4c, a P-type doped control gate polysilicon layer 115 is formed at the location of the flash memory cell region 10, and the remaining control gate intrinsic polysilicon layer 105 is covered with a mask layer 501. And a first injection region 107 is formed in the substrate layer 101 at the location of the flash memory cell region 10, the first injection region 107 extending downward from the upper surface of the substrate layer 101.
Step S4: and respectively forming two first side walls on the P-type doped control gate polycrystalline silicon layer and attached to two side edges of the mask layer.
In this embodiment, a first dielectric layer may be deposited on the surface of the device after step S3, and the first dielectric layer may be made of silicon oxide. And performing anisotropic etching on the first dielectric layer to enable two first side walls to be respectively formed on the P-type doped control gate polycrystalline silicon layer and attached to two side edges of the mask layer. It should be noted that, the first sidewall covers the region of the P-type doped control gate polysilicon layer, and the length of the final control gate structure in each split gate structure is defined. The two first side walls are spaced, and the P-type doped control gate polysilicon layer and the interpoly dielectric layer in the region between the two first side walls are etched and removed in the subsequent steps.
Step S5: and etching to remove the control gate structure which is not covered with the first side wall at the position of the flash memory cell region, so that the floating gate structure is exposed.
And etching and removing the exposed control gate structure by using the first side walls and the mask layer as masks through an etching process, namely etching and removing the P-type doped control gate polysilicon layer and the interpoly dielectric layer in the region between the two first side walls in the flash memory cell region to expose the floating gate polysilicon of the lower floating gate structure.
Step S6: and two second side walls are respectively formed on the exposed floating gate structure by attaching to the side edges of the two first side walls.
In this embodiment, a second dielectric layer may be deposited on the surface of the device after step S5, where the second dielectric layer may be made of silicon oxide. And performing anisotropic etching on the second dielectric layer, so that two second side walls are respectively formed on the exposed floating gate structure and attached to the side edges of the two first side walls. The two second side walls are spaced, and the floating gate polysilicon layer and the floating gate dielectric layer in the region between the two second side walls are etched and removed in the subsequent steps.
Step S7: and etching to remove the floating gate structures of the first side wall and the second side wall at the position of the flash memory cell area without covering the floating gate structures, so that the substrate layer is exposed.
And etching and removing the exposed floating gate structure by using the first side wall and the second side wall as masks through an etching process, namely etching and removing the floating gate polysilicon layer and the floating gate dielectric layer in the region between the two second side walls in the flash memory cell region to expose the substrate layer at the lower layer.
After step S7 is completed, the ion implantation process may be continued by using the first and second sidewalls as masks, so that a second implantation region is formed in the exposed substrate layer, where the second implantation region is located in the first implantation region.
Referring to fig. 4d, a schematic cross-sectional structure of the device after forming the second implantation region is shown. As can be seen from fig. 4d, a first injection region 107 is formed in the substrate layer 101 at the location of the flash memory cell region 10, and a first split-gate structure 21 and a second split-gate structure 22 are formed on the first injection region 107 at intervals, wherein the first split-gate structure 21 and the second split-gate structure 22 respectively include their respective control gate structures and floating gate structures. The length of the control gate structure is defined by the first sidewall 106, the length of the floating gate structure is defined by the first sidewall 106 and the second sidewall 108, and the floating gate structure and the control gate structure are stepped, so that the first sidewall 106 covering the control gate structure and the second sidewall 108 covering the floating gate structure are also stepped. A second implant region 115 is formed in the first implant region 107 at spaced locations between the two floating gate structures.
Step S8: and manufacturing a selection gate structure, so that the selection gate structure is in contact with the exposed substrate layer and separates the first side wall and the second side wall which are positioned at two different side edges.
A select gate dielectric layer and a select gate polysilicon layer may be deposited in sequence on the structure shown in fig. 4d, and then a self-aligned select gate structure may be formed by a chemical mechanical polishing process.
Referring to fig. 4e, a schematic cross-sectional structure diagram of the device after step S8 is completed is shown. As can be confirmed from fig. 4e, the deposited select gate dielectric layer 109 covers the surfaces of the exposed first sidewall 106, the second sidewall 108, and the surface of the second implantation region 115 to form a filling space, and the select polysilicon layer 110 is filled in the filling space, so as to separate the first gate dividing structure from the second gate dividing structure.
Step S9: and manufacturing and forming source and drain regions on two sides of the flash memory cell region.
The process of step S9 may include: on the device structure shown in fig. 4e, a select gate protection layer is formed on the surface of the select polysilicon layer 110 by a thermal oxidation process. And then, etching by taking the first side wall, the selection gate dielectric layer and the selection gate protective layer as mask layers, and removing the device structure in the region except the flash memory cell region. And forming source and drain regions in the substrate layers at two sides of the flash memory cell region, and forming third side walls on the substrate layers at two sides of the flash memory cell region, wherein the third side walls separate two adjacent flash memory cell regions. After step S9 is completed, a schematic cross-sectional structure diagram of the floating gate type split-gate flash memory device structure shown in fig. 2 is formed.
The following table 1 shows a parameter table obtained by respectively simulating the structures of the floating gate type split gate flash memory device provided by the related art and the embodiment of the present application:
TABLE 1
| Vtp(V) | Ir01(A/um) | BV(V) | |
| Prior Art | 0.688 | 3.79E-07 | 7.60E+00 |
| This example | 1.773 | 1.01E-08 | 7.60E+00 |
Where Vtp represents a threshold voltage of the flash memory cell after programming, Ir01 represents a leakage current of the flash memory cell, and BV represents a junction breakdown voltage of the flash memory cell.
The floating gate type split gate flash memory device structure provided in the embodiment of the invention and the manufacturing process thereof are beneficial to manufacturing the device structureWork function difference with doped polysilicon gate
Work function of polysilicon gate more heavily doped than N type
The high characteristic is about 1.2V, so that the threshold voltage Vtp of the flash memory cell after programming is improved by about 1.1V, and further the leakage current Ir01 of the flash memory cell is greatly reduced. Meanwhile, the doping concentration of the first injection region is ensured to be unchanged, so that the breakdown voltage BV of the junction is not influenced.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (9)
1. A floating gate type split gate flash memory device structure, comprising: a substrate layer, and a gate structure grown on the substrate layer; forming source and drain regions in the substrate layers positioned at two sides of the grid structure;
the grid structure comprises a first split grid structure and a second split grid structure which are spaced;
the first gate dividing structure and the second gate dividing structure respectively comprise a floating gate structure and a control gate structure which are sequentially stacked from bottom to top;
a selection gate structure is arranged between the first gate dividing structure and the second gate dividing structure at intervals;
the control gate structure includes a P-type doped control gate polysilicon layer.
2. The floating gate type split gate flash memory device structure of claim 1, wherein the select gate structure comprises an N-type doped select gate polysilicon layer.
3. The floating gate type split-gate flash memory device structure of claim 2, wherein a first implant region is formed at a substrate layer location in contact with the select gate structure; the first implantation region extends downwards from the upper surface of the substrate layer and is used for adjusting the threshold voltage of a selection device.
4. The floating gate type split gate flash memory device structure of claim 1, wherein the P-type doped control gate polysilicon layer has an impurity implantation dose of 5e14cm-2～5e15cm-2。
5. The floating gate type split gate flash memory device structure of claim 1, wherein the impurity implantation energy of the P-type doped control gate polysilicon layer is 2KeV to 20 KeV.
6. The floating gate type split-gate flash memory device structure of claim 1, wherein the gate structure is grown in a flash cell region, a second implant region being formed in the substrate layer at the location of the flash cell region; the second injection region extends downwards from the upper surface of the substrate layer and is used for adjusting the threshold voltage of the floating gate storage transistor and preventing the floating gate storage transistor from being penetrated.
7. A manufacturing process of a floating gate type split gate flash memory device structure is characterized by comprising the following steps:
providing a substrate layer with a floating gate structure and a control gate structure deposited on the upper surface in sequence; the control gate structure comprises a control gate intrinsic polycrystalline silicon layer;
defining a flash memory cell area through the mask layer;
injecting P-type impurity ions, so that the P-type impurity ions enter the control gate intrinsic silicon layer at the position of the flash memory cell region to form a P-type doped control gate polycrystalline silicon layer;
forming two first side walls on the P-type doped control gate polycrystalline silicon layer and attached to two side edges of the mask layer respectively;
etching to remove the control gate structure which is not covered with the first side wall at the position of the flash memory cell region, so that the floating gate structure of the layer is exposed;
two second side walls are respectively formed on the exposed floating gate structure and attached to the side edges of the two first side walls;
etching to remove the floating gate structure of the flash memory cell region without covering the first side wall and the second side wall, so that the substrate layer is exposed;
manufacturing a selection gate structure, so that the selection gate structure is in contact with the exposed substrate layer, and the first side wall and the second side wall which are positioned at two different side edges are separated;
and manufacturing and forming source and drain regions on two sides of the flash memory cell region.
8. The process of claim 7, wherein the step of implanting P-type impurity ions into the control gate polysilicon layer at the location of the flash memory cell region comprises the following steps: 5e14cm-2～5e15cm-2。
9. The process of claim 7, wherein the step of implanting P-type impurity ions into the control gate polysilicon layer at the location of the flash memory cell region comprises the following steps: 2KeV to 20 KeV.
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| CN109148599A (en) * | 2018-09-29 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Floating gate type grid flash memory and its manufacturing method |
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