CN108565265A - A kind of three-dimensional storage and its data manipulation method - Google Patents
A kind of three-dimensional storage and its data manipulation method Download PDFInfo
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- CN108565265A CN108565265A CN201810344451.5A CN201810344451A CN108565265A CN 108565265 A CN108565265 A CN 108565265A CN 201810344451 A CN201810344451 A CN 201810344451A CN 108565265 A CN108565265 A CN 108565265A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The present invention provides a kind of three-dimensional storage and its data manipulation method, three-dimensional storage includes compound substrate, and compound substrate includes the first semiconductor layer of metal substrate and formation on the metallic substrate, and the first semiconductor layer is the first doping type；Stack layer is formed in compound substrate, if stack layer includes along perpendicular to the spaced dried layer grid layer in the direction of compound substrate；Across the raceway groove hole of stack layer；Channel layer in raceway groove hole；The doped region of the second doping type in the first semiconductor layer, doped region form Ohmic contact with metal substrate, so that the public source of memory includes at least the first semiconductor layer, metal substrate.Data manipulation method step is simple, can realize efficient whole erasing.Memory provided by the present invention has lower source resistances, and device performance is more excellent, and operating procedure is simple, and efficiency is higher.
Description
Technical field
The present invention relates to flash memories field more particularly to a kind of three-dimensional storages and its data manipulation method.
Background technology
In order to meet the development of efficient and cheap microelectronic industry, semiconductor storage unit needs to have higher integrated
Density.It is because their integration density is very important in terms of determining product price, i.e., high about semiconductor storage unit
Density is integrated to be very important.For traditional two dimension and planar semiconductor memory part, because of their integration density master
Will depend on single memory device shared by unit area, integrated level be highly dependent on photoetching, masking process quality.But
Even if constantly improving photoetching, masking process precision with expensive process equipment, the promotion of integration density remains very limited
's.
As the replacement for overcoming this two-dimentional limit, three-dimensional semiconductor memory device is suggested.Three-dimensional semiconductor memory
It is necessary to have the techniques that can obtain lower manufacturing cost for part, and can obtain positive means structure.
In the prior art, in order to realize to three-dimensional storage data erasing the stage using body erasing (Body Erase, change
Becoming grid can cause to incude potential change in source-drain area and charge storage layer, whole to wipe) mode, be commonly stored device
Source electrode is formed in a silicon substrate.And since using silicon substrate, source electrode line has high resistance, need frequent, a large amount of gold
Belong to wiring to reduce the resistance value of source electrode line.When expanding memory core area size, improving memory capacity, it is easy to be limited to
Interference caused by the high resistance of source electrode line or a large amount of metal lines.Therefore, there is an urgent need for one kind capable of effectively reducing source electrode line electricity
Resistance value, and the memory core heart district of extension is suitble to stack scheme.
Invention content
A brief summary of one or more aspects is given below to provide to the basic comprehension in terms of these.This general introduction is not
The extensive overview of all aspects contemplated, and be both not intended to identify critical or decisive element in all aspects also non-
Attempt to define the range in terms of any or all.Its unique purpose is to provide the one of one or more aspects in simplified form
A little concepts are with the sequence for more detailed description given later.
To solve the above-mentioned problems, the present invention provides a kind of three-dimensional storages, including：Compound substrate, above-mentioned composite lining
Bottom includes metal substrate and the first semiconductor layer being formed in above-mentioned metal substrate, and above-mentioned first semiconductor layer is mixed for first
Miscellany type；Stack layer is formed in above-mentioned compound substrate, and above-mentioned stack layer includes along between the direction of above-mentioned compound substrate
If every the dried layer grid layer of setting；Across the raceway groove hole of above-mentioned stack layer；Channel layer in above-mentioned raceway groove hole；Positioned at above-mentioned
The doped region of the second doping type in first semiconductor layer, above-mentioned doped region form Ohmic contact with above-mentioned metal substrate, with
The public source of above-mentioned memory is set to include at least above-mentioned first semiconductor layer, above-mentioned metal substrate.
Optionally, further include：At least across the grid line separate slot of above-mentioned stack layer；Filling in above-mentioned grid line separate slot
Object；Above-mentioned doped region is located at the lower section of above-mentioned grid line separate slot.
Optionally, above-mentioned filler includes metal layer and the insulating layer between above-mentioned metal layer and grid layer, on
The side wall that insulating layer covers above-mentioned grid line separate slot is stated, above-mentioned metal layer is extended to along above-mentioned direction and is connect with above-mentioned metal substrate,
Above-mentioned public source also includes above-mentioned metal layer.
Optionally, further include：Isolation layer between above-mentioned metal substrate and above-mentioned first semiconductor layer, above-mentioned metal
Layer is connect across above-mentioned isolation layer with above-mentioned metal substrate along above-mentioned direction.
Optionally, the material of above-mentioned metal layer includes W.
Optionally, above-mentioned filler is insulant.
Optionally, further include：Second of the second doping type between above-mentioned metal substrate and the first semiconductor layer
Semiconductor layer；Above-mentioned doped region diffuses to along above-mentioned direction and forms above-mentioned Ohmic contact with above-mentioned metal substrate.
Optionally, the material of above-mentioned second semiconductor layer includes polysilicon.
Optionally, above-mentioned doped region is heavily doped region.
Optionally, above-mentioned first doping type is p-type, and above-mentioned second doping type is N-type.
Optionally, the material of above-mentioned first semiconductor layer includes polysilicon.
Optionally, the material of above-mentioned metal substrate includes WSi.
Optionally, further include：The barrier layer that is set gradually between above-mentioned grid layer and above-mentioned channel layer, charge-trapping
Layer, tunnel layer.
Optionally, above-mentioned memory is configured to：When carrying out data read operation to above-mentioned memory, electric current is from above-mentioned storage
The drain region of device flows to above-mentioned public source, and further, electric current is from above-mentioned first semiconductor layer at least via above-mentioned doping
Area at least flows to above-mentioned metal substrate.
Optionally, above-mentioned memory is configured to：When carrying out data read operation to above-mentioned memory, above-mentioned drain region access
Bias voltage, above-mentioned public source ground connection；The above-mentioned grid layer of not selected storage unit accesses conducting voltage, above-mentioned conducting
Voltage is enough that above-mentioned channel layer is made to be connected；Voltage is read in the above-mentioned grid layer access of selected storage unit.
Optionally, above-mentioned memory is configured to：When carrying out data erasing operation to above-mentioned memory, electric current is from above-mentioned first
Semiconductor layer flows to above-mentioned grid layer.
Optionally, above-mentioned memory is configured to：When carrying out data erasing operation to above-mentioned memory, the leakage of above-mentioned memory
Polar region is floating, and above-mentioned grid layer ground connection, above-mentioned first semiconductor layer accesses erasing voltage, and above-mentioned erasing voltage is enough to make above-mentioned deposit
Tunneling effect occurs for reservoir.
Optionally, above-mentioned memory is 3D nand memories.
The present invention also provides a kind of data manipulation method such as above-mentioned three-dimensional storage, above-mentioned data manipulation method packets
The operating method of digital independent is included, the operating method of above-mentioned digital independent includes that the drain region of above-mentioned memory is made to access biased electrical
Pressure；Above-mentioned public source is set to be grounded；The above-mentioned grid layer of not selected storage unit is set to access conducting voltage, above-mentioned electric conduction
Pressure is enough that above-mentioned channel layer is made to be connected；So that the above-mentioned grid layer of selected storage unit is accessed and reads voltage；Sensing is selected
Storage unit above-mentioned drain region and above-mentioned common source region between voltage, and/or, curent change is to judge above-mentioned storage
The data mode of unit.
Optionally, the ranging from 0.3-0.5V of above-mentioned bias voltage；The ranging from 3-8V of above-mentioned conducting voltage.
Optionally, above-mentioned data manipulation method further includes the operating method of data erasing, the operation side of above-mentioned data erasing
Method includes：Keep above-mentioned drain region floating；Above-mentioned grid layer is set to be grounded；Make above-mentioned first semiconductor layer access erasing voltage, it is above-mentioned
Erasing voltage is enough to make above-mentioned memory that tunneling effect occurs, so that the electronics stored in memory is attracted to above-mentioned the first half
Conductor layer.
Optionally, the operating method of above-mentioned data erasing further comprises：Keep above-mentioned metal substrate floating, or, in access
State erasing voltage.
Optionally, the ranging from 14-20V of above-mentioned erasing voltage.
Optionally, above-mentioned data manipulation method further includes the operating method of data programming, the operation side of above-mentioned data programming
Method includes：Above-mentioned drain region is set to be grounded；Above-mentioned public source is set to be grounded；Make above-mentioned grid layer access program voltage, above-mentioned programming
Voltage is enough to make above-mentioned memory that tunneling effect occur, so as to be stored with electronics in memory.
Optionally, the ranging from 12-27V of above-mentioned program voltage.
Memory provided by the present invention can utilize the first semiconductor layer to realize that body is wiped, and improve memory erasing behaviour
The efficiency of work, and by the resistance of the metal substrate reduction source electrode in compound substrate, improve the response speed of memory, be easy
Realize stacking and the extension of memory.
Description of the drawings
Fig. 1-4 shows the part-structure schematic diagram of the section of different three-dimensional storage embodiments provided by the invention.
Fig. 5 shows an embodiment flow chart of the manufacturing method for manufacturing three-dimensional storage provided by the invention.
Fig. 6 shows the flow chart of the data reading step of the data manipulation method of three-dimensional storage provided by the invention.
Fig. 7 shows the flow chart of the data erasure step of the data manipulation method of three-dimensional storage provided by the invention.
Fig. 8 shows that the data of the data manipulation method of three-dimensional storage provided by the invention write the flow chart of step.
Specific implementation mode
The present invention relates to semiconductor technologies and device.More specifically, the embodiment of the present invention provides a kind of semiconductor storage
Device, the semiconductor memory are three-dimensional storage, including compound substrate, and compound substrate includes metal substrate and is formed in metal
The first semiconductor layer on substrate.By the formation of metal substrate in compound substrate, three-dimensional storage source electrode is effectively reduced
Resistance value effectively improves the efficiency of erasing of three-dimensional storage, the property in memory core region by the formation of the first semiconductor layer
It can be more excellent.The present invention also provides other embodiments.
It provides and is described below so that those skilled in the art can implement and using the present invention and be incorporated into specific
In application background.Various modifications and various uses in different application will be readily apparent for those skilled in the art
, and general principle defined herein is applicable to the embodiment of wider range.The present invention is not limited to herein as a result,
The embodiment provided, but the broadest range consistent with principle disclosed herein and novel features should be awarded.
In the following detailed description, many specific details are elaborated to provide the more thorough understanding to the present invention.However, right
In it should be apparent to those skilled in the art that the practice of the present invention can need not be confined to these details.In other words, known
Structure and device be shown in block diagram form without display the details of, to avoid the fuzzy present invention.
Note that use in the case of, it is mark left, right, front and rear, top, bottom, positive and negative, clockwise and anticlockwise only
It is used for convenience, and does not imply that any specific fixed-direction.In fact, they are used for reflection pair
Relative position between the various pieces of elephant and/or direction.
When describing the embodiments of the present invention, for purposes of illustration only, indicating that the sectional view of device architecture can disobey general proportion work
Partial enlargement, and schematic diagram is example, should not limit the scope of protection of the invention herein.In addition, in actual fabrication
Should include length, width and depth three-dimensional space.
As used herein term " ... top (over) ", " ... lower section (under) ", " ... between
(between) " and " ... upper (on) " refer to this layer relative to other layers of relative position.Similarly, for example, by sinking
It is there are one product or be placed on above or below in the of another layer one layer can contact directly with another layer or can be had or more
A middle layer.In addition, one layer being deposited or being placed between layer can directly contact with these layers or can have one
A or multiple middle layers.In contrast, it is contacted with the second layer in the first layer of second layer "upper".Further it is provided that one layer of phase
For other layers of relative positions (assuming that film operation is deposited, changed and removed relative to starting substrates without considering base
The absolute orientation at bottom).
In order to achieve the above object, the resistance value of memory source polar curve is reduced, memory performance is improved, the present invention provides
A kind of three-dimensional storage, Fig. 1-4 show that the part-structure of the section of different three-dimensional storage embodiments provided by the invention shows
It is intended to.
As shown in Figure 1, three-dimensional storage provided by the present invention includes compound substrate 110, stack layer 120, channel layer
130, drain region 140, grid line separate slot and the filler 150 being filled in grid line separate slot and doped region 160.
Specifically, compound substrate 110 includes metal substrate 1101 and what is be formed in metal substrate 1101 the first half lead
Body layer 1102, the material of metal substrate 1101 can be preferably the silicide of tungsten.The material of first semiconductor layer 1102
It is the first doping type including polysilicon.
Stack layer 120 is formed in compound substrate 110, is that grid layer 1201 and interlayer insulating film 1202 are alternately laminated.Heap
Lamination 120 determines the number of plies of stack layer, the number of plies example of stack layer according to the number of the storage unit formed needed for vertical direction
It can be such as 8 layers, 32 layers, 64 layers, the number of plies of stack layer is more, can more improve integrated level.May be used chemical vapor deposition,
Atomic layer deposition or other suitable deposition methods, alternating deposit grid layer 1201 and interlayer insulating film 1202, form and are somebody's turn to do successively
Stack layer 120.Preferably, the material of grid layer 1201 can be tungsten, and the material of interlayer insulating film 1202 is silica.
Channel layer 130 is formed in (not shown) in raceway groove hole, and raceway groove hole is formed in stack layer 120, and channel layer 130 hangs down
Include directly barrier layer 1301, electricity successively along stack layer side surface between compound substrate 110, channel layer 130 and stack layer 120
Lotus trapping layer 1302, tunnel layer 1303, insulator 1304 can be filled in raceway groove hole, and the material of insulator 1304 preferably may be used
Think silica.More preferably, epitaxial layer 1305 is still further comprised between compound substrate and raceway groove hole.
Drain region 140 is formed in above raceway groove hole, more specifically, is formed on channel layer 130 and insulator 1304
Side.Adulterate the second doping type ion in drain region 140, it is preferable that the concentration of the ion adulterated can have in drain region 140
Institute is different, as shown in Figure 1, two different drain electrode sub-districts 1401,1402 of ion concentration can be formed.
It will be appreciated by those skilled in the art that the structure and system in the raceway groove hole of memory provided by the present invention, drain region
Standby technique may be used those skilled in the art at present or by three-dimensional storage raceway groove to be used hole, drain region structure and its
Preparation process, and it is not limited to above-mentioned example.
Grid line separate slot and the metal layer 150 being filled in grid line separate slot, are formed in stack layer 120, grid line separate slot (does not show
Go out) the first semiconductor layer 1102 of at least exposed composite substrate 110, in the embodiment shown in fig. 1, the exposure of grid line separate slot is multiple
The metal substrate 1101 of substrate 110 is closed, and it is metal layer 150 to be filled in grid line separate slot, since the exposure of grid line separate slot is multiple
The metal substrate 1101 of substrate 110 is closed, therefore is in direct contact between metal layer 150 and metal substrate 1101, physical contact is constituted.
The material of metal layer 150 is preferably tungsten.
More preferably, as shown in Figure 1, on the stack layer side wall that grid line separate slot is exposed, it is also formed with isolation layer 1501,
Isolation layer 1501 can isolating metal layer 150 and grid layer 1201, avoid it is short-circuit between the two, meanwhile, isolation layer 1501 can also
Enough reduce the interference between metal layer 150 and grid layer 1201 (especially when grid layer is metal gate layers).
Doped region 160 is formed in the first semiconductor layer 1102 of the compound substrate exposed via grid line separate slot, with grid line
Separate slot adjoins, and metal substrate 1101 is electrically connected with the first semiconductor layer by doped region 160, more specifically, as shown in Figure 1
Embodiment in, doped region 160 is formed in the first semiconductor layer exposed via grid line separate slot, direct with metal charge 150
Contact constitutes physical contact, therefore metal charge 150 can electrically be connected by doped region 160 and the first semiconductor layer 1102
It connects.Simultaneously because metal charge 150 and metal substrate 1101 are physically contacted, therefore so that metal substrate 1101 and the first half
Conductor layer can be electrically connected by doped region 160.
Doped region 160 is the second doping type, and doped region 160 is heavily doped region.Using the first doping type as p-type,
Two doping types are 10^19-10 for N classes, to need the implantation concentration into the first semiconductor layer 1102 when forming doped region 160
^21/cm3N-type ion so that forming PN junction between the first semiconductor layer 1102 and doped region 160 so that electric current can
It is conducting to other conductors by doped region 160.So that the public source of memory is formed in the first semiconductor layer and gold
Belong in substrate.Further, due to being filled with metal layer, in the embodiment shown in fig. 1, public source in grid line separate slot
It also include the metal layer being located in grid line separate slot.
It will be appreciated by those skilled in the art that the above-mentioned citing about doping type have it is exemplary, be not to doping
The restriction of type.
Since the public source of memory includes metal substrate 1101, resistivity is effectively reduced, in reality as shown in Figure 1
It applies in example, public source further includes the metal layer being formed in grid line separate slot, and the resistivity of source electrode more effectively declines.
Fig. 2 shows the cross sectional portion structural schematic diagrams of another embodiment of three-dimensional storage provided by the invention.
In embodiment as shown in Figure 2, most of structure of memory is identical as embodiment as shown in Figure 1, identical part-structure
It may refer to above-mentioned, details are not described herein.Wherein, difference lies in multiple with embodiment shown in FIG. 1 for embodiment shown in Fig. 2
It further includes isolation layer 1103 to close substrate 110, is formed between the first semiconductor layer 1102 and metal substrate 1101, isolation layer 1103
Enable to the electrology characteristic of compound substrate 110 more excellent.As shown in Fig. 2, the metal layer 150 in grid line separate slot is still and metal liner
Bottom 1101 be physically contacted, therefore, although doped region 160 with metal substrate 1101 physical contact, metal layer 150 still with mix
Miscellaneous area physical contact 160, and since metal layer 150 and metal silicide substrate 1101 are physically contacted so that electric current still can be with
Metal layer 150 is flowed to by doped region 160, and flows to metal substrate 1101.To realize that metal substrate 1101 is led with the first half
Electric connection between body layer.
Three-dimensional storage as shown in Figure 1 or 2 can control three-dimensional storage to carry out digital independent to memory
Operation.Specifically, three-dimensional storage provided by the present invention is by the electricity between channel layer 1303 and grid layer 1201
Lotus trapping layer 1302 captures charge, to store data.The amount of charge that electric charge capture layer 1302 captures determines that storage is single
The Vt of member.Therefore, the read operation of data is detection storage unit stored charge amount, that is, the mistake of storage unit Vt
Journey.
When carrying out data read operation to memory, bias voltage, public source ground connection are accessed in drain region 140 so that
It, can be by sensing the curent change between drain region 140 and public source (caused by potential change when being read
Curent change, also can sensing voltage variation) judge data mode that memory is stored.The range of bias voltage can be
Between 0.3-0.5V.Under these conditions, if channel layer 130 is connected, the Vt of conducting electric current and storage unit is inversely proportional, for
For memory, channel layer conducting is because being applied with the voltage more than storage unit Vt in grid.
For the storage unit not being selected, in read operation, grid layer 1201 accesses conducting voltage, so that ditch
Channel layer 130 is connected, and electric current can flow to public source from drain region 140.Conducting voltage, which is one, can ensure to be more than any one
The voltage of a storage unit Vt, but conducting voltage cannot be too big, otherwise can make memory that tunneling effect occur.The model of conducting voltage
Enclosing can be between 3-8V.
For selected storage unit, in read operation, voltage is read in the access of grid layer 1201, if it is big to read voltage
In the Vt of storage unit, then channel layer 130 can be made to be connected.By attempting to apply grid layer 1201 different reading voltage,
It is known that storage unit stored charge amount, is also known that its data stored.
Above-mentioned memory data read operation method is widely used, and is including but not limited to applied to be arranged to SLC
(Single-Level Cell, single layer cell, a storage unit store (bit) data), MLC (Multi-Level
Cell, storage unit store two bits), (Triple-Level Cell, a storage unit store three digits to TLC
According to) or QLC (Quad-Level Cell, a storage unit storage four figures evidence) scene.
In the above-described embodiments, public source is including the first semiconductor layer 1102, metal substrate 1101 and in grid line separate slot
In metal layer 150.Due to the presence of doped region so that electric current can be between the first semiconductor layer 1102 and metal layer 150
Flowing.It is above-mentioned to memory carry out data read operation when, if memory be arranged to the first doping type be p-type, second
Doping type is N-type, and electric current flows to metal substrate 1101 and metal layer 150 from the first semiconductor layer 1102 by doped region 160.
Three-dimensional storage as shown in Figure 1 or 2 can control three-dimensional storage to carry out data erasing to memory
Operation.Specifically, three-dimensional storage provided by the present invention is by the electricity between channel layer 1303 and grid layer 1201
Lotus trapping layer 1302 captures charge, to store data.Thus, the erasing operation of data is will be on electric charge capture layer 1302
The process of charge release.
When carrying out data erasing operation to memory, drain region 140 is floating (floating), and grid layer 1201 is grounded,
First semiconductor layer 1102 accesses erasing voltage.Since the first semiconductor layer 1102 is in high potential, charge-trapping can be attracted
The electronics captured in layer 1302, and erasing voltage is enough to make memory that tunneling effect occur, so that electronics success is attracted by source electrode,
And then release the electronics on electric charge capture layer 1302.The range of erasing voltage is between 14-20V.Under these conditions, electronics
It has been able to be attracted to the first semiconductor layer 1102, therefore for the metal substrate 1101 and metal layer 150 in public source
For, floating state is may be at, it can also be as the first semiconductor layer 1102 in by the state of access erasing voltage.It is excellent
Selection of land can select metal substrate 1101 and metal layer 150 being in the floating state being easier to control.
By above-mentioned method for deleting, the whole erasing (Body Erase) of memory, memory erasing operation can be realized
Ultrahigh in efficiency.In the above-described embodiments, electronics is at least attracted to the first semiconductor layer 1102, therefore electric current is led from the first half
Body layer 1102 flows to grid layer 1201.
Three-dimensional storage as shown in Figure 1 or 2 can control three-dimensional storage to carry out what data were write to memory
Operation.Specifically, three-dimensional storage provided by the present invention is by the electricity between channel layer 1303 and grid layer 1201
Lotus trapping layer 1302 captures charge, to store data.Thus, the compilation operation of data is to make electronics by electric charge capture layer
The process of 1302 captures.
When carrying out data compilation operation to memory, drain region 140 is grounded, and public source ground connection, grid layer 1201 connects
Enter program voltage.Since grid layer 1201 is in high potential, electronics can be attracted close, and program voltage is enough that memory is made to send out
Raw tunneling effect, so that electronics is captured during close to grid layer 1201 by electric charge capture layer 1302.The model of program voltage
It is trapped among between 12-27V, and different program voltages determines the electron amount in write-in electric charge capture layer 1302, to make
The distinct data states of Memory Storage Unit can be realized with different program voltages.In the above-described embodiments, electronics is inhaled
Grid layer 1201 is guided to, therefore electric current flows to drain region 140 from grid layer 1201.
Therefore memory provided by the present invention can utilize the first semiconductor layer to realize that body is wiped, and improve memory and wipe
The efficiency of division operation, and by the resistance of the metal substrate reduction source electrode in substrate, improve the response speed of memory, store
The nucleus performance of device is more excellent.
Fig. 3 shows the cross sectional portion structural schematic diagram of another embodiment of three-dimensional storage provided by the invention.
In embodiment as shown in Figure 3, most of structure of large memories is identical as embodiment as shown in Figure 1, identical part knot
Structure may refer to above-mentioned, and details are not described herein.Wherein, the difference of embodiment shown in Fig. 3 and embodiment as shown in Figure 1 exists
In the filler in grid line separate slot is insulant 350, also, in an embodiment as illustrated in figure 3, grid line separate slot exposed composite
First semiconductor layer of substrate, and the discord metal substrate of insulant 350 filled in grid line separate slot is in direct contact.In grid line separate slot
Middle filling insulation can more effectively reduce the coupling, doing between block in the memory block kept apart with grid line separate slot without 350
It disturbs.As shown in figure 3, doped region 160 is formed in the first semiconductor layer 1102, it is physically contacted with metal substrate 1101 so that the
Ohmic contact is formed via doped region 160 between semi-conductor layer 1102 and metal substrate 1101, therefore, electric current can be first
It is flowed between semiconductor layer 1102 and metal substrate 1101, the first semiconductor layer 1102 and metal substrate 1101 constitute common source
Pole, metal substrate 1101 can effectively reduce the resistance value of source electrode as a part for public source.
Fig. 4 shows the cross sectional portion structural schematic diagram of another embodiment of three-dimensional storage provided by the invention.
In embodiment as shown in Figure 4, most of structure of large memories is identical as embodiment as shown in Figure 1, identical part knot
Structure may refer to above-mentioned, and details are not described herein.Wherein, the difference of embodiment shown in Fig. 4 and embodiment as shown in Figure 1 exists
In, compound substrate 110 further includes the second semiconductor layer 1104, be formed in the first semiconductor layer 1102 and metal substrate 1101 it
Between.The semiconductor layer of unlike material is different from the associativity of metal substrate, if material and gold that the first semiconductor layer 1102 is selected
The associativity belonged between the material that substrate 1101 is selected is poor, then the material knot that material can be selected to be selected with metal substrate 1101
The preferable semiconductor of conjunction property forms the second semiconductor layer 1104 between the first semiconductor layer 1102 and metal substrate 1101, makes multiple
Close substrate 110 structure is more reliable, performance is more excellent.Meanwhile as shown in figure 4, doped region 160 is diffused into the second semiconductor layer
1104 so that doped region 160 and metal substrate 1101 are physically contacted, and Ohmic contact is formed, and therefore, electric current can be led the first half
It is flowed between body layer 1102 and metal substrate 1101, the first semiconductor layer 1102 and metal substrate 1101 constitute public source, gold
Belong to the resistance value that substrate 1101 can effectively reduce source electrode as a part for public source.
Three-dimensional storage as shown in Figure 3 or Figure 4, can control three-dimensional storage with to memory carry out digital independent,
Data are write and the operation of data erasing.The major part side of data manipulation is carried out to three-dimensional storage as shown in Figure 3 or Figure 4
Method is identical as the method for data manipulation is carried out to three-dimensional storage as shown in Figure 1 or 2, identical major part operating method with
And principle may refer to above-mentioned, details are not described herein.Wherein, embodiment as shown in Figure 3 or Figure 4, due in grid line separate slot
Filling be insulant 350, insulant 350 plays the role of isolation, no longer with grid line in embodiment as shown in Figure 1 or 2
The effect that metal layer 150 in separate slot can form public source is identical.Therefore, it is stored to three-dimensional as shown in Figure 3 or Figure 4
When device carries out data read operation, insulant 350 is no longer grounded, and electric current is no longer flow through the insulant 350 in grid line separate slot.It carries out
When data erasing operation, insulant 350 does not need floating or access erasing voltage.When carrying out data compilation operation, insulant 350
No longer it is grounded.
Memory provided by the present invention can utilize the first semiconductor layer to realize that body is wiped, and improve memory erasing behaviour
The efficiency of work, and by the resistance of the metal substrate reduction source electrode in compound substrate, improve the response speed of memory, be easy
Realize stacking and the extension of memory.
It will be appreciated by those skilled in the art that three-dimensional storage provided by the present invention can be set to NAND type, also
NOR type is can be set to, is arranged according to actual demand.
Three-dimensional storage provided by the present invention can manufacture to obtain according to flow chart as shown in Figure 5.Art technology
Personnel should be known that it is as shown in Figure 5 be only be made to an embodiment of three-dimensional storage provided by the present invention, and
Not to the restriction of the manufacturing method of three-dimensional storage provided by the present invention.As shown in figure 5, manufacturing method may include following
Step：
Step 510：Compound substrate is provided, deposits the first semiconductor layer on the metallic substrate to form compound substrate.
Step 520：Replace depositing layers and interlayer insulating film in compound substrate to form stack layer.
Specifically, the material of grid layer is tungsten, and interlayer insulating film is silica.
Step 530：Etch stack layer, to be formed perpendicular to the raceway groove hole of compound substrate；
Step 540：Channel layer is formed in raceway groove hole；
Specifically, in this step, it still further comprises：
The epitaxial semiconductor layer in the compound substrate exposed via raceway groove hole.
Barrier layer is deposited in the stack layer side surface exposed by raceway groove hole；
In barrier layer surface deposited charge trapping layer；
Tunnel layer is deposited in charge-trapping layer surface；And
In tunnelling layer surface depositing trench layer, and can select to fill megohmite insulant in raceway groove hole.
Step 550：Drain region is formed above memory block.
Specifically, in channel layer and megohmite insulant disposed thereon drain region.
Step 560：Etch stack layer, to form grid line separate slot, the first the half of grid line separate slot at least exposed composite substrate leads
Body layer.
Step 570：Ion was once injected to form doped region to the first semiconductor.
Specifically, in this step, doped region is heavily doped region, by taking the first semiconductor layer is p-type as an example, is led to the first half
The N-type ion concentration of body layer injection is 10^19-10^21/cm3。
And step 580：Fill grid line separate slot.
It is still further comprised more specifically, manufacturing memory as shown in Figure 1：In step 560, grid line separate slot is further
The metal substrate of ground exposed composite substrate；
In step 580, the filler being filled in grid line separate slot is metal layer, is physically contacted with metal substrate；Specifically,
Further include：Before filling metal layer, on the side wall of the stack layer exposed via grid line separate slot, depositing insulating layer.And
The doped region injected in step 570 is physically contacted with metal layer, so that metal layer passes through with the first semiconductor layer
Doped region is electrically connected.
It is still further comprised more specifically, manufacturing memory as shown in Figure 2：In step 510, the composite lining provided
Bottom further includes isolation layer, and step 510 further comprises：Isolation layer is deposited on the metallic substrate, the deposition the first half on isolation layer
Conductor layer is to form compound substrate.
It is still further comprised more specifically, manufacturing memory as shown in Figure 3：In step 560, the exposure of grid line separate slot is multiple
Close the first semiconductor layer of substrate；
In step 580, the filler being filled in grid line separate slot is insulant；And
The doped region injected in step 570 is diffused to be physically contacted with metal substrate, to form Ohmic contact.
It is still further comprised more specifically, manufacturing memory as shown in Figure 4：In step 510, the composite lining provided
Bottom further includes the second polysilicon layer, and step 510 further comprises：The second polysilicon layer is deposited on the metallic substrate, more than second
The first semiconductor layer is deposited on crystal silicon layer to form compound substrate；And
Step 570 further comprises：It is adulterated to the first semiconductor layer and the injection of the second polysilicon layer via grid line separate slot
Ion makes injected doped region be physically contacted with metal substrate, to form Ohmic contact.
As shown in Figure 6 to 8, the present embodiment also provides a kind of to three-dimensional storage as described above progress data manipulation side
The step of the step of method, data manipulation method includes the steps that digital independent, data erasing and data are write.
It is specific as shown in fig. 6, the step of digital independent, includes the following steps：
Step 610, trigger data reading program.
Step 620 makes the drain region of memory access bias voltage；Public source is set to be grounded；Make not selected storage
The grid layer of unit accesses conducting voltage, and conducting voltage is enough that channel layer is made to be connected；Make the grid layer of selected storage unit
Voltage is read in access.
Voltage between the drain region and common source region of the storage unit that step 630, sensing are selected, and/or, electric current
Variation is to judge the data mode of storage unit.
The three-dimensional storage that data manipulation method provided by the present invention is controlled is by positioned at channel layer and grid layer
Between electric charge capture layer capture charge, to store data.The amount of charge of electric charge capture layer capture determines that storage is single
The Vt of member.Therefore, the read operation of data is detection storage unit stored charge amount, that is, the mistake of storage unit Vt
Journey.
To memory carry out data read operation when, drain region access bias voltage, public source ground connection so that into
It, can be by sensing (the electric current change caused by potential change of the curent change between drain region and public source when row read operation
Change, also can sensing voltage variation) judge data mode that memory is stored.The range of bias voltage can be in 0.3-0.5V
Between.Under these conditions, if channel layer is connected, the Vt of conducting electric current and storage unit is inversely proportional, for memory,
Channel layer conducting is because being applied with the voltage more than storage unit Vt in grid.In the case where channel layer is connected, electric current from
Drain region flows to common source region.
For the storage unit not being selected, in read operation, grid layer accesses conducting voltage, so that channel layer
Conducting, electric current can flow to public source from drain region.Conducting voltage, which is one, can ensure to be more than any one storage unit
The voltage of Vt, but conducting voltage cannot be too big, otherwise can make memory that tunneling effect occur.The range of conducting voltage can be in 3-
Between 8V.
For selected storage unit, in read operation, voltage is read in grid layer access, is deposited if reading voltage and being more than
The Vt of storage unit can then be such that channel layer is connected.By attempting to apply grid layer different reading voltage, so that it may be deposited with knowing
Storage unit stored charge amount is also known that its data stored.
Memory data read operation method provided by the present invention is widely used, and is including but not limited to applied to be set
For SLC (Single-Level Cell, single layer cell, a storage unit store (bit) data), MLC (Multi-
Level Cell, a storage unit store two bits), TLC (Triple-Level Cell, a storage unit storage three
Position data) or QLC (Quad-Level Cell, a storage unit storage four figures evidence) scene.
Specifically as shown in fig. 7, data include the following steps the step of erasing：
Step 710, trigger data wipe program.
Step 720 keeps drain electrode floating；Make grounded-grid；The first semiconductor layer is set to access erasing voltage.
The three-dimensional storage that data manipulation method provided by the present invention is controlled is by positioned at channel layer and grid layer
Between electric charge capture layer capture charge, to store data.Thus, the erasing operation of data is will be on electric charge capture layer
The process of charge release.
When carrying out data erasing operation to memory, drain region is floating (floating), and grid layer ground connection, the first half lead
Body layer accesses erasing voltage.Since the first semiconductor layer is in high potential, the electronics captured in electric charge capture layer can be attracted, and
Erasing voltage is enough to make memory that tunneling effect occur, so that electronics success is attracted by source electrode, and then releases electric charge capture layer
On electronics.The range of erasing voltage is between 14-20V.Under these conditions, electronics has been able to be attracted to the first half and leads
Body layer, therefore for the metal substrate in public source, floating state is may be at, it can also be with the first semiconductor layer one
Sample is in by the state of access erasing voltage.Preferably, it can select metal substrate being in the floating state being easier to control.
Data method for deleting provided by the present invention can realize the whole erasing (Body Erase) of memory, storage
The ultrahigh in efficiency of device erasing operation.In the above-described embodiments, electronics is at least attracted to the first semiconductor layer, therefore electric current is from
Semi-conductor layer flows to grid layer.
Specifically as shown in figure 8, the step of data are write includes the following steps：
Step 810, trigger data write program.
Step 820 makes grounded drain；Public source is set to be grounded；Grid is set to access program voltage.
The three-dimensional storage that data manipulation method provided by the present invention is controlled is by positioned at channel layer and grid layer
Between electric charge capture layer capture charge, to store data.Thus, the compilation operation of data is to make electronics by charge-trapping
The process of layer capture.
When carrying out data compilation operation to memory, drain region ground connection, public source ground connection, grid layer access programming electricity
Pressure.Since grid layer is in high potential, electronics can be attracted close, and program voltage is enough to make memory that tunneling effect occur,
So that electronics is captured during close to grid layer by electric charge capture layer.The range of program voltage between 12-27V, and
Different program voltages determines the electron amount in write-in electric charge capture layer, can be realized thereby using different program voltages
The distinct data states of Memory Storage Unit.In the above-described embodiments, electronics is attracted to grid layer, therefore electric current is from grid
Laminar flow is to drain region.
According to the operating method of three-dimensional storage provided by the present invention, memory can be realized by simple step
Reading, erasing and compilation operation, efficiency are higher.
Although to simplify explanation to illustrate the above method and being described as a series of actions, it should be understood that and understand,
The order that these methods are not acted is limited, because according to one or more embodiments, some actions can occur in different order
And/or with from it is depicted and described herein or herein it is not shown and describe but it will be appreciated by those skilled in the art that other
Action concomitantly occurs.
Offer is that can make or use this public affairs to make any person skilled in the art all to the previous description of the disclosure
It opens.The various modifications of the disclosure all will be apparent for a person skilled in the art, and as defined herein general
Suitable principle can be applied to spirit or scope of other variants without departing from the disclosure.The disclosure is not intended to be limited as a result,
Due to example described herein and design, but should be awarded and principle disclosed herein and novel features phase one
The widest scope of cause.
Claims (25)
1. a kind of three-dimensional storage, which is characterized in that including：
Compound substrate, the compound substrate include metal substrate and the first semiconductor layer being formed in the metal substrate,
First semiconductor layer is the first doping type；
Stack layer is formed in the compound substrate, and the stack layer includes along perpendicular to the direction interval of the compound substrate
If the dried layer grid layer being arranged；
Across the raceway groove hole of the stack layer；
Channel layer in the raceway groove hole；
The doped region of the second doping type in first semiconductor layer, the doped region are formed with the metal substrate
Ohmic contact, so that the public source of the memory includes at least first semiconductor layer, the metal substrate.
2. three-dimensional storage as described in claim 1, which is characterized in that further include：At least across the grid line of the stack layer
Separate slot；Filler in the grid line separate slot；
The doped region is located at the lower section of the grid line separate slot.
3. three-dimensional storage as claimed in claim 2, which is characterized in that the filler includes metal layer and is located at described
Insulating layer between metal layer and grid layer, the insulating layer cover the side wall of the grid line separate slot, and the metal layer is described in
Direction is extended to be connect with the metal substrate, and the public source also includes the metal layer.
4. three-dimensional storage as claimed in claim 3, which is characterized in that further include：Positioned at the metal substrate and described the
Isolation layer between semi-conductor layer, the metal layer are connect across the isolation layer with the metal substrate along the direction.
5. three-dimensional storage as claimed in claim 3, which is characterized in that the material of the metal layer includes W.
6. three-dimensional storage as claimed in claim 2, which is characterized in that the filler is insulant.
7. three-dimensional storage as claimed in claim 6, which is characterized in that further include：Positioned at the metal substrate and the first half
Second semiconductor layer of the second doping type between conductor layer；
The doped region diffuses to along the direction and forms the Ohmic contact with the metal substrate.
8. three-dimensional storage as claimed in claim 7, which is characterized in that the material of second semiconductor layer includes polycrystalline
Silicon.
9. three-dimensional storage as described in claim 1, which is characterized in that the doped region is heavily doped region.
10. three-dimensional storage as described in claim 1, which is characterized in that first doping type be p-type, described second
Doping type is N-type.
11. three-dimensional storage as described in claim 1, which is characterized in that the material of first semiconductor layer includes polycrystalline
Silicon.
12. three-dimensional storage as described in claim 1, which is characterized in that the material of the metal substrate includes WSi.
13. three-dimensional storage as described in claim 1, which is characterized in that further include：In the grid layer and the channel layer
Between set gradually barrier layer, electric charge capture layer, tunnel layer.
14. three-dimensional storage as described in claim 1, which is characterized in that the memory is configured to：To the memory into
When row data read operation, electric current flows to the public source from the drain region of the memory, and further, electric current is from institute
It states the first semiconductor layer and at least at least flows to the metal substrate via the doped region.
15. three-dimensional storage as claimed in claim 14, which is characterized in that the memory is configured to：To the memory
When carrying out data read operation, bias voltage, the public source ground connection are accessed in the drain region；
The grid layer of not selected storage unit accesses conducting voltage, and the conducting voltage is enough that the channel layer is made to lead
It is logical；
Voltage is read in the grid layer access of selected storage unit.
16. three-dimensional storage as described in claim 1, which is characterized in that the memory is configured to：To the memory into
When row data erasing operation, electric current flows to the grid layer from first semiconductor layer.
17. three-dimensional storage as claimed in claim 16, which is characterized in that the memory is configured to：To the memory
When carrying out data erasing operation, the drain region of the memory is floating, the grid layer ground connection, the first semiconductor layer access
Erasing voltage, the erasing voltage are enough to make the memory that tunneling effect occur.
18. such as claim 1 to 17 any one of them three-dimensional storage, which is characterized in that the memory is that 3D NAND are deposited
Reservoir.
19. a kind of data manipulation method of such as claim 1 to 18 any one of them three-dimensional storage, which is characterized in that institute
The operating method that data manipulation method includes digital independent is stated, the operating method of the digital independent includes making the memory
Bias voltage is accessed in drain region；
The public source is set to be grounded；
The grid layer of not selected storage unit is set to access conducting voltage, the conducting voltage is enough to make the channel layer
Conducting；
So that the grid layer of selected storage unit is accessed and reads voltage；
Voltage between the drain region and the common source region of the selected storage unit of sensing, and/or, curent change
To judge the data mode of the storage unit.
20. data manipulation method as claimed in claim 19, which is characterized in that the ranging from 0.3- of the bias voltage
0.5V；
The ranging from 3-8V of the conducting voltage.
21. data manipulation method as claimed in claim 19, which is characterized in that the data manipulation method further includes that data are wiped
The operating method removed, the operating method that the data are wiped include：
Keep the drain region floating；
The grid layer is set to be grounded；
The first semiconductor layer access erasing voltage, the erasing voltage is set to be enough to make the memory that tunneling effect occur,
So that the electronics stored in memory is attracted to first semiconductor layer.
22. data manipulation method as claimed in claim 21, which is characterized in that the operating method of the data erasing is further
Including：
Keep the metal substrate floating, or, accessing the erasing voltage.
23. data manipulation method as claimed in claim 21, which is characterized in that the ranging from 14-20V of the erasing voltage.
24. data manipulation method as claimed in claim 19, which is characterized in that the data manipulation method further includes that data are compiled
The operating method of journey, the operating method that the data program include：
The drain region is set to be grounded；
The public source is set to be grounded；
Make the grid layer access program voltage, the program voltage is enough to make the memory that tunneling effect occur, so as to deposit
Electronics is stored in reservoir.
25. data manipulation method as claimed in claim 24, which is characterized in that the ranging from 12-27V of the program voltage.
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