CN110571223B - Three-dimensional memory and forming method and control method thereof - Google Patents
Three-dimensional memory and forming method and control method thereof Download PDFInfo
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- CN110571223B CN110571223B CN201910904899.2A CN201910904899A CN110571223B CN 110571223 B CN110571223 B CN 110571223B CN 201910904899 A CN201910904899 A CN 201910904899A CN 110571223 B CN110571223 B CN 110571223B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a forming method and a control method thereof. The three-dimensional memory includes: the memory device comprises a substrate, a plurality of memory strings and a plurality of control circuits, wherein the substrate is provided with a stacking structure, a plurality of channel holes penetrating through the stacking structure and the memory strings filled in each channel hole; a plurality of first plugs, which are filled in part of the channel holes one by one and are connected with the top of the memory string in the channel hole, wherein the first plugs are provided with first doped ions; and the second plugs are filled in the residual channel holes in the stacked structure one by one and are connected with the tops of the storage strings in the channel holes, the second plugs are provided with second doped ions, and the conductivity types of the first doped ions are opposite to that of the second doped ions. The invention increases the storage density of the storage unit under the condition of low manufacturing cost and improves the storage performance of the three-dimensional memory.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a forming method and a control method thereof.
Background
As technology develops, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In non-volatile memories, such as NAND memories, one way to increase memory density is through the use of vertical memory arrays, i.e., 3D NAND (three-dimensional NAND) memories; with higher and higher integration, 3D NAND memories have evolved from 32 layers to 64 layers, and even higher.
As market demands for memory density continue to increase, programming methods with more programming states are being developed so that each physical memory cell (cell) can represent more bits (bit) of information. However, the implementation of more programmed states has higher requirements on the formation process of a single memory cell and the distribution uniformity among multiple memory cells.
Therefore, how to increase the storage density of the memory cells and improve the performance of the three-dimensional memory is a technical problem to be solved.
Disclosure of Invention
The invention provides a three-dimensional memory, a forming method and a control method thereof, which are used for solving the problem of low storage density of a storage unit in the prior art so as to improve the storage performance of the three-dimensional memory.
In order to solve the above problems, the present invention provides a three-dimensional memory including:
the memory device comprises a substrate, a plurality of memory strings and a plurality of control circuits, wherein the substrate is provided with a stacking structure, a plurality of channel holes penetrating through the stacking structure and the memory strings filled in each channel hole;
a plurality of first plugs, which are filled in part of the channel holes one by one and are connected with the top of the memory string in the channel hole, wherein the first plugs are provided with first doped ions;
and the second plugs are filled in the residual channel holes in the stacked structure one by one and are connected with the tops of the storage strings in the channel holes, the second plugs are provided with second doped ions, and the conductivity types of the first doped ions are opposite to that of the second doped ions.
Optionally, the number of the first plugs and the second plugs is equal.
Optionally, the method further includes:
a first bit line, one end of the first plug is connected with the top of a memory string, and the other end of the first plug is connected with the first bit line;
and one end of the second plug is connected with the top of a storage string, the other end of the second plug is connected with the second bit line, and the first bit line is parallel to the second bit line.
Optionally, in a direction perpendicular to the first bit line, the first plugs and the second plugs are alternately arranged, and the first plugs and the second plugs are staggered from each other.
Optionally, the stacked structure has a first region and a second region independent of each other, the first region has a plurality of the first plugs therein, and the second region has a plurality of the second plugs therein.
In order to solve the above problems, the present invention further provides a method for forming a three-dimensional memory, including the steps of:
providing a substrate, wherein the substrate is provided with a stacked structure, a plurality of channel holes penetrating through the stacked structure and a storage string filled in each channel hole;
and forming a plurality of first plugs and a plurality of second plugs, wherein the first plugs are filled in part of the channel holes one by one and are connected with the tops of the storage strings in the channel holes, the second plugs are filled in the rest of the channel holes in the stacked structure one by one and are connected with the tops of the storage strings in the channel holes, the first plugs are provided with first doped ions, the second plugs are provided with second doped ions, and the conductivity types of the first doped ions are opposite to that of the second doped ions.
Optionally, the specific steps of forming the first plug and the second plug include:
depositing a plug material on the top of all the storage strings to form a plurality of initial plugs corresponding to the storage strings one by one;
implanting first doping ions into a part of the initial plug to form a first plug;
and implanting second doping ions into the residual initial plug to form a second plug.
Optionally, the number of the first plugs is equal to the number of the second plugs.
Optionally, the method further comprises the following steps:
and forming a first bit line and a second bit line which are parallel to each other, wherein one end of the first plug is connected with the top of a storage string, the other end of the first plug is connected with the first bit line, one end of the second plug is connected with the top of the storage string, and the other end of the second plug is connected with the second bit line.
Optionally, in a direction perpendicular to the first bit line, the first plugs and the second plugs are alternately arranged, and the first plugs and the second plugs are staggered from each other.
Optionally, the stacked structure has a first region and a second region independent of each other, the first region has a plurality of the first plugs therein, and the second region has a plurality of the second plugs therein.
In order to solve the above problem, the present invention further provides a method for controlling a three-dimensional memory according to any one of the above embodiments, including:
when reading, applying a starting voltage to all storage layers of the three-dimensional memory so that a channel layer in the storage string is the same as the conductivity type of the first plug and is opposite to the conductivity type of the second plug;
and simultaneously applying a first bit line voltage to the first plug and the second plug, and identifying the first plug and the second plug, wherein the first bit line voltage is a voltage for enabling the current in the channel hole corresponding to the first plug to be conducted and enabling the current in the channel hole corresponding to the second plug to be not conducted.
Optionally, after applying a turn-on voltage to all memory layers of the three-dimensional memory, forming a PN junction between the second plug and a channel layer of a memory string connected thereto;
the first bit line voltage is less than the turn-on voltage of the PN junction.
Optionally, an upper selection pipe connected with the plurality of channel holes one by one is further arranged above the stacked structure, and a lower selection pipe connected with the plurality of channel holes one by one is further arranged in the substrate; the specific steps of simultaneously applying a first bit line voltage to the first plug and the second plug include:
applying a first bit line voltage to the first and second plugs and simultaneously turning on all of the upper select tubes and all of the lower select tubes.
Optionally, after identifying the first plug and the second plug, the method further includes the following steps:
selecting a storage layer in the three-dimensional memory as a selection layer when reading operation is carried out;
applying a first bit line voltage to the first plug, applying a second bit line voltage to the second plug, and applying a read voltage to the selection layer to read stored information in the selection layer, the second bit line voltage being higher than an on voltage of the PN junction.
Optionally, after identifying the first plug and the second plug, the method further includes the following steps:
selecting a storage layer in the three-dimensional memory as a selection layer when a programming operation is carried out;
a program voltage is applied to the selection layer, and a bit line voltage is not applied to the first plug and the second plug, so that a program operation is performed on a memory string connected to the first plug while an inhibit operation is performed on a memory string connected to the second plug.
Optionally, after identifying the first plug and the second plug, the method further includes the following steps:
selecting a storage layer in the three-dimensional memory as a selection layer when a programming operation is carried out;
a programming voltage is applied to the selection layer and a third bit line voltage is simultaneously applied to the first plug and the second plug to perform a programming operation on a memory string connected to the second plug and simultaneously perform an inhibit operation on a memory string connected to the first plug.
Optionally, after identifying the first plug and the second plug, the method further includes the following steps:
when an erasing operation is performed, a floating voltage is applied to the first plug and the second plug at the same time, and information stored in the storage layer is erased.
According to the three-dimensional memory and the forming method and the control method thereof provided by the invention, two types of channel structures are formed in the three-dimensional memory, namely the first channel structure with the first plug and the second channel structure with the second plug, the conductivity type of the first plug in the first channel structure is opposite to that of the second plug in the second channel structure, and the first bits in the two channel structures in the reading operation are respectively marked according to the difference of the reading values in the reading operation, so that the storage information amount of the storage unit is increased by 1bit, namely the storage density of the storage unit is increased under the low manufacturing cost, and the storage performance of the three-dimensional memory is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a three-dimensional memory in accordance with an embodiment of the present invention;
FIG. 2 is a schematic diagram of a top view of a three-dimensional memory according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a three-dimensional memory according to an embodiment of the present invention;
FIG. 4 is a flow chart of a method for controlling a three-dimensional memory according to an embodiment of the present invention;
FIG. 5 is a control diagram illustrating a first bit read operation performed on a three-dimensional memory according to an embodiment of the present invention;
FIG. 6 is a control diagram illustrating another bit read operation performed on a three-dimensional memory according to an embodiment of the present invention;
FIG. 7 is a control diagram illustrating a programming operation for an N-type channel structure in a three-dimensional memory according to an embodiment of the present invention;
FIG. 8 is a control diagram illustrating a programming operation performed on a P-type channel structure in a three-dimensional memory according to an embodiment of the present invention;
FIG. 9 is a control diagram of the three-dimensional memory according to the embodiment of the invention during an erase operation.
Detailed Description
The following describes in detail a specific embodiment of a three-dimensional memory, a method for forming the same, and a control method according to the present invention with reference to the accompanying drawings.
In the three-dimensional memory, a bit line-channel plug-channel layer-epitaxial semiconductor layer (SEG) -substrate-Array Common Source layer (ACS) jointly form a carrier channel. When information reading operation is carried out on a storage unit in the three-dimensional memory, if the current in the path is conducted, the reading value is 1; if the current in the path is not conducting, the read value is "0".
Most of the current three-dimensional memories use a TLC (Triple-Level Cell) programming mode, each physical memory Cell can only store 3-bit information quantity, and the storage density is low, so that the development of the storage performance of the three-dimensional memory is limited.
In order to increase the storage density of a single memory cell in a three-dimensional memory and improve the storage performance of the three-dimensional memory, the present embodiment provides a three-dimensional memory, fig. 1 is a schematic cross-sectional view of the three-dimensional memory according to the embodiment of the present invention, and fig. 2 is a schematic top-view structural view of the three-dimensional memory according to the embodiment of the present invention. The three-dimensional memory described in this embodiment may be, but is not limited to, a 3DNAND memory. As shown in fig. 1 and fig. 2, the three-dimensional memory provided by the present embodiment includes:
the memory device comprises a substrate 10, wherein the substrate 10 is provided with a stacked structure 13, a plurality of channel holes penetrating through the stacked structure 13 and a memory string filled in each channel hole;
a plurality of first plugs 111, each of which is filled in a part of the trench hole and connected to the top of the memory string in the trench hole, wherein the first plugs 111 have first doped ions;
and a plurality of second plugs 121, one by one, filled in the remaining channel holes in the stacked structure 13 and connected to the top of the memory string in the channel hole, wherein the second plugs 121 have second doping ions, and the conductivity types of the first doping ions are opposite to the conductivity types of the second doping ions.
Specifically, as shown in fig. 1, the memory string includes a blocking layer 112 located in the channel hole, a charge trapping layer 113 covering a surface of the blocking layer 112, a tunneling layer 114 covering a surface of the charge trapping layer 113, a channel layer 115 covering a surface of the tunneling layer 114, and an insulating layer 116 covering a surface of the channel layer 115. The top of the memory string is electrically connected to the first plug 111 or the second plug 121, and the bottom is electrically connected to the epitaxial semiconductor layer 117.
The stack structure 13 includes gate layers and interlayer insulating layers alternately stacked in a direction perpendicular to the substrate 10 (i.e., a Z-axis direction in fig. 1), and the channel hole penetrates the stack structure 13 in the direction perpendicular to the substrate 10. The structures and materials of all the memory strings and the epitaxial semiconductor layers in the three-dimensional memory can be set to be the same. All the channel holes in the three-dimensional memory can be divided into two parts, wherein the tops of a part of the channel holes are filled with first plugs 111 electrically connected with the memory strings in the channel holes, and the tops of another part of the channel holes (i.e. all the channel holes except the first plugs 111) are filled with second plugs 121 electrically connected with the memory strings in the channel holes.
The first dopant ions may be N-type ions and the second dopant ions may correspondingly be P-type ions; or, the first doped ions are P-type ions, and the second doped ions are correspondingly N-type ions. The present embodiment forms two channel structures in the stacked structure by doping to make the conductivity type of the first plug 111 opposite to the conductivity type of the second plug 121, namely: a first channel structure 11 including a memory string and the first plug 111 in a channel hole; and a second channel structure 12 including a memory string located in another channel hole and the second plug 121. Subsequently, when a data information reading operation is performed, different bit line voltages can be controlled to be applied to the first channel structure 11 and the second channel structure 12, so that data information read from the first channel structure 11 (for example, a read value of the first channel structure is "1") is different from data information read from the second channel structure 12 (for example, a read value of the second channel structure is "0"), and the data information can be used as identification marks of the first channel structure 11 and the second channel structure 12. That is to say, in the embodiment, by ion doping, information of a channel structure identification bit is added to each memory cell, that is, in a TLC programming mode, the information storage amount of each memory cell is increased from 3 bits to 4 bits, so that the storage density of the memory cell is increased, and the storage performance of the three-dimensional memory is improved. In addition, the purpose of increasing the storage density can be achieved by only carrying out a simple ion implantation process, so that the manufacturing cost of the three-dimensional memory is reduced.
The relative number relationship between the first plug 111 and the second plug 121 can be set by those skilled in the art according to actual needs, for example, the number of the first plugs 111 is greater than, less than or equal to the number of the second plugs 121, and it is only necessary to ensure that the sum of the numbers of the first plugs 111 and the second plugs 121 is equal to the number of the channel holes in the stacked structure. In order to further simplify the manufacturing process and the data manipulation method of the three-dimensional memory, the number of the first plugs 111 and the second plugs 121 is optionally equal.
Optionally, as shown in fig. 2, the three-dimensional memory further includes:
a first bit line 20, one end of the first plug 111 is connected to the top of a memory string, and the other end is connected to the first bit line 20;
a second bit line 22, one end of the second plug 121 is connected to the top of a memory string, the other end is connected to the second bit line 22, and the first bit line 20 is parallel to the second bit line 22.
For example, as shown in FIG. 2, the first bit line 20 and the second bit line 22 both extend along the Y-axis direction. The first plug 111 is electrically connected to the first bit line 20 through a first contact plug 21, and the second plug 121 is electrically connected to the second bit line 22 through a second contact plug 23. The first contact plug 21 and the second contact plug 23 both extend in the Z-axis direction in fig. 1, and may be made of tungsten.
Optionally, the first plugs 111 and the second plugs 121 are alternately arranged in a direction perpendicular to the first bit line 20, and the first plugs 111 and the second plugs 121 are staggered.
Specifically, as shown in fig. 2, the first plugs 111 and the second plugs 121 are alternately arranged along the X-axis direction, and the adjacent first plugs 111 and second plugs 121 are staggered from each other, so as to avoid signal crosstalk when performing subsequent data information operations.
In other specific embodiments, the stacked structure has a first region and a second region independent of each other, the first region has a plurality of the first plugs therein, and the second region has a plurality of the second plugs therein. The number of the first areas can be 1 or more; the number of the second regions may also be 1 or more. The position arrangement relationship between the first region and the second region can be set by those skilled in the art according to actual needs, but it is preferable that no crosstalk occurs between the signal applied to the first plug and the signal applied to the second plug.
Furthermore, the present embodiment further provides a method for forming a three-dimensional memory, and fig. 3 is a flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention. The structure of the three-dimensional memory manufactured by the present embodiment can be seen in fig. 1 and 2. As shown in fig. 1 to fig. 3, the method for forming a three-dimensional memory according to the present embodiment includes the following steps:
step S31, providing a substrate 10, in which the substrate 10 has a stacked structure 13, a plurality of channel holes penetrating through the stacked structure 13, and a memory string filled in each of the channel holes;
step S32, forming a plurality of first plugs 111 and a plurality of second plugs 121, where the plurality of first plugs 111 are filled in a part of the trench holes one by one and connected to the top of the memory strings in the trench holes, and the plurality of second plugs 121 are filled in the remaining trench holes in the stacked structure 13 one by one and connected to the top of the memory strings in the trench holes, the first plugs 111 have first doping ions, the second plugs 121 have second doping ions, and the first doping ions and the second doping ions have opposite conductivity types.
Specifically, the substrate 10 may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or the like. The first dopant ions may be N-type ions and the second dopant ions may correspondingly be P-type ions; or, the first doped ions are P-type ions, and the second doped ions are correspondingly N-type ions.
Optionally, the specific steps of forming the first plug 111 and the second plug 121 include:
depositing a plug material on the top of all the storage strings to form a plurality of initial plugs corresponding to the storage strings one by one;
implanting first doping ions into a part of the initial plug to form a first plug 111;
second doping ions are implanted into the remaining initial plug to form a second plug 121.
Specifically, the plug material may be, but is not limited to, a polysilicon material, and a specific method of implanting the first dopant ion or the second dopant ion into the initial plug may be, but is not limited to, an IMP (Ionized metal plasma) process. Implanting a part of the initial plug with first doping ions to form the first plug 111; the remaining amount of the initial plug is implanted with second dopant ions to form the second plug 121.
Optionally, the number of the first plugs 111 is equal to the number of the second plugs 121.
Optionally, the method for forming the three-dimensional memory further includes the following steps:
a first bit line 20 and a second bit line 22 are formed in parallel, one end of the first plug 111 is connected to the top of a memory string, and the other end is connected to the first bit line 20, and one end of the second plug 121 is connected to the top of a memory string, and the other end is connected to the second bit line 22.
Optionally, the first plugs 111 and the second plugs 121 are alternately arranged in a direction perpendicular to the first bit line 20, and the first plugs 111 and the second plugs 121 are staggered.
In other specific embodiments, the stacked structure has a first region and a second region independent of each other, the first region has a plurality of the first plugs therein, and the second region has a plurality of the second plugs therein.
Furthermore, the present invention provides a method for controlling a three-dimensional memory according to any of the above embodiments, and fig. 4 is a flowchart of a method for controlling a three-dimensional memory according to an embodiment of the present invention, and the structure of the three-dimensional memory according to the embodiment may be referred to fig. 1 and fig. 2. As shown in fig. 1, fig. 2 and fig. 4, the method for controlling a three-dimensional memory according to this embodiment includes the following steps:
step S41, in a read operation, applying a turn-on voltage to all memory layers of the three-dimensional memory such that a channel layer in the memory string is of the same conductivity type as the first plug 111 and is opposite to the conductivity type of the second plug 112;
step S42, applying a first bit line voltage to the first plug 111 and the second plug 121 simultaneously, and identifying the first plug 111 and the second plug 121, where the first bit line voltage is a voltage that makes a current in a channel hole corresponding to the first plug 111 conductive and makes a current in a channel hole corresponding to the second plug 121 nonconductive.
Optionally, after applying a turn-on voltage to all memory layers of the three-dimensional memory, a PN junction is formed between the second plug 121 and a channel layer of a memory string connected thereto;
the first bit line voltage is less than the turn-on voltage of the PN junction.
Optionally, an upper selection pipe connected with the plurality of channel holes one by one is further arranged above the stacked structure, and a lower selection pipe connected with the plurality of channel holes one by one is further arranged in the substrate; the specific steps of simultaneously applying the first bit line voltage to the first plug 111 and the second plug 121 include:
a first bit line voltage is applied to the first plug 111 and the second plug 121, and all the upper selection tubes and all the lower selection tubes are simultaneously turned on.
In the following description, the first doped ions are N-type ions, the second doped ions are P-type ions, and the substrate 10 is a P-type substrate, and accordingly, the first channel structure 11 in fig. 1 is an N-type channel structure, and the second channel structure 12 is a P-type channel structure. FIG. 5 is a control diagram illustrating a first bit read operation performed on a three-dimensional memory according to an embodiment of the present invention. In a read operation, an upper select transistor and a lower select transistor electrically connected to the N-type channel structure and the P-type channel structure are both turned on, and then a first bit line voltage Vo _ L is applied from the first bit line 20 to the upper select transistor connected to the N-type channel structure, a first bit line voltage Vo _ L is also applied from the second bit line 22 to the upper select transistor connected to the P-type channel structure, and simultaneously a turn-on voltage VPASS is applied to all memory layers in the three-dimensional memory, so that a channel layer in the memory string in the stacked structure is inverted to an N-type, thereby forming a PN junction in the P-type channel structure. By controlling the first bit line voltage Vo _ L to be lower than the turn-on voltage of the PN junction (e.g., the first bit line voltage Vo _ L is 0.3V), the current in the P-type channel structure is not conducted, and the read value of the P-type channel structure is "0". Since no PN junction is formed in the N-type channel structure, the current in the N-type channel structure is conducted, and the read value is 1.
In the embodiment, before a conventional programming mode (such as TLC), a PN junction is formed in a part of channel holes of a memory, and then a read value of each channel structure is different by applying a bit line voltage lower than a turn-on voltage of the PN junction, so that a P-type channel structure and an N-type channel structure are identified, that is, 1bit of information is added to a single memory cell for identifying the type of the channel structure, thereby increasing the storage density of the memory cell.
Optionally, the method for controlling the three-dimensional memory further includes the following steps:
selecting a storage layer in the three-dimensional memory as a selection layer when reading operation is carried out;
the stored information in the selection layer is read by applying a first bit line voltage to the first plug 111, applying a second bit line voltage to the second plug 121, and applying a read voltage to the selection layer, the second bit line voltage being higher than the turn-on voltage of the PN junction.
FIG. 6 is a control diagram for performing other bit read operations on a three-dimensional memory according to an embodiment of the present invention. For example, as shown in fig. 6, after the N-type channel structure and the P-type channel structure are identified through steps S41 and S42, the information stored in a memory cell of the three-dimensional memory can be read by programming such as TLC. When reading, the upper selection tube and the lower selection tube connected with the N-type channel structure and the P-type channel structure are both started, a reading voltage Vread is applied to the selection layer, a first bit line voltage Vo _ L is still applied to the N-type channel structure through the first bit line 20, current in the N-type channel structure is conducted, current in the P-type channel structure is conducted through the second bit line 22, a second bit line voltage Vo _ H, P-type channel structure higher than the first bit line voltage Vo _ L is applied to the P-type channel structure, and information in the selection layer is read. The second bit line voltage Vo _ H is preferably set to a value such that the potential in the P-type channel structure is equal to or similar to the potential in the N-type channel structure, for example, Vo _ L is 0.3V, Vo _ H is 0.7V to 1V, to further improve the performance of information reading.
Optionally, after identifying the first plug 111 and the second plug 121, the method further includes the following steps:
selecting a storage layer in the three-dimensional memory as a selection layer when a programming operation is carried out;
a program voltage is applied to the selection layer and a bit line voltage is not applied to the first plug 111 and the second plug 121 to perform a program operation on a memory string connected to the first plug 111 and simultaneously perform an inhibit operation on a memory string connected to the second plug 121.
Optionally, after identifying the first plug 111 and the second plug 121, the method further includes the following steps:
selecting a storage layer in the three-dimensional memory as a selection layer when a programming operation is carried out;
a program voltage is applied to the selection layer and a third bit line voltage is simultaneously applied to the first plug 111 and the second plug to perform a program operation on a memory string connected to the second plug 121 and simultaneously perform an inhibit operation on a memory string connected to the first plug 111.
Fig. 7 is a control diagram illustrating a program operation of an N-type channel structure in a three-dimensional memory according to an embodiment of the present invention, and fig. 8 is a control diagram illustrating a program operation of a P-type channel structure in a three-dimensional memory according to an embodiment of the present invention. For example, as shown in fig. 7 and 8, when a memory string in the N-type channel structure is selected as a program string to program the selection layer, a program voltage is applied to the selection layer, a bit line voltage is not applied to the program string (i.e., the bit line voltage is 0V), a third bit line voltage V _ L is applied to the N-type channel structures other than the selected N-type channel structure, and a bit line voltage is not applied to all the P-type channel structures (i.e., the bit line voltage is 0V), that is, an Inhibit (Inhibit) operation is performed on all the memory strings other than the program string (i.e., as an Inhibit string). When a memory string in the P-type channel structure is selected as a programming string to program the selection layer, a programming voltage is applied to the selection layer, a third bit line voltage V _ L is applied to the programming string, and the bit line voltage V _ L is not applied to other P-type channel structures except the selected P-type channel structure (i.e., the bit line voltage is 0V), and the third bit line voltage V _ L is applied to all N-type channel structures, i.e., Inhibit (Inhibit) operations are performed on the other memory strings except the selected P-type channel structure (i.e., as Inhibit strings).
Optionally, after identifying the first plug 111 and the second plug 121, the method further includes the following steps:
when an erasing operation is performed, a floating voltage is simultaneously applied to the first plug 111 and the second plug 121, and information stored in the memory layer is erased.
FIG. 9 is a control diagram of the three-dimensional memory according to the embodiment of the invention during an erase operation. For example, as shown in fig. 9, the first bit line 20 and the second bit line 22 respectively apply a floating voltage Vfloating to the N-type channel structure and the P-type channel structure, the gate voltages of all the upper selection transistors are gradually increased from 0V to the floating voltage Vfloating, a substrate voltage V _ H is applied to the substrate, and meanwhile, no turn-on voltage is applied to all the storage layers (i.e., the gate voltages of all the storage layers are 0V), so that the information stored in the memory cell is erased.
In the three-dimensional memory, the two types of channel structures are formed in the three-dimensional memory, the conductivity type of the first plug in the first channel structure is opposite to the conductivity type of the second plug in the second channel structure, and the first bits in the two channel structures during the reading operation are respectively marked according to the difference of the reading values during the reading operation, so that the amount of the stored information of the storage unit is increased by 1bit, that is, the storage density of the storage unit is increased at low manufacturing cost, and the storage performance of the three-dimensional memory is improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (18)
1. A three-dimensional memory, comprising:
the memory device comprises a substrate, a plurality of memory strings and a plurality of control circuits, wherein the substrate is provided with a stacking structure, a plurality of channel holes penetrating through the stacking structure and the memory strings filled in each channel hole;
a plurality of first plugs, which are filled in part of the channel holes one by one and are connected with the top of the memory string in the channel hole, wherein the first plugs are provided with first doped ions;
a plurality of second plugs, one by one, filled in the remaining trench holes in the stacked structure and connected to the top of the memory string in the trench hole, wherein the second plugs have second doped ions, and the conductivity types of the first doped ions are opposite to the conductivity types of the second doped ions;
wherein the three-dimensional memory includes only the first plug or the three-dimensional memory includes only the second plug in an extending direction along the same bit line.
2. The three-dimensional memory according to claim 1, wherein the first plugs and the second plugs are equal in number.
3. The three-dimensional memory according to claim 1, further comprising:
a first bit line, one end of the first plug is connected with the top of a memory string, and the other end of the first plug is connected with the first bit line;
and one end of the second plug is connected with the top of a storage string, the other end of the second plug is connected with the second bit line, and the first bit line is parallel to the second bit line.
4. The three-dimensional memory according to claim 3, wherein the first plugs and the second plugs are alternately arranged in a direction perpendicular to the first bit line, and the first plugs and the second plugs are staggered from each other.
5. The three-dimensional memory according to claim 1, wherein the stacked structure has a first region and a second region independent of each other, the first region has a plurality of the first plugs therein, and the second region has a plurality of the second plugs therein.
6. A method for forming a three-dimensional memory is characterized by comprising the following steps:
providing a substrate, wherein the substrate is provided with a stacked structure, a plurality of channel holes penetrating through the stacked structure and a storage string filled in each channel hole;
forming a plurality of first plugs and a plurality of second plugs, wherein the plurality of first plugs are filled in part of the channel holes one by one and are connected with the tops of the storage strings in the channel holes, the plurality of second plugs are filled in the rest of the channel holes in the stacked structure one by one and are connected with the tops of the storage strings in the channel holes, the first plugs are provided with first doped ions, the second plugs are provided with second doped ions, and the conductivity types of the first doped ions are opposite to that of the second doped ions;
wherein the three-dimensional memory includes only the first plug or the three-dimensional memory includes only the second plug in an extending direction along the same bit line.
7. The method of claim 6, wherein the step of forming the first plug and the second plug comprises:
depositing a plug material on the top of all the storage strings to form a plurality of initial plugs corresponding to the storage strings one by one;
implanting first doping ions into a part of the initial plug to form a first plug;
and implanting second doping ions into the residual initial plug to form a second plug.
8. The method of claim 6, wherein the number of the first plugs is equal to the number of the second plugs.
9. The method of forming a three-dimensional memory according to claim 6, further comprising the steps of:
and forming a first bit line and a second bit line which are parallel to each other, wherein one end of the first plug is connected with the top of a storage string, the other end of the first plug is connected with the first bit line, one end of the second plug is connected with the top of the storage string, and the other end of the second plug is connected with the second bit line.
10. The method of claim 9, wherein the first plugs and the second plugs are alternately arranged in a direction perpendicular to the first bit lines, and the first plugs and the second plugs are staggered from each other.
11. The method of claim 6, wherein the stacked structure has a first region and a second region independent of each other, the first region has a plurality of the first plugs therein, and the second region has a plurality of the second plugs therein.
12. A method for controlling a three-dimensional memory according to any one of claims 1 to 5, comprising the steps of:
when reading, applying a starting voltage to all storage layers of the three-dimensional memory so that a channel layer in the storage string is the same as the conductivity type of the first plug and is opposite to the conductivity type of the second plug;
and simultaneously applying a first bit line voltage to the first plug and the second plug, and identifying the first plug and the second plug, wherein the first bit line voltage is a voltage for enabling the current in the channel hole corresponding to the first plug to be conducted and enabling the current in the channel hole corresponding to the second plug to be not conducted.
13. The method of claim 12, wherein after applying a turn-on voltage to all memory layers of the three-dimensional memory, a PN junction is formed between the second plug and a channel layer of a memory string connected thereto;
the first bit line voltage is less than the turn-on voltage of the PN junction.
14. The method of claim 13, wherein the stacked structure further has an upper selection pipe connected to the plurality of trench holes one by one, and the substrate further has a lower selection pipe connected to the plurality of trench holes one by one; the specific steps of simultaneously applying a first bit line voltage to the first plug and the second plug include:
applying a first bit line voltage to the first and second plugs and simultaneously turning on all of the upper select tubes and all of the lower select tubes.
15. The method for controlling the three-dimensional memory according to claim 13, further comprising the steps of, after identifying the first plug and the second plug:
selecting a storage layer in the three-dimensional memory as a selection layer when reading operation is carried out;
applying a first bit line voltage to the first plug, applying a second bit line voltage to the second plug, and applying a read voltage to the selection layer to read stored information in the selection layer, the second bit line voltage being higher than an on voltage of the PN junction.
16. The method for controlling the three-dimensional memory according to claim 12, further comprising, after identifying the first plug and the second plug, the steps of:
selecting a storage layer in the three-dimensional memory as a selection layer when a programming operation is carried out;
a program voltage is applied to the selection layer, and a bit line voltage is not applied to the first plug and the second plug, so that a program operation is performed on a memory string connected to the first plug while an inhibit operation is performed on a memory string connected to the second plug.
17. The method for controlling the three-dimensional memory according to claim 12, further comprising, after identifying the first plug and the second plug, the steps of:
selecting a storage layer in the three-dimensional memory as a selection layer when a programming operation is carried out;
a programming voltage is applied to the selection layer and a third bit line voltage is simultaneously applied to the first plug and the second plug to perform a programming operation on a memory string connected to the second plug and simultaneously perform an inhibit operation on a memory string connected to the first plug.
18. The method for controlling the three-dimensional memory according to claim 12, further comprising, after identifying the first plug and the second plug, the steps of:
when an erasing operation is performed, a floating voltage is applied to the first plug and the second plug at the same time, and information stored in the storage layer is erased.
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