TW201721921A - Three dimensional memory device - Google Patents

Abstract

A 3D memory device includes a multi-layer stacks structure having a plurality of conductive strips and a first, a second, a third and a fourth ridge stack; a first SSL switch, a first GSL switch, a second SSL switch and a second GSL switch respectively disposed on the first, the second the third and the fourth ridge stack; a first U-shaped memory cells string connecting the first SSL switch with the first GSL switch; a second U-shaped memory cells string connecting the second SSL switch with the second GSL switch; a first word lines contact in contact with the conductive strips disposed in the first ridge stack; a second word lines contact in contact with the conductive strips disposed in the second ridge stack; and a third word lines contact in contact with the conductive strips disposed in the third ridge stack and the fourth ridge stack.

Description

Three-dimensional memory component

This invention relates to a high density memory component. In particular, a three-dimensional (Three Dimemsional, 3D) memory component.

Non-volatile memory components, such as flash memory, have the property of not losing information stored in the memory unit when the power source is removed. It has been widely used in solid-state mass storage applications for portable music players, mobile phones, digital cameras, and the like. In order to meet the demand for higher density storage capacity, there are various three-dimensional memory components of different structures, such as single-gate memory cells, double gate memory cells, and wraparound gates. A three-dimensional flash memory component of a surrounding cell is proposed.

A typical three-dimensional non-volatile memory component includes a plurality of memory cell stereoscopic arrays having vertical channels constructed in multi-layer stacks. Taking a Single-Gate Vertical Channel (SGVC) NAND memory device having a U-shaped memory cell string structure as an example, a stacked conductive strip of polycrystalline germanium material is generally used as a gate of a memory cell. Since the resistance of the polysilicon is large, when constructing the memory cell array, the conductive strips need to be separated into a plurality of segments, and the stepped word line contacts the structural word line contact structure, which will be located in the same layer. The conductive strips are electrically connected to the metal word lines located above the memory cell array.

Since the word line contact structure occupies a relatively large area of the memory element, the wiring space for accommodating the metal word line above the memory cell array is limited. With the expansion of the memory capacity of the memory element, the number of conductive stripe layers in the multi-layer stacked layer structure is relatively increased, and more word line and word line contact structures need to be set. At present, it can only be adapted by reducing the line diameter and pitch of the word line, or increasing the area size of the memory block.

However, reducing the line diameter and spacing of the word lines can result in reduced process window, reduced yield, and significantly increased process cost, even due to oxide breakdown. Increasing the area size of the memory block does not match the current trend of component shrinkage.

Therefore, there is a need to provide an advanced memory component to solve the problems faced by the above-mentioned techniques.

An embodiment of the present specification provides a three-dimensional memory element. The three-dimensional memory component comprises: a multi-layer stacks, a first String Select Line (SSL) switch, a first Ground Selection Line (GSL) switch, and a second serial a select line switch, a second ground select line switch, a first U-shaped memory cell string, a second U-shaped memory cell string, a first word line contact structure, a second word line contact structure, and a third word line Contact structure. The multilayer stack structure includes a plurality of conductive strips isolated from each other and a plurality of trenches for defining at least a first ridge stack, a second ridge stack, a third ridge stack, and a fourth Ridge stacking. The first tandem select line switch is located above the first ridge stack. The first ground select line switch is located above the second ridge stack. The first U-shaped memory cell string is serially connected to the first string select line switch and the first ground select line switch. The second series of select line switches are located above the third ridge stack. A second ground select line switch is located above the fourth ridge stack. The second U-shaped memory cell is serially connected in series with the second serial selection line switch and the second ground selection line switch. The first word line contact structure is in contact with the conductive strips on the first ridge stack. The second word line contact structure is in contact with the conductive strips on the second ridge stack; the third word line contact structure is in contact with the conductive strips on the third ridge stack and the fourth ridge stack.

According to the above embodiment, the present specification provides a three-dimensional memory element having a plurality of ridge stacks, wherein each ridge stack includes, respectively, a tandem select line switch or a ground select line switch at the top and The serial selection line switch or a plurality of memory cells below the ground selection line switch. Forming the first string select line switch and the first ground select line switch located on the two ridge stacks, and the memory cells located under the first tandem select line switch and the first ground select line switch a U-shaped memory cell string; at the same time by serially connecting the second string selection line switch and the second ground selection line switch on the other two different ridge stacks, and the second series selection line switch and the second The memory cell below the ground selection line switch forms a second U-shaped memory cell string.

The memory cell located below the first string select line switch of the first U-shaped memory cell string is connected to the first word line contact structure; the second string select line switch located in the second U-shaped memory cell string The lower memory cell is connected to the second word line contact structure; and the memory cell located below the first ground select line switch of the first U-shaped memory cell string and the second ground selection located in the second U-shaped memory cell string The memory cells below the line switches are connected to the same third word line contact structure. In other words, in the three-dimensional memory element, the number of word line contact structures used to connect the memory cells under the ground selection switch is smaller than the word line contact structure used to connect the memory cells located below the serial selection switch. If the memory capacity is not changed, the setting of the word line contact structure can be reduced as compared with the three-dimensional memory element of the prior art.

By reducing the setting of the word line contact structure, the area size of the memory element can be reduced; the memory capacity of the memory element can be expanded without affecting the process margin, the process cost can be greatly reduced, and the oxide layer can be prevented from being struck. The wear phenomenon occurs, increasing the process yield of the vertical channel memory components.

The invention provides a memory component, which can solve the problem of insufficient processing margin of the conventional memory component, and at the same time save manufacturing cost and improve process yield. The above and other objects, features and advantages of the present invention will become more <RTIgt;

However, it must be noted that these specific embodiments are not intended to limit the invention. The invention may be practiced with other features, elements, methods and parameters. The preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the invention. Equivalent modifications and variations will be made without departing from the spirit and scope of the invention. In the different embodiments and the drawings, the same elements will be denoted by the same reference numerals.

Referring to FIGS. 1A to 1C, FIGS. 1A to 1C are perspective views showing a process structure for fabricating a single-gate vertical channel NAND memory device 100 according to an embodiment of the present invention. A method of fabricating a single gate vertical channel NAND memory device 100 includes the steps of first forming a multilayer stack structure 104 (as depicted in FIG. 1A) on a surface of a substrate 101. In the present embodiment, the multilayer stack structure 104 includes a plurality of conductive layers 102 and a plurality of insulating layers 103 staggered on each other on the substrate 101 along the Z-axis direction depicted in FIG. 1A.

In some embodiments of the present invention, the material of the conductive layer 102 may include n-type polycrystalline germanium (or n-type epitaxial single crystal germanium) doped with phosphorus or arsenic, and p-type polycrystalline germanium doped with boron (or p-type germanium). Crystal single crystal germanium), undoped polycrystalline germanium, metal silicides such as titanium telluride (TiSi), cobalt telluride (CoSi) or germanium (SiGe), oxide semiconductors, such as indium oxide Zinc (InZnO) or indium gallium zinc oxide (InGaZnO), metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), titanium nitride ( TiN), tantalum nitride (TaN) or tantalum aluminum nitride (TaAlN), or a combination of two or more of the above materials. The insulating layer 103 may be composed of a dielectric material such as an oxide, a nitride, an oxynitride, a silicate or the like.

Next, a patterning process is performed on the multilayer stack structure 104 to form a plurality of ridge stacks 104A, 104B, 104C, and 104D. In some embodiments of the invention, the multilayer stack structure 104 is etched using an anisotropic etching process, such as a reactive ion etch (RIE) process. The multilayer stack structure 104 is divided into a plurality of ridge stacks 104A, 104B, 104C, and 104D by forming trenches 105 extending laterally along X and extending longitudinally along the Z axis among the multilayer stack structure 104, and the substrate 101 is formed. A portion of the area is exposed through the trench 105 (as depicted in FIG. 1B).

Each of the ridge stacks 104A, 104B, 104C, and 104D includes a plurality of strips of conductive strips. For example, in the present embodiment, the ridge stack 104A has the conductive strips 104A1, 104A2, 104A3, 104A4, 104A5, and 104A6 stacked upward along the Z-axis direction; the ridge stack 104B has the conductive strips stacked upward along the Z-axis direction. Strips 104B1, 104B2, 104B3, 104B4, 104B5, and 104B6; ridge stack 104C having conductive strips 104C1, 104C2, 104B3, 104C4, 104C5, and 104C6 stacked upward along the Z-axis direction; and ridge stack 104D having along Z Conductive strips 104D1, 104D2, 104D3, 104D4, 104D5, and 104D6 stacked in the axial direction. Wherein, the conductive strips 104A6, 104B6, 104C6, and 104D6 located at the top plane of the ridge stacks 104A, 104B, 104C, and 104D have conductive strips 104A1- than other planes located in the same ridge stacks 104A, 104B, 104C, and 104D. 104A5, 104B1-104B5, 104C1-104C5 and 104D1-104D5 are also of large thickness.

Thereafter, a memory material layer 106 having a charge trapping structure is formed over the sidewalls of the ridge stacks 104A, 104B, 104C, and 104D and at the bottom of the trench 105. A patterned semiconductor channel layer 107 is formed over the memory material layer 106. Further, at the cross point where the conductive strips 104A1-A6, 104B1-B6, 104C1-C6, and 104D1-D6 of the ridge stacks 104A, 104B, 104C, and 104D overlap with the memory material layer 106 and the channel layer 107, A plurality of memory cells 108 are respectively defined (as shown in FIG. 1C).

In some embodiments of the present invention, the charge trapping structure of the memory material layer 106 may be a composite multi-layer selected from the group consisting of oxide-nitride-oxide (ONO). Structure, an oxide-nitride-oxide-nitride-oxide (ONONO) structure, a 矽-矽 oxide-tantalum nitride-矽 structure Silicon-oxide-nitride-oxide-silicon (SONOS) structure, a gap-engineered silicon-oxide-nitride-oxide-silicon (bandgap engineered silicon-oxide-nitride-oxide-silicon) , BE-SONOS) structure, tantalum nitride (aluminum oxide, silicon nitride, silicon oxide, silicon, tantalum) structure and a high dielectric constant energy of a metal A group of metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon (MA BE-SONOS) structures. The semiconductor channel layer 107 may be composed of an n-type polysilicon doped with phosphorus or arsenic, or an n-type epitaxial single crystal germanium. Further, the semiconductor channel layer 107 may be composed of a p-type polycrystalline germanium doped with boron or a p-type epitaxial single crystal germanium.

In the present embodiment, the patterned semiconductor channel layer 107 is composed of n-type polysilicon, and the patterned semiconductor channel layer 107 includes at least two portions separated from each other. A portion of the semiconductor channel layer 107 covers the bottom of the adjacent ridge stacks 104A and 104B and the trenches 105 used to isolate the ridge stacks 104A and 104B. A U-shaped channel film is formed between the ridge stacks 104A and 104B, respectively, for serially connecting a plurality of memory cells 108 formed on the ridge stacks 104A and 104B to form a first U-shaped memory cell train 109A. Another portion of the semiconductor channel layer 107 covers the bottom of the adjacent ridge stacks 104C and 104C and the trenches 105 used to isolate the ridge stacks 104C and 104D. And another U-shaped channel film is formed between the ridge stacks 104C and 104D for serially connecting a plurality of memory cells 108 formed on the ridge stacks 104C and 104D to form a second U-shaped memory cell string 109B.

Wherein, the memory cell located at the top of the ridge stack 104A can serve as the first ground select line switch 110A of the first U-shaped memory cell string 109A; the memory cell located at the top of the ridge stack 104B can serve as the first U-shaped The first string selection switch 111A of the memory cell string 109A. The memory cell located at the top of the ridge stack 104C can serve as the second ground select line switch 110B of the second U-shaped memory cell string 109B; the memory cell located at the top of the ridge stack 104D can serve as the second U-shaped memory cell. The second string selection switch 111B of the series 109B.

It is also worth noting that although FIG. 1C only shows two U-shaped memory cell strings formed by four ridge stacks (ridge stacks 104A, 104B, 104C, and 104D) (the first U-shaped memory cell string) 109A and second U-shaped memory cell string 109B). However, it is merely for the purpose of clarity of description and is not intended to limit the invention. In some embodiments of the invention, the single-gate vertical channel NAND memory element 100 can include more ridge stacks and more U-shaped memory cell strings to form a three-dimensional memory cell array.

Thereafter, the dielectric material layer 112 is filled in the trenches 105. In some embodiments of the present invention, the material forming the dielectric material layer 112 may include ceria, tantalum nitride, hafnium oxynitride, a high-k material, or any combination of the above. In this embodiment, it is preferred to also include forming an air gap 113 in the trench 105 for reducing interference between the memory cells 108 on the sidewalls of the different ridge stacks 104A, 104B, 104C and 104D.

Subsequent to FIG. 1D, a contact plug 114 is formed on top of the ridge stacks 104A, 104B, 104C, and 104D to respectively make the first tandem select line switch 111A and the second tandem select line switch 111B. Connected to a bit line 115; and a contact plug 116 is formed to connect the first ground select line switch 110A and the second ground select line switch 110B to a common source line 118 via metal wires 117, respectively. And forming a stepped plurality of word line contact structures (for example, 119B shown in FIG. 1D) in the peripheral region of the three-dimensional memory cell array, so as to be used in the same layer of the ridge stacks 104A, 104B, 104C, and 104D. Conductive strips 104A1-D1, 104A2-D2, 104A3-D3, 104A4-D4, 104A5-D5, and 104A6-D6 to form layer memory cells 108 are connected to different word lines 120, respectively.

For a detailed arrangement of word line contact structures, such as word line contact structures 119A, 119B, and 119C, refer to FIG. 2, which is a partial structure of a single gate vertical channel NAND memory device 100 according to FIG. 1D. Top view. The word line contact structures 119A, 119B, and 119C are disposed on both sides of the long axis of the ridge stacks 104A, 104B, 104C, and 104D, respectively. In the present embodiment, the word line contact structure 119A includes a plurality of contact layers stacked in a stepped manner for respectively contacting the conductive strips located at different levels in the ridge stack 104B; the word line contact structure 119B includes a stepped stack A plurality of contact layers are respectively used to contact the conductive strips at different levels in the ridge stack 104D. The word line contact structure 119C includes a plurality of contact layers stacked in a stepped manner for contacting the conductive strips of the same level in the ridge stacks 104A and 104C, respectively.

In other words, the conductive strips in the same planar layer of the ridge stacks 104A and 104C share a single word line contact structure 119C. In detail, the conductive strips 104A1 and 104C1 of the first planar layer of the ridge stacks 104A and 104C are in contact with the first contact layer (not shown) of the stepped word line contact structure 119C; The conductive strips 104A2 and 104C2 are in contact with the stepped word line contact structure 119C in a second contact layer (not shown); the conductive strips 104A3 and 104C3 in the third planar layer are in contact with the stepped word line. The third contact layer (not shown) of 119C is in contact; the conductive strips 104A4 and 104C4 located in the fourth planar layer are in contact with the fourth contact (not shown) layer of the stepped word line contact structure 119C; Conductive strips 104A5 and 104C5 of the planar layer are in contact with a fifth contact layer (not shown) of the stepped word line contact structure 119C; and conductive strips 104A6 and 104C6 in the sixth planar layer, and stepped characters The sixth contact layer (not shown) of the line contact structure 119C is in contact. Since the word line contact structure is well known, its detailed construction and fabrication method will not be described here.

However, the configuration of the word line contact structure is not limited thereto. In some embodiments of the present invention, the conductive strips under the tandem selection line switch in more than two different U-shaped memory cell strings , respectively, with different word line contact structures; the conductive strips under the ground select line switches located in more than two different U-shaped memory cell strings share a word line contact structure.

In some embodiments of the invention, the single gate vertical channel NAND memory device 100 further includes a plurality of series select line contact pads 121 and a common ground select line contact pad 122 for respectively selecting the string select line switches (for example, the first tandem select line switch 111A and the second tandem select line switch 111B) and the ground selection switch (eg, the first ground select line switch 110A and the second ground select line switch 110B) are connected to the decoder (not Painted). For example, in the present embodiment, each of the tandem select line contact pads 121 is located at one end of the ridge stacks 104B and 104D having the first tandem select line switch 111A and the second tandem select line switch 111B, adjacent to the word line. Contact structures 119A and 119B are in contact with conductive strips 104B6 and 104D6 used to form first tandem select line switch 111A and second tandem select line switch 111B. A common ground select line contact pad 122 is located at one end of the ridge stacks 104A and 104C having the first ground select line switch 110A and the second ground select line switch 110B, adjacent to the word line contact structure 119C, and used to form the The conductive strips 104A6 and 104C6 of a ground select line switch 110A and a second ground select line switch 110B are in contact.

The shape of the shared word line contact structure 119C may vary with the design of the single gate vertical channel NAND memory element. For example, please refer to FIG. 3, which is a partial top view of a single-gate vertical channel NAND memory device 300 according to another embodiment of the present invention. The single gate vertical channel NAND memory device 300 is substantially identical in structure to the single gate vertical channel NAND memory device 100 except that the shape of the word line contact structure 319C adjacent the ground select line contact pads 122 is different. In the present embodiment, the word line contact structure 319C shared by the conductive strips 104A6 and 104C6 located under the first ground select line switch 110A and the second ground select line switch 110B of the ridge stacks 104A and 104C may Configured as a vertical step structure. The lateral width of the single gate vertical channel NAND memory element 300 is further saved.

In order to prevent signal interference caused by different U-shaped memory cell series 109A and 109B having a common word line contact structure 119C in a write operation, a read operation, and an erase operation, in some embodiments of the present invention, a single gate The very vertical channel NAND memory element 100 can include a first control switch IG_1A between the first series select line switch 111A of the U-shaped memory cell string 109A and the first ground select line switch 110A, and a U-shaped The second control switch IG_1B between the second string selection line switch 111B of the memory cell string 109B and the second ground selection line switch 110B.

For example, please refer to FIG. 4, which is an equivalent circuit diagram when a single gate vertical channel NAND memory device 100 of FIG. 1C performs a write operation. In this embodiment, the first control switch IG_1A may include a complementary switch circuit 123 coupled to the bottom conductive strip 104B1 of the spine stack 104B for controlling the memory cells 108 located at the bottom of the spin stack 104B. Opening and closing. The second control switch IG_1B is coupled to the bottom conductive strip 104D1 located in the spine stack 104D for controlling the opening and closing of the memory cells 108 located at the bottom of the spin stack 104D. Since the structure of the second control switch IG_1B can be the same as that of the first control switch IG_1A, the structure of the second control switch IG_1B is not shown in FIG. However, in other embodiments, the structure of the second control switch IG_1B may still be different from the first control switch IG_1A.

In addition, in some preferred embodiments, the single-gate vertical channel NAND memory device 100 may further include a first auxiliary switch IG_0A between the first ground selection line switch 110A and the first control switch IG_1A, and a The second auxiliary switch IG_0B between the second ground selection line switch 110B and the second control switch IG_1B. Similarly, the structures of the first auxiliary switch IG_0A and the second auxiliary switch IG_0B may be the same as or different from the first control switch IG_1A.

In the present embodiment, the first auxiliary switch IG_0A is connected to the bottom conductive strip 104A1 of the spin-on stack 104A for controlling the opening and closing of the memory cell 108 located at the bottom of the spin-pack stack 104A; the second auxiliary switch IG_0B is connected to the ridge The conductive strips 104C1 at the bottom of the stack 104C are connected to control the opening and closing of the memory cells 108 at the bottom of the spin stack 104C.

When the first cell select switch 111A selects the memory cell 108P in the first U-shaped memory cell string 109A to perform a write operation, the first string select line switch 111A, the first control switch IG_1A, and the first auxiliary are turned on. Switch IG_0A; and turn off the first ground select line switch 110A. The first string selection line switch 111A and the first ground selection line switch 110A are simultaneously applied with a voltage of 0 volts (0 V) by the bit line 115 and the common source line 118; and the selected memory cell 108P is further selected by the word line 120. A gate write voltage Vpgm is applied; and a gate pass voltage Vpass is applied to the other memory cells 108 located on the first U-type memory cell string 109A. Wherein, the gate write voltage Vpgm is greater than the gate pass voltage Vpass, thereby inducing electrons to generate Fowler–Nordheim tunneling effect, and writing data into the memory cell 108P.

The second U-shaped memory cell string 109B, which is not selected, keeps the second series-selected line switch 111B located on the ridge stack 104D and the gate of the memory cell below it floating while the write operation is being performed (floating ). Since the conductive strips in the ridge stacks 104A and 104C share one word line contact structure 119C; and the first ground select line switch 110A and the second ground select line switch 110B also share the ground select line contact pads 122. Thus, the gate voltage applied to the second ground select line switch 110B on the ridge stack 104C and the memory cell 108 (including the memory cell 108P') below it, and the first ground selection applied to the ridge stack 104A The gate voltage of the line switch 110A and the memory cell 108 (including the memory cell 108P) therebelow is identical. Turning off the second control switch IG_1B causes local self-boosting of 104C in the second U-shaped memory cell string 109B to maintain a sufficient potential to prevent the memory cell 108P' located on the ridge stack 104C. It is written by the influence of the write voltage Vpgm.

Referring to FIG. 5, FIG. 5 is an equivalent circuit diagram when the single gate vertical channel NAND memory device 100 of FIG. 1C performs a read operation. In this embodiment, when the first cell select line switch 111A selects the memory cell 108R located on the first U-shaped memory cell string 109A to perform a read operation, the first string select line switch 111A is turned on. A ground selection line switch 110A, a first control switch IG_1A, and a first auxiliary switch IG_0A. The bit line 115 and the common source line 118 are simultaneously applied with 1 volt (1 V) and 0 volt (0 V) to the first string selection line switch 111A and the first ground selection line switch 110A, respectively, and further by word lines. 120 applies a gate read voltage Vref to the selected memory cell 108R; and applies a gate pass voltage Vpass to the other memory cells 108 located on the first U-shaped memory cell series 109A. The data can be read from the selected memory cell 108R.

When the second U-shaped memory cell string 109B that is not selected is in the read operation, the second string select line switch 111B located on the ridge stack 104D and the memory cell 108 gate below it remain floating. Since the conductive strips in the ridge stacks 104A and 104C share one word line contact structure 119C; and the first ground select line switch 110A and the second ground select line switch 110B also share the ground select line contact pads 122. Thus, the gate voltage applied to the second ground select line switch 110B on the ridge stack 104C and the memory cell 108 (including the memory cell 108R') below it, and the first ground selection applied to the ridge stack 104A The gate voltages of line switch 110A and memory cell 108 (including memory cell 108R) below it are identical. Turning off the second control switch IG_1B, and keeping the second string selection line switch 111B in the second U-shaped memory cell string 109B and the gate of the memory cell 108 below it floating, preventing the second unselected The memory cell 108R' in the U-shaped memory cell string 109B is read by the gate read voltage Vref.

Please refer to FIG. 6. FIG. 6 is an equivalent circuit diagram when the single gate vertical channel NAND memory device 100 of FIG. 1C is erased. In this embodiment, when the first U-shaped memory cell string 109A is selected for the erase operation, 7 is applied to the gates of the first string selection line switch 111A, the first control switch IG_1A, and the first auxiliary switch IG_0A. Volt voltage (7V), thereby turning it on; applying 0 volt (0 V) to the first ground select line switch 110A with the common source line 118, keeping the gate of the first ground select line switch 110A floating; The gate of all the memory cells 108 on the first U-shaped memory cell series 109A applies a voltage of 0 volts (0 V); and a 20 volt (20 V) erase is applied to the first string select line switch 111A by the bit line 115. Voltage. The memory cell 108 located on the first U-shaped memory cell string 109A generates a Gate-Induce Drain Leakage (GIDL) GIDL.

The second U-shaped memory cell string 109B, which is not selected, performs the erase operation, the second string selection line switch 111B on the ridge stack 104D and the memory cell 108 and the second control switch IG_1B and the The gates of the two ground selection switches 110B are kept floating. Since the conductive strips in the ridge stacks 104A and 104C share one word line contact structure 119C; and the first ground select line switch 110A and the second ground select line switch 110B also share the ground select line contact pads 122. Therefore, the gate voltage of the second ground select line switch 110B applied to the ridge stack 104C and the memory cell 108 thereunder will be the same as the first ground select line switch 110A applied to the ridge stack 104A and below it. The gate voltage of the memory cell 108 is exactly the same. The second string selection line switch 111B located on the ridge stack 104D and the memory cells 108 below it and the gates of the second control switch IG_1B are kept floating, which can delay the erasing time and prevent the second U-shaped memory cell The memory cell 108 in the string 109B is erased during the nanosecond erase time.

According to the above embodiment, the present specification provides a three-dimensional memory element having a plurality of ridge stacks, wherein each ridge stack includes, respectively, a tandem select line switch or a ground select line switch at the top and a string A plurality of memory cells below the column select line switch or the ground select line switch. Forming the first string select line switch and the first ground select line switch located on the two ridge stacks, and the memory cells located under the first tandem select line switch and the first ground select line switch a U-shaped memory cell string; at the same time by serially connecting the second string selection line switch and the second ground selection line switch on the other two different ridge stacks, and the second series selection line switch and the second The memory cell below the ground selection line switch forms a second U-shaped memory cell string.

The memory cell located below the first string select line switch of the first U-shaped memory cell string is connected to the first word line contact structure; the second string select line switch located in the second U-shaped memory cell string The lower memory cell is connected to the second word line contact structure; and the memory cell located below the first ground select line switch of the first U-shaped memory cell string and the second ground selection located in the second U-shaped memory cell string The memory cells below the line switches are connected to the same third word line contact structure. In other words, in the three-dimensional memory element, the number of word line contact structures used to connect the memory cells under the ground selection switch is smaller than the word line contact structure used to connect the memory cells located below the serial selection switch. If the memory capacity is not changed, the setting of the word line contact structure can be reduced as compared with the three-dimensional memory element of the prior art.

By reducing the setting of the word line contact structure, the area size of the memory element can be reduced; the memory capacity of the memory element can be expanded without affecting the process margin, the process cost can be greatly reduced, and the oxide layer can be prevented from being struck. The wear phenomenon occurs, increasing the process yield of the vertical channel memory components.

100, 300‧‧‧ memory components
101‧‧‧Substrate
102‧‧‧ Conductive layer
103‧‧‧Insulation
104‧‧‧Multilayer stacking structure
104A, 104B, 104C, 104D‧‧‧ ridge stacking
104A1-104A6, 104B1-104B6, 104C1-104C6, 104D1-104D6‧‧‧ Conductive strip
105‧‧‧ trench
106‧‧‧ memory material layer
107‧‧‧Semiconductor channel layer
108, 108P, 108R‧‧‧ memory cells
109A, 109B‧‧‧U-shaped memory cell series
110A, 110B‧‧‧ Grounding selection line switch
111A, 111B‧‧‧ tandem selector switch
112‧‧‧ dielectric material layer
113‧‧‧Air gap
114‧‧‧Contact plug
115‧‧‧ bit line
116‧‧‧Contact plug
117‧‧‧Metal wire
118‧‧‧Common source line
119A, 119B, 119C, 319C‧‧‧ character line contact structure
120‧‧‧ character line
121, 122‧‧‧ contact pads
IG_1A, IG_1B control switch
IG_0A, IG_0B‧‧‧ auxiliary switch
Vpgm‧‧‧ write voltage
Vpass‧‧‧ gate pass voltage
Vref‧‧‧ gate reading voltage
Floating‧‧‧ floating
GIDL‧‧‧ gate induced buckling leakage current

Other objects, features, and advantages of the present invention will be described in the following embodiments and claims, which are described in detail below with reference to the accompanying drawings: Figures 1A through 1D are a single brake according to the prior art. A perspective view of a partial structure of a very vertical channel NAND memory device; FIG. 2 is a partial top view of a single gate vertical channel NAND memory device according to FIG. 1D; FIG. 3 is another view of the present invention. A top view of a partial gate vertical channel NAND memory device shown in the embodiment; FIG. 4 is a diagram showing a single gate vertical channel NAND memory device for a program operation of FIG. Equivalent circuit diagram; Figure 5 is an equivalent circuit diagram when a single gate vertical channel NAND memory device of FIG. 1C is read operation; and FIG. 6 is a diagram 1C An equivalent circuit diagram for a single gate vertical channel NAND memory device for an erase operation.

100‧‧‧ memory components

101‧‧‧Substrate

102‧‧‧ Conductive layer

103‧‧‧Insulation

104‧‧‧Multilayer stacking structure

104A, 104B, 104C, 104D‧‧‧ ridge stacking

106‧‧‧ memory material layer

107‧‧‧Semiconductor channel layer

108‧‧‧ memory cells

109A, 109B‧‧‧U-shaped memory cell series

110A, 110B‧‧‧ Grounding selection line switch

111A, 111B‧‧‧ tandem selector switch

112‧‧‧ dielectric material layer

113‧‧‧Air gap

114, 116‧‧‧ contact plug

115‧‧‧ bit line

117‧‧‧Metal wire

118‧‧‧Common source line

119B‧‧‧ character line contact structure

120‧‧‧ character line

Claims (10)

A three-dimensional (3D) memory component, comprising: a multi-layer stacks comprising a plurality of conductive strips and a plurality of trenches isolated from each other for At least a first ridge stack, a second ridge stack, a third ridge stack, and a fourth ridge stack are defined; a first String Selection Line (SSL) switch Located on the first ridge stack; a first Ground Selection Line (GSL) switch located on the second ridge stack; a first U-shaped memory cell string (U-shaped cell String), serially connecting the first serial select line switch and the first ground select line switch; a second serial select line switch located on the third ridge stack; a second ground select line switch located a second U-shaped memory cell string, serially connecting the second string selection line switch and the second ground selection line switch; a first word line contact structure, and the The conductive strip contacts on the first ridge stack a second word line contact structure in contact with the plurality of conductive strips on the second ridge stack; and a third word line contact structure, and the third ridge stack and the fourth ridge The conductive strips on the stack are in contact. The three-dimensional memory component of claim 1, further comprising a first tandem select line contact pad in contact with a top conductive strip on the first spine stack; a second tandem select line Contact pads are in contact with a top conductive strip on the third spin stack; and a ground select line contact pad is in contact with the two top conductive strips on the second spin stack and the four spin stack. The three-dimensional memory component of claim 1, further comprising: a memory material layer on a plurality of sidewalls of the trenches; a patterned channel film covering the memory material layer and the trenches And a plurality of memory cells formed at a plurality of cross points of the memory material layer and the patterned channel film and the conductive strips. The three-dimensional memory device of claim 3, wherein: the first U-shaped memory cell string is connected to the first serial-selective line switch by a portion of the patterned channel film, located at the first a ridge stack and the memory cells on the second ridge stack and the first ground select line switch; and the second U-shaped memory cell string is connected in series by another portion of the patterned channel film A second string select line switch, the memory cells on the third ridge stack and the fourth ridge stack, and the second ground select line switch are formed. The three-dimensional memory component of claim 3, further comprising: a first control switch located between the first tandem select line switch and the first ground select line switch; and a second control switch Located between the second tandem select line switch and the second ground select line switch. The three-dimensional memory component of claim 5, wherein: the first control switch is coupled to a bottom conductive strip of the first spine stack; and the second control switch is stacked with the third spine A bottom conductive strip is connected. The three-dimensional memory component of claim 6, further comprising: a first auxiliary switch located between the first control switch and the first ground selection line switch; and a second auxiliary switch located at the Between the second control switch and the second ground selection line switch. The three-dimensional memory component of claim 7, wherein: the first auxiliary switch is in contact with a bottom conductive strip of the second spine stack; and the second auxiliary switch is stacked with the fourth spine A bottom conductive strip contacts. The three-dimensional memory component of claim 5, wherein when the first U-shaped memory cell string is selected for a program operation, the writing operation comprises: turning on the first serial port Selecting a line switch and the first control switch; turning off the first ground select line switch, the second ground select line switch, and the second control switch; and pairing the memory cells on the first U-shaped memory cell string One of them applies a write voltage (Vpgm); and applies a pass voltage (Vpass) to the other of the memory cells located on the first U-shaped memory cell string, wherein the write voltage is greater than the turn-on voltage. The three-dimensional memory component of claim 9, wherein a gate of the second tandem select line switch remains floating while the write operation is being performed.