JP2014236015A - Semiconductor device, and method of manufacturing the same - Google Patents

Semiconductor device, and method of manufacturing the same Download PDF

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JP2014236015A
JP2014236015A JP2013114546A JP2013114546A JP2014236015A JP 2014236015 A JP2014236015 A JP 2014236015A JP 2013114546 A JP2013114546 A JP 2013114546A JP 2013114546 A JP2013114546 A JP 2013114546A JP 2014236015 A JP2014236015 A JP 2014236015A
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region
trench
floating gate
forming
insulating film
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邦彦 岩本
Kunihiko Iwamoto
邦彦 岩本
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ローム株式会社
Rohm Co Ltd
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Abstract

A semiconductor device capable of realizing a small cell size with a simple process and a method of manufacturing the same are provided.
A semiconductor substrate, a trench that separates the semiconductor substrate into a plurality of active regions, and a protrusion that protrudes above the surface of the semiconductor substrate are embedded in the trench. A pair of regions formed in the active region 10 and spaced apart from each other along the longitudinal direction of the trench 6 in the buried insulating film 7 having a ratio of 2.3 to 3.67, The p + -type source region 13 and the p + -type drain region 14 that provide the n-type channel region 15 and the single layer straddling the p + -type source region 13 and the p + -type drain region 14 do not overlap the protrusion 9. Thus, the semiconductor device 1 including the floating gate 11 formed so as to protrude above the protruding portion 9 is manufactured.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device including a nonvolatile memory cell and a manufacturing method thereof.

  Patent Document 1 discloses a semiconductor substrate, a first tunnel oxide film formed in a predetermined region of the semiconductor substrate, a first floating gate formed above the first tunnel oxide film, an upper portion of the semiconductor substrate, A second tunnel oxide film formed along one sidewall of the floating gate; a second floating gate formed in contact with the second tunnel oxide film and isolated from the first floating gate; the first floating gate and the second floating gate; A dielectric film formed on the floating gate; a control gate formed on the dielectric film; a first junction region formed on a semiconductor substrate below one side of the second tunnel oxide film; A flash memory cell including a second junction region formed in a semiconductor substrate below one side of a tunnel oxide film is disclosed (FIG. 1 of Patent Document 1). ). The structure of the flash memory cell is a 2-bit cell structure (four-level state). The first floating gate and the second floating gate are separated by a second tunnel oxide film (high-temperature oxide film), and charge is applied to each floating gate. Store.

JP 2004-56134 A

  In the flash memory cell of Patent Document 1, a configuration in which the first floating gate and the second floating gate are separated by the second tunnel oxide film is essential. Therefore, in the manufacturing process disclosed in Patent Document 1, a polysilicon film used as the first floating gate, a second tunnel oxide film, and a silicon nitride film used as the second floating gate are sequentially deposited, and then these films are deposited. Is polished and formed by the CMP method.

  However, in order to polish three different material films by the CMP method as in Patent Document 1, it is necessary to use an apparatus having suitable polishing conditions for each material film to be polished. Therefore, transfer between polishing apparatuses is required, and polishing conditions must be set for each apparatus, which complicates the manufacturing process. Furthermore, there is a possibility that particles adhere to the wafer surface during the polishing of different films and the transfer of the wafer between polishing apparatuses.

In another aspect, in the flash memory cell of Patent Document 1, it is necessary to form two floating gates, the first and second floating gates, between the first junction region and the second junction region. There is also a problem that the cell size increases.
An object of the present invention is to provide a semiconductor device capable of realizing a small cell size by a simple process and a manufacturing method thereof.

  Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce threshold fluctuation due to the influence of coupling between floating gates.

  In order to achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor substrate having a well region of a first conductivity type formed on a surface portion thereof, and selectively formed in the well region, wherein the well region is divided into a plurality of well regions. A plurality of stripe-shaped trenches that are separated into active regions, a buried insulating film embedded in the trenches so as to have a protruding portion that protrudes above the surface of the semiconductor substrate, and a longitudinal direction of the trenches in the active region A pair of regions spaced apart from each other along a second conductive type source region and drain region providing a first conductive type channel region in a region therebetween, and the source region and It consists of a single layer straddling the drain region and protrudes above the protrusion so as not to overlap the protrusion of the buried insulating film. And a made floating gates, the aspect ratio of the buried insulating film is 2.3 to 3.67, which is a semiconductor device.

  This semiconductor device can be manufactured by the method according to claim 5. Accordingly, the invention according to claim 5 provides a plurality of stripe-shaped openings on a semiconductor substrate having a well region of the first conductivity type formed on the surface portion without interposing an electrode material between the semiconductor substrate and the semiconductor substrate. Forming an etching mask selectively, forming a trench separating the well region into a plurality of active regions by etching the semiconductor substrate through the opening of the etching mask, and the trench Filling the trench with a buried insulating film having a protrusion protruding from the surface of the semiconductor substrate by the thickness of the etching mask by supplying an insulating material so as to be buried back from the bottom of the substrate to the top surface of the etching mask. Exposing the active region surrounded by the protrusion by removing the etching mask; The electrode material is buried in the active region and the electrode material covering the remaining buried insulating film is deposited, and from the exposed state of the electrode material, the uppermost surface of the electrode material is the protrusion of the buried insulating film. Polishing the electrode material to the same height as the top surface, thereby forming a floating gate made of the electrode material in the active region, and selectively removing the protrusions of the buried insulating film Forming a recess between adjacent floating gates, and selectively removing the floating gates along the longitudinal direction of the trenches to thereby form a pair of first regions formed of a part of the semiconductor substrate. And the second region are spaced apart from each other and the well region between them is exposed to the first conductivity type chip. Forming a source region in the first region and forming a drain region in the second region by supplying a second conductivity type impurity to the first region and the second region. A method for manufacturing a semiconductor device including a process.

  According to this method, since the floating gate composed of a single layer is formed by polishing from the state in which the electrode material is exposed, it is not necessary to perform the polishing step for forming the floating gate a plurality of times. Therefore, transfer between polishing apparatuses is not necessary, and polishing conditions for forming the floating gate need only be set once, so that the manufacturing process can be simplified. Furthermore, since transfer between polishing apparatuses becomes unnecessary, adhesion of particles to the surface of the semiconductor substrate (wafer) can be reduced.

  In addition, since no electrode material is interposed between the etching mask and the semiconductor substrate when forming the trench for the buried insulating film, the aspect ratio of the trench including the opening of the etching mask (trench depth H / trench The width A) can be made smaller than when an electrode material is interposed. Further, since it is not necessary to overlap the floating gate with the protruding portion of the buried insulating film, it is not necessary to increase the trench width in anticipation of the width of the overlapping portion of the floating gate when designing the width of the trench. Therefore, the trench can be finely processed, and the burying property of the buried insulating film can be improved. As a result, a buried insulating film having an aspect ratio of 2.3 to 3.67 can be formed as in the first aspect of the invention. In addition, since no step is formed between the floating gate and the buried insulating film, it is possible to effectively prevent the generation of weak spots and voids when the buried insulating film is buried.

In addition, after removing the etching mask, the electrode material embedded in the position (active region) where the etching mask was located becomes a floating gate, so the height of the floating gate can be increased by adjusting the thickness of the etching mask. Can be adjusted easily.
In the semiconductor device according to claim 1 manufactured by the above method, the floating gate is formed of a single layer straddling the source region and the drain region, so that a small cell size can be realized.

In addition, since the floating gate does not overlap the protruding portion of the buried insulating film, the distance between the adjacent floating gates can be increased with the buried insulating film interposed therebetween. As a result, the parasitic capacitance between adjacent floating gates can be reduced, so that the threshold fluctuation due to the coupling effect between the floating gates can be reduced.
According to a second aspect of the present invention, the source region and the drain region are a p-type source region and a p-type drain region, respectively, and the well region and the channel region are an n-type well region and an n-type channel region, respectively. The semiconductor device according to claim 1, wherein

According to this configuration, writing / erasing of data with respect to the memory cell is performed using the p-type MOSFET.
Data writing to the memory cell composed of the p-type MOSFET is achieved by injecting electrons (hot electrons) generated by band-to-band tunneling in the vicinity of the p-type drain region into the floating gate. That is, the p-type source region is set to the ground potential (0 V). A voltage is applied to the p-type drain region, the control gate, and the n-type well region. As a result, hot electrons are generated in the vicinity of the p-type drain region, and the hot electrons are injected into the floating gate. On the other hand, when erasing data, a voltage is applied to the n-type well region and the control gate. By applying this voltage, an electric field is generated between the floating gate and the n-type well region, and electrons are extracted from the floating gate to the n-type well region by the FN tunnel phenomenon using the electric field. This series of write / erase operations can be performed with a smaller current than the write / erase operations of a memory cell made of an n-type MOSFET. Therefore, even with a simple structure in which the floating gate is formed of a single layer as in the present invention, good write / erase operations can be performed. That is, the present invention can be utilized more effectively by making the memory cell a p-type MOSFET.

Further, from the viewpoint of miniaturization of the cell size, as in the invention of claim 3, the first width W 1 of the floating gate along the width direction of the trench and the floating along the longitudinal direction of the trench. Both of the second widths W 2 of the gates are preferably 100 nm or less.
According to a fourth aspect of the present invention, the floating gate is preferably made of polysilicon.

According to a sixth aspect of the present invention, in the step of forming the etching mask, the aspect ratio of the space including the trench and the opening when forming the buried insulating film is 2.3 to 3.67. 6. The method of manufacturing a semiconductor device according to claim 5, wherein a thickness of the etching mask is set.
According to this method, since the aspect ratio of the space including the opening of the trench and the etching mask is 2.3 to 3.67, the buried insulating film can be satisfactorily buried.

According to a seventh aspect of the present invention, in the step of forming the recess, the removal amount of the protruding portion is set so that the aspect ratio of the buried insulating film is 2.3 to 3.67. It is preferable to do.
According to an eighth aspect of the present invention, the well region and the channel region are an n-type well region and an n-type channel region, respectively, and the step of forming the source region and the drain region is performed by supplying a p-type impurity. A method for manufacturing a semiconductor device according to claim 5, comprising a step of forming a p-type source region and a p-type drain region.

By this method, the semiconductor device according to claim 2 can be manufactured.
According to a ninth aspect of the present invention, the step of forming the trench includes a step of setting a pitch of the trench so that a first width W1 of the adjacent trench is 100 nm or less, and the floating gate Selectively removing the floating gate so that a second width W 2 along the longitudinal direction of the trench of the floating gate remaining between the first region and the second region is 100 nm or less. A method for manufacturing a semiconductor device according to claim 5, comprising a step of setting the pitch of the semiconductor device.

By this method, the semiconductor device according to claim 3 can be manufactured.
Further, as in the invention described in claim 10, the step of forming the floating gate preferably includes a step of polishing the electrode material by a CMP method.
Further, as in the invention described in claim 11, it is preferable that the step of forming the buried insulating film includes a step of supplying the insulating material by a high density plasma (HDP) CVD method.

  According to a twelfth aspect of the present invention, the etching mask is preferably made of a silicon nitride (SiN) film.

FIG. 1 is a layout diagram of a memory cell of a semiconductor device according to an embodiment of the present invention. 2A and 2B are bird's-eye views for explaining the internal structure of the memory cell. FIG. 2A shows a view seen from the direction along the bit line, and FIG. The figure seen from the direction along a line is shown. FIGS. 3A and 3B are views for explaining a part of the manufacturing method of the semiconductor device according to the embodiment of the present invention. 4 (a) and 4 (b) are diagrams showing the next step of FIGS. 3 (a) and 3 (b). 5 (a) and 5 (b) are diagrams showing the next step of FIGS. 4 (a) and 4 (b). 6 (a) and 6 (b) are diagrams showing the next process of FIGS. 5 (a) and 5 (b). 7 (a) and 7 (b) are diagrams showing the next step of FIGS. 6 (a) and 6 (b). 8 (a) and 8 (b) are diagrams showing the next step after FIGS. 7 (a) and 7 (b). FIGS. 9A and 9B are views showing the next step after FIGS. 8A and 8B. 10 (a) and 10 (b) are diagrams showing the next step of FIGS. 9 (a) and 9 (b). 11 (a) and 11 (b) are diagrams showing the next process of FIGS. 10 (a) and 10 (b). 12 (a) and 12 (b) are diagrams showing the next step of FIGS. 11 (a) and 11 (b). 13 (a) and 13 (b) are diagrams showing the next step after FIGS. 12 (a) and 12 (b).

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a layout diagram of a memory cell 2 of a semiconductor device 1 according to an embodiment of the present invention. In the semiconductor device 1, the striped bit lines BL that run in the vertical direction (Y direction) and the striped word lines WL that run in the horizontal direction (X direction) intersect in a lattice shape in plan view. A memory cell 2 is formed in the window portion of the lattice. By arranging the memory cells 2 in each window portion, the memory cells 2 are arranged in a matrix of X rows × Y columns (X and Y are positive integers) as a whole. The bit line BL is electrically connected to a p + -type drain region 14 described later, and the word line WL is electrically connected to a control gate 18 described later. By selecting the intersection between the bit line BL and the word line WL under the control of the bit line driving circuit 3 and the word line driving circuit 4, data can be written / erased in the memory cell 2 located at the intersection.

Next, the internal structure of the memory cell 2 will be described with reference to FIG. 2A and 2B are bird's-eye views for explaining the internal structure of the memory cell 2. FIG. 2A shows a view seen from the direction along the bit line BL, and FIG. Shows a view from the direction along the word line WL.
The semiconductor device 1 includes a semiconductor substrate 5. The semiconductor substrate 5 is made of, for example, a p-type silicon substrate, and the impurity concentration is, for example, 1 × 10 15 cm −3 to 5 × 10 15 cm −3 . An n-type well 12 is formed on the surface portion of the semiconductor substrate 5. The impurity concentration of the n-type well 12 is, for example, 1 × 10 17 cm −3 to 5 × 10 17 cm −3 .

The semiconductor substrate 5 is formed with a stripe-shaped trench 6 that separates the surface region of the semiconductor substrate 5 into a plurality of active regions 10 and a buried insulating film 7 embedded in the trench 6. Thus, an STI structure including the trench 6 and the buried insulating film 7 is formed in the semiconductor substrate 5.
The trenches 6 are formed in the region of the n-type well 12 from the surface of the semiconductor substrate 5, and are arranged in stripes so that linear line trenches are parallel to each other. As shown in FIG. 2A, the width A of the trench 6 and the width B between the adjacent trenches 6 are both 90 nm or less in this embodiment. That is, the semiconductor device 1 has a line and space of 90 nm or less. As shown in FIG. 2A, each trench 6 is formed in a taper shape in which the width A is narrowed in the depth direction from the opening end to the bottom when cut in the width direction orthogonal to the longitudinal direction. Has been. The depth H of each trench 6 is 0.13 μm to 0.16 μm in this embodiment, so that the aspect ratio of each trench 6 (depth H of trench 6 / width A of trench 6) is 1.30 to 1.77. The width A of the trench 6 is defined as the width at the opening end of the trench 6 in this embodiment.

The buried insulating film 7 is made of silicon oxide (SiO 2 ), and has a buried portion 8 accommodated in the trench 6 and a protruding portion 9 formed outside the trench 6 and protruding upward from the surface of the semiconductor substrate 5. Including one. The protrusion 9 is formed in a quadrangular shape that protrudes perpendicularly to the surface of the semiconductor substrate 5 in a cross-sectional view, and has a top surface (flat surface) parallel to the surface of the semiconductor substrate 5 and a vertical side surface. Have. Moreover, the protrusion amount of the protrusion part 9 is 0.09 micrometer-0.17 micrometer on the basis of the surface of the semiconductor substrate 5, for example. The aspect ratio (the total height of the buried portion 8 and the protruding portion 9 / the width A of the trench 6) of the buried insulating film 7 including the protruding portion 9 is 2.3 to 3.67.

Therefore, the active region 10 defined by the trench 6 is sandwiched between adjacent protrusions 9 and becomes a recess having a depth corresponding to the height difference between the top surface of the protrusion 9 and the surface of the semiconductor substrate 5. ing. A floating gate 11 is formed in each recess (active region 10). The floating gate 11 is embedded in the active region 10 formed of a recess so that the side surface thereof is in close contact with the side surface of the protruding portion 9 of the embedded insulating film 7, and further protrudes above the protruding portion 9. The protruding portion of the floating gate 11 is finished so that the entire side surface thereof is flush with the side surface of the protruding portion 9 so as not to overlap the protruding portion 9 of the buried insulating film 7. In this embodiment, the floating gate 11 is made of p-type polysilicon doped with a p-type impurity (for example, boron) at a high concentration. The impurity concentration of the floating gate 11 is, for example, 1 × 10 20 cm −3 to 5 × 10 20 cm −3 .

Further, as shown in FIG. 2B, a plurality of floating gates 11 are provided at intervals along the longitudinal direction of the trench 6 in each active region 10. A p + type source region 13 and a p + type drain region 14 are formed on the surface of the semiconductor substrate 5 (n-type well 12) exposed in each active region 10 in this way. Further, the surface portion of the n-type well 6 sandwiched between these provides the n-type channel region 15. That is, each memory cell 2 is composed of a p-type MOSFET.

The p + type source regions 13 and the p + type drain regions 14 are alternately provided along the longitudinal direction of the trench 6. Therefore, each floating gate 11 is a single layer straddling the p + type source region 13 and the p + type drain region 14. Here, “the floating gate 11 is a single layer” means that, for example, when the active region 10 is scanned along the longitudinal direction of the trench 6, between the pair of adjacent p + type source regions 13 and p + type drain regions 14. This means that a plurality of floating gates 11 are not provided, and of course, there is no boundary, an insulating separation film or the like disposed at the boundary. Further, the first width W 1 (FIG. 2A) of the portion along the width direction of the trench 6 of each floating gate 11, the p + type source region 13 and the p + type drain region along the longitudinal direction of the trench 6. The second width W 2 (FIG. 2B) of the portion extending over 14 is 90 nm or less. The first width W 1 matches the width B between the adjacent trenches 6. In this embodiment, the first width W 1 and the second width W 2 are both 90 nm or less as an example. However, in some cases, the first width W 1 and the second width W 2 are 100 nm or less. There may be.

  A tunnel oxide film 16 is formed on the surface of the semiconductor substrate 5 in the n-type channel region 15 so as to face the floating gate 11. The thickness of the tunnel oxide film 16 is about 80 mm, for example. The tunnel oxide film 16 allows electrons to pass between the n-type channel region 15 and the floating gate 11 by FN (Fowler-Nordheim) tunneling.

A control gate 18 is formed on the floating gate 11 so as to face the floating gate 11 with the ONO film 17 interposed therebetween.
The ONO film 17 is composed of an ONO laminated insulating film in which films made of silicon nitride (SiN) are sandwiched from above and below by films made of silicon oxide (SiO 2 ).
The control gate 18 is formed in a straight line extending across the trench 6. That is, the control gate 18 straddles a plurality of active regions 10 via the recesses 27 on the buried insulating film 7 formed between the adjacent floating gates 11. Thereby, the control gate 18 collectively covers all the floating gates 11 arranged on the same straight line along the direction crossing the trench 6. The control gate 18 is a common gate for a plurality of memory cells 2 arranged on the same straight line.

A word line WL and a nitride film 19 are stacked on the control gate 18. In this embodiment, the word line WL is made of tungsten silicide, and the nitride film 19 is made of silicon nitride (SiN). The thickness of the word line WL is about 0.07 μm, and the thickness of the nitride film 19 is about 0.15 μm. A sidewall 20 is formed so as to collectively cover the side surfaces of the floating gate 11, the ONO film 17, the control gate 18, the word line WL and the nitride film 19. The sidewall 20 has a laminated structure of, for example, silicon nitride (SiN) / silicon oxide (SiO 2 ).

A source wiring 21 is electrically connected to the p + type source region 13. The source wiring 21 is formed in a straight line extending across the trench 6. That is, the source wiring 21 is connected to all the p + type source regions 13 that are arranged on the same straight line extending across the plurality of active regions 10 and crossing the trench 6. Thereby, the source wiring 21 is a common source for the plurality of memory cells 2 arranged on the same straight line. As a material of the source wiring 21, for example, tungsten can be used. By using tungsten, the source wiring 21 can be formed with good processing accuracy even in the semiconductor device 1 having a line and space of 90 nm or less.

The bit line BL is electrically connected to the p + type drain region 14 through a bit contact 22 (bit plug). One bit contact 22 is connected to each p + -type drain region 14 separated from each other. As a material for the bit line BL and the bit contact 22, for example, tungsten can be used. By using tungsten, the bit line BL and the bit contact 22 can be formed with good processing accuracy even in the semiconductor device 1 having a line and space of 90 nm or less.

In the semiconductor device 1, data writing to the memory cell 2 is achieved by injecting electrons (hot electrons) generated by band-to-band tunneling in the vicinity of the p + type drain region 14 into the floating gate 11. That is, the source line 21 connected to the p + type source region 13 is set to the ground potential (0 V). Then, voltages (for example, Vg = −1.8V, Vd = 10V to 12V, V WELL = 4.4V) are applied to the bit line BL, the word line WL, and the n-type well 12. As a result, hot electrons are generated in the vicinity of the p + -type drain region 14, and the hot electrons are injected into the floating gate 11.

On the other hand, when erasing data, voltages (for example, Vg = −20 V, Vd = 0 V, V WELL = 0 V) are applied to the bit line BL, the word line WL, and the semiconductor substrate 5. By applying this voltage, an electric field is generated between the floating gate 11 and the n-type well 12, and electrons are extracted from the floating gate 11 to the n-type well 12 by the FN tunnel phenomenon using the electric field.

  This series of write / erase operations can be performed with a smaller current than the write / erase operations of a memory cell made of an n-type MOSFET. Therefore, even with a simple structure in which the floating gate 11 is composed of a single layer as in this embodiment, good write / erase operations can be performed. That is, the semiconductor device 1 can be used more effectively by making the memory cell 2 a p-type MOSFET.

3 to 13 are views for explaining a part of the manufacturing method of the semiconductor device 1 according to the embodiment of the present invention in the order of steps. 3 to 13, the bird's eye view of (a) corresponds to the bird's eye view of FIG. 2 (a), and the bird's eye view of (b) corresponds to the bird's eye view of FIG. 2 (b).
In order to manufacture the semiconductor device 1, a process of forming the trench 6 and the buried insulating film 7 from a state where a semiconductor substrate 5 is first prepared and no processing such as ion implantation is performed on the semiconductor substrate 5 is performed. Done. Specifically, as shown in FIGS. 3A and 3B, a pad oxide film 23 is formed on the surface of the semiconductor substrate 5 by, for example, a thermal oxidation method, and then on the pad oxide film 23 by, for example, a CVD method. Then, a hard mask 24 as an example of the etching mask of the present invention is formed. The thickness of the pad oxide film 23 is, for example, about 10 nm. The hard mask 24 is formed of a silicon nitride film having a thickness of about 175 nm, for example. At this time, the thickness of the hard mask 24 is set so that the aspect ratio of the space including the trench 6 and the opening 25 described later is 2.3 to 3.67.

  Next, as shown in FIGS. 4A and 4B, the hard mask 24 and the pad oxide film 23 are selectively etched in order to selectively form the opening 25 in the region where the trench 6 is to be formed. . Then, an etching gas is supplied to the semiconductor substrate 5 through the opening 25. Etching gas advances from the opening 25 in the depth direction of the semiconductor substrate 5, and a trench 6 having a tapered shape in cross section is formed in the semiconductor substrate 5.

  Next, as shown in FIGS. 5A and 5B, the trench 6 is backfilled by deposition of silicon oxide. The silicon oxide is deposited by, for example, a P-CVD (Plasma-Enhanced Chemical Vapor Deposition) method or an HDP-CVD (High-Density Plasma Chemical Vapor Deposition) method. The HDP-CVD method is preferable. The trench 25 and the opening 25 of the hard mask 24 are backfilled with silicon oxide, and the hard mask 24 is completely covered with silicon oxide. Thereafter, unnecessary portions of the silicon oxide (portions outside the trench 6 and the opening 25 of the hard mask 24) are removed by polishing by a CMP (Chemical Mechanical Polishing) method. This polishing is continued until the surface of the hard mask 24 and the surface of the buried oxide film (polishing surface) are flush with each other. Thereby, the buried insulating film 7 is buried so as to fill the opening 25 of the trench 6 and the hard mask 24. In the buried insulating film 7, a portion sandwiched between the pad oxide film 23 and the hard mask 24 becomes the protruding portion 9. In this step, in order to uniformly and uniformly bury silicon oxide in the trench 6, for example, thinning by RIE (Reactive Ion Etching) method, P-CVD method or HDP-CVD method is used. The silicon oxide may be deposited while alternately repeating the deposition by.

Next, as shown in FIGS. 6A and 6B, by removing the hard mask 24, the protruding portion 9 of the buried insulating film 7 is exposed in a protruding state. As a result, the active region 10 formed of a recess surrounded by the protrusion 9 is formed at the position where the hard mask 24 was present. Thereafter, n-type well ions are formed by implanting n-type impurity ions into the semiconductor substrate 5. Arsenic (As + ) ions or phosphorus (P + ) ions are used as n-type impurity ions.

Next, as shown in FIGS. 7A and 7B, after the pad oxide film 23 is removed, the exposed surface of the semiconductor substrate 5 is thermally oxidized, whereby the tunnel oxide film 16 is formed. . After the tunnel oxide film 16 is formed, a polysilicon film 26 to which p-type impurity ions (for example, boron (B + ) ions) are added is deposited by CVD. The polysilicon film 26 is formed so as to fill the active region 10 made of a recess and cover the buried insulating film 7.

  Next, as shown in FIGS. 8A and 8B, the polysilicon film 26 is exposed from the state in which the surface of the polysilicon film 26 is exposed, that is, the surface of the polysilicon film 26 is not covered with any film. The unnecessary portion (portion covering the buried insulating film 7) is removed by polishing by the CMP method. This polishing is continued until the top surface of the protruding portion 9 of the buried insulating film 7 and the surface (polishing surface) of the polysilicon film 26 are flush with each other. As a result, the floating gate 11 is embedded in the active region 10 formed of a recess surrounded by the protruding portion 9.

Next, as shown in FIGS. 9A and 9B, the protrusion 9 of the buried insulating film 7 is selectively removed from the surface with a uniform thickness so that the protrusion 9 becomes thin. Adjusted. The removal amount of the protruding portion 9 is set so that, for example, the aspect ratio of the buried insulating film 7 remaining after this processing is 2.3 to 3.67. By making the protrusion 9 thinner, a recess 27 having a depth corresponding to the height difference between the top surface of the floating gate 11 and the top surface of the protrusion 9 is formed between the adjacent floating gates 11. Next, an ONO film 28 is formed on the entire surface of the semiconductor substrate 5 so as to collectively cover the plurality of floating gates 11 by CVD. Next, after the ONO film 28 is formed, a polysilicon film 29 to which p-type impurity ions (for example, boron (B + ) ions) are added is deposited by CVD.

Next, as shown in FIGS. 10A and 10B, a tungsten silicide film 30 and a nitride film 31 are deposited on the entire surface of the semiconductor substrate 5 by the CVD method.
Next, as shown in FIGS. 11A and 11B, the nitride film 31, the tungsten silicide film 30, the polysilicon film 29, the ONO film 28, and the floating gate 11 are selectively formed along the longitudinal direction of the trench 6. Removed. Thereby, the semiconductor substrate 5 is partitioned into the memory cells 2 arranged in a matrix, and the source forming region 32 as an example of the first region of the present invention and the second region of the present invention so as to sandwich the floating gate 11. As an example, a drain formation region 33 is formed at the same time. Further, a nitride film 26 made of a part of the nitride film 31, a word line WL made of a part of the tungsten silicide film 30, a control gate 18 made of a part of the polysilicon film 29, and an ONO film made of a part of the ONO film 28. 17 is also formed at the same time. Next, boron (B + ) as a p-type impurity is ion-implanted into the source formation region 32 and the drain formation region 33, and then thermally diffused by annealing. As a result, the p + type source region 13, the p + type drain region 14 and the n type channel region 15 are simultaneously formed.

Next, a silicon nitride (SiN) film and a silicon oxide (SiO 2 ) film are deposited on the entire surface of the semiconductor substrate 5 by, eg, CVD. Thereafter, by etching back the silicon nitride film / silicon oxide film, the sidewall 20 is formed as shown in FIGS.
Thereafter, as shown in FIGS. 13A and 13B, the source wiring 21, the bit contact 22 and the bit line BL are formed, whereby the semiconductor device 1 shown in FIGS. 2A and 2B is obtained.

  According to the above method, as shown in FIGS. 3A and 3B, the trench 6 and the buried insulating film 7 are formed from a state in which the semiconductor substrate 5 is not subjected to any processing such as ion implantation. A process is performed. Therefore, it is possible to prevent a minute defect from occurring in the semiconductor substrate 5 before the formation of the STI structure including the trench 6 and the buried insulating film 7. Therefore, a good STI structure can be formed, and the yield can be improved.

  4A and 4B, since no electrode material is interposed between the hard mask 24 and the semiconductor substrate 5 when the trench 6 for the buried insulating film 7 is formed, the hard mask 24 The aspect ratio of the trench 6 including the opening 25 can be reduced as compared with the case where an electrode material is interposed. Further, as shown in FIGS. 2A and 2B, it is not necessary to overlap the floating gate 11 with the protruding portion 9 of the buried insulating film 7. Therefore, when designing the width A of the trench 6, the floating gate 11 In view of the width of the overlap portion, the trench width A need not be increased. Therefore, the trench 6 can be finely processed, and further, the embedding property of the buried insulating film 7 can be improved. As a result, the buried insulating film 7 having an aspect ratio of 2.3 to 3.67 can be formed as in this embodiment.

Further, as a result of not allowing the floating gate 11 to overlap the protruding portion 9 of the buried insulating film 7, no step is formed between the floating gate 11 and the buried insulating film 7. As a result, it is possible to effectively prevent the generation of weak spots and voids when the buried insulating film 7 is buried.
Further, as shown in FIGS. 8A and 8B, the floating gate 11 composed of a single layer is formed by polishing from a state in which the surface of the polysilicon film 26 is not covered with any film. It is not necessary to perform the polishing process for forming 11 a plurality of times. This eliminates the need for transfer between polishing apparatuses, and the polishing conditions for forming the floating gate 11 need only be set once, so that the manufacturing process can be simplified. Furthermore, since transfer between polishing apparatuses becomes unnecessary, adhesion of particles to the surface of the semiconductor substrate 5 (wafer) can be reduced.

  Further, as shown in FIGS. 7A and 7B and FIGS. 8A and 8B, after the hard mask 24 is removed, the poly buried in the active region 10 including the recess where the hard mask 24 was located. Since the silicon film 26 becomes the floating gate 11, the height of the floating gate 11 can be easily adjusted only by adjusting the thickness of the hard mask 24 in the steps of FIGS.

  Further, since the deposition process of the polysilicon film 26 by the CVD method is only one process, it is not necessary to put the semiconductor substrate 5 in and out of the CVD apparatus many times when forming the floating gate 11. Therefore, it is not necessary to consider that the polysilicon film 26 is unnecessarily oxidized, and it is not necessary to make a special preparation such as inserting the semiconductor substrate 5 into the CVD apparatus at a low temperature. As a result, the burden on the CVD apparatus can be reduced.

In the semiconductor device 1 manufactured by the above method, as shown in FIGS. 2A and 2B, the floating gate 11 is composed of a single layer straddling the p + type source region 13 and the p + type drain region 14. Therefore, a small cell size can be realized.
Further, as shown in FIGS. 2A and 2B, since the floating gate 11 does not overlap the protruding portion 9 of the buried insulating film 7, the distance between the adjacent floating gates 11 across the buried insulating film 7 is increased. can do. Thereby, since the parasitic capacitance between the adjacent floating gates 11 can be reduced, the threshold fluctuation due to the coupling effect between the floating gates 11 can be reduced. That is, conversely, when the floating gate 11 overlaps the protruding portion 9, the floating gate 11 approaches the adjacent floating gate 11, so that the distance between the floating gates 11 is inevitably reduced. Therefore, the parasitic capacitance tends to increase.

As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
For example, in the above-described embodiment, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 1 is reversed may be employed. For example, in the semiconductor device 1, the p-type portion may be n-type and the n-type portion may be p-type. Accordingly, the MOSFET constituting the memory cell 2 may be a p-type MOSFET or an n-type MOSFET as described above.

In addition, a peripheral circuit region in which various elements such as a charge pump, a Zener diode, and a MIS transistor are formed may be set around the memory cell 2.
In addition, various design changes can be made within the scope of matters described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Memory cell 3 Bit line drive circuit 4 Word line drive circuit 5 Semiconductor substrate 6 Trench 7 Buried insulating film 8 Buried part 9 Protruding part 10 Active region 11 Floating gate 12 N-type well 13 p + type source region 14 p + Type drain region 15 n type channel region 16 tunnel oxide film 17 ONO film 18 control gate 19 nitride film 20 sidewall 21 source wiring 22 bit contact 23 pad oxide film 24 hard mask 25 opening 26 polysilicon film 27 recess 28 ONO film 29 Polysilicon film 30 Tungsten silicide film 31 Nitride film 32 Source formation region 33 Drain formation region

Claims (12)

  1. A semiconductor substrate having a well region of a first conductivity type formed on a surface portion;
    A plurality of stripe-shaped trenches selectively formed in the well region and separating the well region into a plurality of active regions;
    A buried insulating film buried in the trench so as to have a protruding portion protruding above the surface of the semiconductor substrate;
    A pair of regions formed in the active region and spaced apart from each other along the longitudinal direction of the trench, the second conductivity type source region providing a channel region of the first conductivity type in a region between them And a drain region;
    A single layer straddling the source region and the drain region, and including a floating gate formed so as to protrude above the protruding portion so as not to overlap the protruding portion of the buried insulating film,
    A semiconductor device, wherein the buried insulating film has an aspect ratio of 2.3 to 3.67.
  2. The source region and the drain region are a p-type source region and a p-type drain region, respectively;
    The semiconductor device according to claim 1, wherein the well region and the channel region are an n-type well region and an n-type channel region, respectively.
  3. The first width W 1 of the floating gate along the width direction of the trench and the second width W 2 of the floating gate along the longitudinal direction of the trench are both 100 nm or less. The semiconductor device described.
  4.   The semiconductor device according to claim 1, wherein the floating gate is made of polysilicon.
  5. Forming an etching mask having a plurality of stripe-shaped openings selectively on the semiconductor substrate having the first conductivity type well region formed on the surface portion without interposing an electrode material between the semiconductor substrate and the semiconductor substrate; When,
    Forming a trench that separates the well region into a plurality of active regions by etching the semiconductor substrate through the openings of the etching mask;
    By supplying an insulating material so as to be filled back from the bottom of the trench to the top surface of the etching mask, a buried insulating film having a protruding portion protruding from the surface of the semiconductor substrate by the thickness of the etching mask is embedded in the trench. Process,
    Removing the etching mask to expose the active region surrounded by the protrusion, and burying an electrode material in the active region, and depositing an electrode material covering the remaining buried insulating film;
    By polishing the electrode material from a state where the electrode material is exposed until the top surface of the electrode material is flush with the top surface of the protruding portion of the buried insulating film, Forming a floating gate,
    Forming a recess between the adjacent floating gates by selectively removing the protruding portion of the buried insulating film;
    By selectively removing the floating gate along the longitudinal direction of the trench, a pair of the first region and the second region formed of a part of the semiconductor substrate are exposed with a space therebetween, and between them. Forming a first conductivity type channel region in the well region of
    Forming a source region in the first region and forming a drain region in the second region by supplying a second conductivity type impurity to the first region and the second region. Production method.
  6.   In the step of forming the etching mask, the thickness of the etching mask is adjusted so that the aspect ratio of the space including the trench and the opening when forming the buried insulating film is 2.3 to 3.67. The method for manufacturing a semiconductor device according to claim 5, wherein the setting is performed.
  7.   7. The semiconductor device according to claim 5, wherein in the step of forming the recess, the removal amount of the protruding portion is set so that an aspect ratio of the buried insulating film is 2.3 to 3.67. Production method.
  8. The well region and the channel region are an n-type well region and an n-type channel region, respectively;
    8. The semiconductor according to claim 5, wherein the step of forming the source region and the drain region includes a step of forming a p-type source region and a p-type drain region by supplying a p-type impurity. Device manufacturing method.
  9. The step of forming the trench includes the step of setting the pitch of the trench so that the first width W 1 of the adjacent trench is 100 nm or less,
    The step of selectively removing the floating gate is such that a second width W 2 along the longitudinal direction of the trench of the floating gate remaining between the first region and the second region is 100 nm or less. The manufacturing method of the semiconductor device as described in any one of Claims 5-8 including the process of setting the pitch of the said floating gate.
  10.   The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the floating gate includes a step of polishing the electrode material by a CMP method.
  11.   The method of manufacturing a semiconductor device according to claim 5, wherein the step of forming the buried insulating film includes a step of supplying the insulating material by a high density plasma (HDP) CVD method.
  12.   The method of manufacturing a semiconductor device according to claim 5, wherein the etching mask is made of a silicon nitride (SiN) film.
JP2013114546A 2013-05-30 2013-05-30 Semiconductor device, and method of manufacturing the same Pending JP2014236015A (en)

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JP2013114546A JP2014236015A (en) 2013-05-30 2013-05-30 Semiconductor device, and method of manufacturing the same
US14/290,138 US9082654B2 (en) 2013-05-30 2014-05-29 Method of manufacturing non-volatile memory cell with simplified step of forming floating gate
CN201410240551.5A CN104218075B (en) 2013-05-30 2014-05-30 The manufacturing method of semiconductor devices and semiconductor devices
US14/735,179 US9425203B2 (en) 2013-05-30 2015-06-10 Non-volatile memory cell in semiconductor device
US15/214,587 US10622443B2 (en) 2013-05-30 2016-07-20 Semiconductor device with different material layers in element separation portion trench and method for manufacturing semiconductor device

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