CN113707665A

CN113707665A - Memory and forming method thereof

Info

Publication number: CN113707665A
Application number: CN202111019363.6A
Authority: CN
Inventors: 刘毅华; 刘峻; 范鲁明
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-01-02
Filing date: 2019-01-02
Publication date: 2021-11-26
Also published as: CN109742081B; CN109742081A

Abstract

The invention relates to a memory and a forming method thereof, wherein the forming method of the memory comprises the following steps: providing a substrate, a storage stack structure formed on the substrate, a trench column structure penetrating through the storage stack structure and a separation wall, wherein a common source is formed in the substrate at the bottom of the separation wall; thinning the back of the substrate; and forming a conducting layer on the back of the thinned substrate to be connected with the common source, wherein the conducting layer is used as a common source contact part. The method is beneficial to improving the performance of the memory.

Description

Memory and forming method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof.

Background

In recent years, Flash Memory (Flash Memory) memories have been developed particularly rapidly. The main characteristic of flash memory is that it can keep the stored information for a long time without power-up, and it has the advantages of high integration level, fast access speed, easy erasing and rewriting, so it is widely used in microcomputer, automation control and other fields. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), the three-dimensional flash memory (3D NAND) technology has been rapidly developed.

The 3D NAND memory comprises a substrate and a memory stack structure formed on the surface of the substrate, wherein a channel column structure penetrating through the surface of the substrate is formed in the memory stack structure to form vertically arranged memory strings, a bottom selection transistor (BSG) is arranged at the bottom of each memory string, a common source contact penetrating through the substrate is further formed in the memory stack structure, a common source doped region is formed in the substrate at the bottom of the common source contact, and the bottom selection transistor (BSG) is connected to a rear-end interconnection circuit through the common source doped region.

Common source contacts (ACS) are typically filled with either all tungsten or polysilicon and tungsten. However, the following problems currently exist: too high stress of the full tungsten fill can cause the subsequent process to be greatly affected; although the stress can be reduced by filling the polysilicon and the tungsten, the resistance of the common source contact (ACS) is higher due to the larger resistance of the polysilicon, which affects the performance of the memory.

Disclosure of Invention

The invention provides a memory and a forming method thereof, which can reduce the stress of a common source contact part.

The invention provides a method for forming a memory, which comprises the following steps: providing a substrate, a storage stack structure formed on the substrate, a trench column structure penetrating through the storage stack structure and a separation wall, wherein a common source is formed in the substrate at the bottom of the separation wall; thinning the back of the substrate; and forming a conducting layer on the back of the thinned substrate to be connected with the common source, wherein the conducting layer is used as a common source contact part.

Optionally, forming a conductive layer on the back surface of the thinned substrate to connect the common source, where the step of forming the conductive layer as a common source contact further includes the steps of: forming a dielectric layer on the back of the thinned substrate; etching the dielectric layer to form an opening, wherein the common source in the substrate is exposed out of the opening; and filling the conducting layer in the opening to be connected with the common source, wherein the conducting layer is used as a common source contact part.

Optionally, in the step of thinning the back surface of the substrate, the dielectric layer formed in the substrate is exposed; etching the dielectric layer to form an opening, wherein the common source in the substrate is exposed out of the opening; and filling a conducting layer in the opening to be connected with the common source, wherein the conducting layer is used as a common source contact part.

Optionally, the substrate comprises a bulk silicon layer, a dielectric layer, a thin silicon layer set layer, the dielectric layer being formed between the bulk silicon layer and the thin silicon layer.

Optionally, the method for exposing the dielectric layer formed in the substrate includes: and removing the bulk silicon layer structure in the substrate until the dielectric layer is exposed.

Optionally, a common source doped region is formed in the substrate at the bottom of the isolation wall.

Optionally, the memory stack structure includes alternately stacked insulating layers and control gate layers.

Optionally, a storage base is provided, where the storage base includes the substrate, a storage stack structure formed on the substrate, a trench pillar structure penetrating through the storage stack structure, and a partition wall, and a common source is formed in the substrate at the bottom of the partition wall.

Optionally, the method for forming the storage substrate includes: providing the substrate, and forming an initial stacked structure on the substrate, wherein the initial stacked structure comprises insulating layers and sacrificial layers which are alternately stacked; forming a channel pillar structure through the initial stacked structure; forming a gate line isolation groove penetrating through the initial stacking structure; doping the substrate at the bottom of the grid line isolation groove to form a common source; removing the sacrificial layer along the grid line separation groove; forming a control gate layer between adjacent insulating layers; and filling the grid line separation groove to form a separation wall.

Optionally, the method further comprises: and providing a circuit base, and bonding and connecting the front surface of the storage base with the front surface of the circuit base before thinning the back surface of the substrate.

Optionally, a width of the opening is smaller than or equal to a width of the common source doped region.

Optionally, a bit line connected to the top of the channel pillar structure portion is further formed on the top of the memory stack structure on the front surface of the memory substrate.

The present invention also provides a memory, comprising: the memory device comprises a substrate, a storage stack structure formed on the substrate, a channel column structure penetrating through the storage stack structure and a separation wall, wherein a common source is formed in the substrate at the bottom of the separation wall; a conductive layer on the back side of the substrate connected to the common source, the conductive layer acting as a common source contact.

Optionally, the common source comprises a common source doped region.

Optionally, the method further comprises: the dielectric layer is positioned on the back surface of the substrate, and the conducting layer is positioned in the dielectric layer.

Optionally, the memory device further comprises a storage base, wherein the storage base comprises a substrate, a storage stack structure formed on the substrate, a trench pillar structure penetrating through the storage stack structure, and a partition wall, and a common source is formed in the substrate at the bottom of the partition wall.

Optionally, the method further comprises: and the front surface of the storage substrate is in bonding connection with the front surface of the circuit substrate.

Optionally, a width of the conductive layer is less than or equal to a width of the common source doped region.

Optionally, a bit line connected to the top of the channel pillar structure is further formed on the top of the storage stack structure on the front surface of the storage substrate.

According to the forming method of the memory, the conducting layer is formed on the back surface of the substrate and connected with the common source, and the conducting layer and the storage stacking structure are located on two sides of the substrate, so that the isolation performance between the control gate layer in the storage stacking structure and the conducting layer is improved, and the problem of electric leakage between the control gate layer and the common source contact part is avoided.

Furthermore, the thickness of the dielectric layer on the back of the substrate is small, and the thickness of the conducting layer is naturally low, so that the resistance of the conducting layer is favorably reduced, and the power consumption when the source voltage is applied to the common source is reduced. When the conducting layer is made of metal materials such as tungsten, stress generated on the storage substrate is less due to the fact that the conducting layer is low in thickness, and the structure of the storage can be prevented from changing due to the stress, so that the reliability of the storage can be improved. And because the conducting layer is formed after the front structure of the whole memory is formed, the stress generated by the conducting layer can be adjusted by the modes of thin film deposition and the like on the back surface of the substrate.

Drawings

Fig. 1 to 5 are schematic structural diagrams illustrating a process of forming a memory according to an embodiment of the invention;

fig. 6A to 6B are schematic structural diagrams illustrating a formation process of a memory according to an embodiment of the invention.

Detailed Description

The following describes in detail a specific embodiment of the memory and the forming method thereof according to the present invention with reference to the accompanying drawings.

Referring to fig. 1, a storage substrate is provided, which includes: a substrate 100 and a storage stack structure formed on a front surface of the substrate; a channel column structure 130 penetrating to the surface of the substrate and a separation wall 140 penetrating the initial stacked structure to the surface of the substrate are further formed in the storage stacked structure; a common source is formed in the substrate 100 at the bottom of the isolation wall 140, and the common source includes a common source doped region 141.

The substrate 100 may be a semiconductor material, such as a single crystal silicon substrate, a single crystal germanium substrate, an SOI (silicon on insulator) substrate, a GOI (germanium on insulator) substrate, or the like, and the substrate 100 may also be n-type doped or p-type doped. The skilled person can select suitable materials as the substrate according to actual requirements, and the substrate is not limited herein. In this embodiment, the substrate 100 is a silicon-on-insulator substrate, and includes a bulk silicon layer 111, a dielectric layer 112, and a thin silicon layer 113 on the surface of the dielectric layer 112. The surface of the thin silicon layer 113 serves as the front surface of the substrate 100.

The storage stack structure comprises insulating layers 121 and control gate layers 122 which are stacked alternately, the insulating layers 121 are made of silicon oxide, and the control gate layers 122 comprise gate dielectric layers and control gates. The memory stack structure includes a core region and a step region at the periphery of the core region, and the channel pillar structure 130 is formed in the core region.

The trench pillar structure 130 includes a semiconductor epitaxial layer 131 located in the thin silicon layer 113 of the bottom substrate 100, a functional sidewall 132 located on a sidewall of the trench hole, a channel layer 133 covering the functional sidewall 132 and connected to the semiconductor epitaxial layer 131, and a trench dielectric layer 134 filling the trench hole. The functional sidewall 132 includes a charge blocking layer, a charge tunneling layer, and a charge trapping layer, and is generally an O-N-O (silicon oxide-silicon nitride-silicon oxide) structure, the channel layer 133 is made of polysilicon, and the channel dielectric layer 134 is made of insulating dielectric materials such as silicon oxide.

The length direction of the isolation wall 140 is along the y-axis direction, and isolates the control gate layer 122. Only one partition wall 140 is shown in fig. 1, and in an actual memory structure, a plurality of partition walls 140 arranged in parallel are formed in the memory stack structure to divide the control gate layer 122 into a plurality of regions. A common source doped region 141 is further formed in the substrate 100 at the bottom of the isolation wall 140, and is formed in the thin silicon layer 113.

Bit lines 136 are formed on the tops of the channel pillar structures 130 and arranged along the y-axis direction, and the tops of the channel pillar structures 130 in the same column arranged in the y-axis direction are connected through contacts 135.

The substrate 100 is further covered with an insulating dielectric layer 150 to keep the stacked structure of the substrate 100 flat and to facilitate forming electrical connection structures in the dielectric layer, such as the contact 135 and the bit line 136 on top of the trench pillar structure 130. Word line contacts (not shown) may also be formed in the insulating dielectric layer 150 above the step regions and penetrate to the steps of the control gate layers 122.

The memory substrate is formed with a plurality of memory cells of the memory structure, and electrically connecting structures such as bit lines and word line contacts for connecting the memory cells. And a number of memory cells are partitioned into a plurality of memory blocks by the partition walls 140.

The forming method of the substrate mainly comprises the following steps: providing a substrate 100, and forming an initial stacked structure on the front surface of the substrate 100, wherein the initial stacked structure comprises insulating layers 121 and sacrificial layers which are alternately stacked; forming channel pillar structures 130 through the initial stacked structure to the surface of the substrate 100; forming a gate line isolation trench penetrating the initial stacked structure to the surface of the substrate 100; doping the substrate at the bottom of the grid line isolation groove to form a common source doped region 141; removing the sacrificial layer along the grid line separation groove; forming a control gate layer 122 in an opening formed between the adjacent insulating layers 121 after the sacrificial layer is removed; and then the gate line isolation groove is filled to form the isolation wall 140. The common source doping region 141 is formed before the formation of the storage stack structure, so that the influence of a high-temperature process of a doping process on the storage stack structure can be avoided.

Referring to fig. 2, a circuit substrate 200 is provided, and the front surface of the memory substrate is bonded to the front surface of the circuit substrate 200.

A CMOS control circuit is formed in the circuit substrate 200 as a peripheral circuit of the memory, and the circuit substrate 200 is bonded to the memory substrate 100 to electrically connect the peripheral circuit and the memory cell.

The circuit substrate 200 and the storage substrate are in hybrid bonding, and include a dielectric layer-dielectric layer, a dielectric layer-conductive layer, and a conductive layer-conductive layer bonding type.

Referring to fig. 3, the back surface of the substrate 100 is thinned to expose the dielectric layer 112 in the substrate 100.

And thinning the back surface of the substrate 100 by a wet etching process. In this embodiment, the substrate 100 is an SOI, and a wet etching process with high etching selectivity to the bulk silicon layer 111 may be adopted to etch the bulk silicon layer 111 until the dielectric layer 112 is exposed.

In other embodiments, the back side of the substrate 100 may be thinned by a chemical mechanical polishing or dry etching process.

After the storage base is bonded with the circuit base 200, the back surface of the substrate 100 is thinned, so that damage to a storage stacking structure on the front surface of the storage base in the thinning process can be avoided.

In another embodiment, referring to fig. 6A, the substrate 600 of the storage base is a single crystal silicon substrate; referring to fig. 6B, the back surface of the substrate 600 is thinned to a certain thickness and then stopped, preferably, the bottom of the common source doped region 141 is exposed. The thickness of the substrate 100 after thinning is 1 μm to 2 μm. Then, a dielectric layer 601 is formed on the back surface of the thinned substrate 600, wherein the dielectric layer 601 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the dielectric layer 601 may be 1 μm to 4 μm, and in other specific embodiments, the thickness of the dielectric layer 601 may also be other values.

Referring to fig. 4, the dielectric layer 112 is etched to form an opening 401, and the opening 401 exposes the common source doped region 141 in the thin silicon layer 113.

The width of the opening 401 is smaller than or equal to the width of the common source doped region 141. The problems of electric leakage or short circuit between the conductive layer formed in the opening 401 and the semiconductor epitaxial layer 131 of the channel pillar structure 130 are avoided.

In one embodiment, the opening 401 may be formed by a photolithography-etching process using a mask for forming the gate line spacer, so that the position and the size of the opening 401 correspond to those of the common source doped region 141, and no additional mask cost is required.

The opening 401 corresponds to the common source doped region 141, and the length direction is along the y-axis direction.

Referring to fig. 5, the opening 401 (see fig. 4) is filled with a conductive layer 501, the conductive layer 501 is connected to the common source doped region 141, and the conductive layer 501 serves as a common source contact for connecting to a source voltage.

The material of the conductive layer 501 includes at least one of polysilicon, tungsten, aluminum, or copper. In one embodiment, the material of the conductive layer 501 is tungsten; in another embodiment, the conductive layer 501 is a stacked structure of a polysilicon layer and a tungsten layer.

The method for forming the conductive layer 501 includes: depositing a conductive material on the surface of the dielectric layer 112, wherein the opening 401 is filled with the conductive material; and with the dielectric layer 112 as a stop layer, planarizing the conductive material to form a conductive layer 501 in the opening 401.

Since the dielectric layer 112 has a small thickness, the thickness of the conductive layer 501 is naturally low, which is beneficial to reducing the resistance of the conductive layer 501 and reducing the power consumption when a source voltage is applied to the common source doped region 141. When the conductive layer 501 is made of metal materials such as tungsten, stress on the storage substrate is low due to the low thickness of the conductive layer 501, and the structure of the memory can be prevented from being changed due to the stress, so that the reliability of the memory can be improved. And because the conductive layer 501 is formed after the front structure of the whole memory is formed, the stress generated by the conductive layer 501 can be adjusted by performing thin film deposition on the back surface of the substrate.

Further, the conductive layer 501 is formed on the back surface of the substrate as a common source contact portion, and is located on both sides of the substrate together with the storage stacked structure, so that the isolation performance between the control gate layer 122 in the storage stacked structure and the conductive layer 501 is improved, and the problem of electric leakage between the control gate layer 122 and the common source contact portion is avoided.

The embodiment of the invention also provides a memory.

Fig. 5 is a schematic structural diagram of a memory according to an embodiment of the invention.

The memory includes: the memory substrate comprises a thin silicon layer 113 and a memory stack structure formed on the front surface of the thin silicon layer 113, wherein a channel column structure 130 and a partition wall 400 penetrating through the memory stack structure to the surface of the thin silicon layer 113 are formed in the memory stack structure, and a common source doped region 141 is formed in the thin silicon layer 113 at the bottom of the partition wall 400; a dielectric layer 112 on the back of the thin silicon layer 113; and the conducting layer 501 is positioned in the dielectric layer 112 and connected to the common source doped region 141, and the conducting layer 501 serves as a common source contact.

In this embodiment, the thin silicon layer 113 and the dielectric layer 112 are thinned structures of an SOI substrate, the thin silicon layer 113 is a thin silicon layer on the surface of the SOI substrate, and the dielectric layer 112 is an insulating dielectric layer in the middle of the SOI substrate. The thin silicon layer 113 serves as a substrate for forming a storage stack structure, and in other embodiments, the substrate for forming the storage stack structure may also be another semiconductor substrate, for example, a portion remaining after a single crystal silicon substrate is thinned; and the dielectric layer 112 is formed on the surface of the substrate by a deposition process. The thickness of the thinned substrate is 1-2 μm.

The memory stack structure includes insulating layers 121 and control gate layers 122 alternately stacked. The insulating layer 121 is made of silicon oxide, and the control gate layer 122 includes a gate dielectric layer and a control gate. The memory stack structure includes a core region and a step region at the periphery of the core region, and the channel pillar structure 130 is formed in the core region.

The trench pillar structure 130 includes a semiconductor epitaxial layer 131 located in the substrate 113, a functional sidewall 132 located on a sidewall of the trench hole, a channel layer 133 covering the functional sidewall 132 and connected to the semiconductor epitaxial layer 131, and a trench dielectric layer 134 filling the trench hole. The functional sidewall 132 includes a charge blocking layer, a charge tunneling layer, and a charge trapping layer, and is generally an O-N-O (silicon oxide-silicon nitride-silicon oxide) structure, the channel layer 133 is made of polysilicon, and the channel dielectric layer 134 is made of insulating dielectric materials such as silicon oxide.

The length direction of the isolation wall 140 is along the y-axis direction, and the control gate layer 122 in different regions is isolated. In fig. 5, only one isolation wall 140 is shown, and in an actual memory structure, a plurality of isolation walls 140 arranged in parallel are formed in the memory stack structure to divide the control gate layer 122 into a plurality of regions. A common source doped region 141 is further formed in the substrate 100 at the bottom of the isolation wall 140, and is formed in the thin silicon layer 113.

The substrate 113 is further covered with an insulating dielectric layer 150 to keep the stacked structure of the substrate 113 flat and to facilitate forming electrical connection structures in the dielectric layer, such as the contact 135 and the bit line 136 on top of the trench pillar structure 130. Word line contacts (not shown) may also be formed in the insulating dielectric layer 150 above the step regions and penetrate to the steps of the control gate layers 122.

The memory further comprises: and the front surface of the storage substrate is in bonding connection with the front surface of the circuit substrate 200 through a circuit substrate 200. A CMOS control circuit is formed in the circuit substrate 200 as a peripheral circuit of the memory, and the circuit substrate 200 is bonded to the memory substrate 100 to electrically connect the peripheral circuit and the memory cell.

The dielectric layer 112 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the dielectric layer 112 may be 1 μm to 4 μm.

The width of the conductive layer 501 is smaller than or equal to the width of the common source doped region 141, so that the problems of electric leakage or short circuit between the conductive layer and the semiconductor epitaxial layer 131 of the adjacent channel column structure 130 are avoided. The material of the conductive layer 501 includes at least one of polysilicon, tungsten, aluminum, or copper. In one embodiment, the material of the conductive layer 501 is tungsten; in another embodiment, the conductive layer 501 is a stacked structure of a polysilicon layer and a tungsten layer.

Further, the conductive layer 501 is formed on the back surface of the substrate 113 as a common source contact portion, and is located on both sides of the substrate 113 with the storage stacked structure, so that the isolation performance between the control gate layer 122 in the storage stacked structure and the conductive layer 501 is improved, and the problem of electric leakage between the control gate layer 122 and the common source contact portion is avoided.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A method for forming a memory, comprising:

providing a substrate, a storage stack structure formed on the substrate, a trench column structure penetrating through the storage stack structure and a separation wall, wherein a common source is formed in the substrate at the bottom of the separation wall;

thinning the back of the substrate;

and forming a conducting layer on the back of the thinned substrate to be connected with the common source, wherein the conducting layer is used as a common source contact part.

2. The method of claim 1, wherein a conductive layer is formed on the back of the thinned substrate to connect the common source, and the step of forming the conductive layer as a common source contact further comprises the steps of:

forming a dielectric layer on the back of the thinned substrate;

etching the dielectric layer to form an opening, wherein the common source in the substrate is exposed out of the opening;

and filling the conducting layer in the opening to be connected with the common source, wherein the conducting layer is used as a common source contact part.

3. The method for forming a memory according to claim 1, wherein in the step of thinning the back surface of the substrate, the dielectric layer formed in the substrate is exposed; etching the dielectric layer to form an opening, wherein the common source in the substrate is exposed out of the opening; and filling a conducting layer in the opening to be connected with the common source, wherein the conducting layer is used as a common source contact part.

4. The method of claim 3, wherein the substrate comprises a bulk silicon layer, a dielectric layer, and a thin silicon layer set layer, the dielectric layer being formed between the bulk silicon layer and the thin silicon layer.

5. The method of claim 3, wherein the exposing the dielectric layer formed in the substrate comprises: and removing the bulk silicon layer structure in the substrate until the dielectric layer is exposed.

6. The method as claimed in claim 1, wherein a common source doped region is formed in the substrate at the bottom of the isolation wall.

7. The method of claim 1, wherein the memory stack structure comprises alternately stacked insulating layers and control gate layers.

8. The method as claimed in claim 1, wherein a storage base is provided, the storage base includes the substrate, a storage stack structure formed on the substrate, a trench pillar structure penetrating the storage stack structure, and a partition wall, and a common source is formed in the substrate at the bottom of the partition wall.

9. The method of claim 8, wherein the method of forming the storage substrate comprises:

providing the substrate, and forming an initial stacked structure on the substrate, wherein the initial stacked structure comprises insulating layers and sacrificial layers which are alternately stacked;

forming a channel pillar structure through the initial stacked structure;

forming a gate line isolation groove penetrating through the initial stacking structure;

doping the substrate at the bottom of the grid line isolation groove to form a common source;

removing the sacrificial layer along the grid line separation groove;

forming a control gate layer between adjacent insulating layers;

and filling the grid line separation groove to form a separation wall.

10. The method of claim 8, further comprising: and providing a circuit base, and bonding and connecting the front surface of the storage base with the front surface of the circuit base before thinning the back surface of the substrate.

11. The method as claimed in claim 2 or 3, wherein the width of the opening is less than or equal to the width of the common source doped region.

12. The method as claimed in claim 1, wherein a bit line is further formed on the top of the memory stack structure on the front surface of the memory substrate to connect the top of the channel pillar structure.

13. A memory, comprising:

the memory device comprises a substrate, a storage stack structure formed on the substrate, a channel column structure penetrating through the storage stack structure and a separation wall, wherein a common source is formed in the substrate at the bottom of the separation wall;

a conductive layer on the back side of the substrate connected to the common source, the conductive layer acting as a common source contact.

14. The memory of claim 13, wherein the common source comprises a common source doped region.

15. The memory of claim 13, further comprising: the dielectric layer is positioned on the back surface of the substrate, and the conducting layer is positioned in the dielectric layer.

16. The memory of claim 13, wherein the memory stack structure comprises alternating layers of insulation and control gates.

17. The memory of claim 13, further comprising a storage base, wherein the storage base comprises a substrate, a storage stack structure formed on the substrate, a channel pillar structure penetrating the storage stack structure, and a partition wall, and a common source is formed in the substrate at the bottom of the partition wall.

18. The memory of claim 17, further comprising: and the front surface of the storage substrate is in bonding connection with the front surface of the circuit substrate.

19. The memory of claim 13, wherein a width of the conductive layer is less than or equal to a width of the common source doped region.

20. The memory of claim 17, wherein the top of the memory stack structure on the front surface of the memory substrate is further formed with a bit line connected to the top of the channel pillar structure.