CN109273456B - Method for manufacturing three-dimensional memory - Google Patents
Method for manufacturing three-dimensional memory Download PDFInfo
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- CN109273456B CN109273456B CN201811120270.0A CN201811120270A CN109273456B CN 109273456 B CN109273456 B CN 109273456B CN 201811120270 A CN201811120270 A CN 201811120270A CN 109273456 B CN109273456 B CN 109273456B
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
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Abstract
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a three-dimensional memory. The manufacturing method of the three-dimensional memory comprises the following steps: providing a substrate, wherein the substrate is provided with a stacked structure and a channel hole penetrating through the stacked structure along the direction vertical to the substrate, and the stacked structure comprises a plurality of gate layers which are sequentially arranged along the direction vertical to the substrate; forming a NAND string on a sidewall surface of the channel hole; and depositing a gate layer material on the top of the NAND string along the channel hole to form a channel hole plug. The invention simplifies the manufacturing steps of the three-dimensional memory, reduces the manufacturing cost of the three-dimensional memory and is beneficial to improving the performance of the three-dimensional memory.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a three-dimensional memory.
Background
As technology develops, the semiconductor industry continues to seek new ways to produce such that each memory die in a memory device has a greater number of memory cells. In non-volatile memories, such as NAND memories, one way to increase memory density is through the use of vertical memory arrays, i.e., 3D NAND (three-dimensional NAND) memories; with higher and higher integration, 3D NAND memories have evolved from 32 layers to 64 layers, and even higher.
In the 3D NAND memory, a stacked structure formed by alternately stacking interlayer insulating layers and gates is provided, the stacked structure including a core region and a step region disposed around the core region. The core area is used for storing information; the step area is positioned at the top of the stacked structure and used for transmitting control information to the core area so as to realize the reading and writing of the information in the core area. Meanwhile, in order to realize control of data storage in the 3D NAND memory, a channel hole penetrating through the stack structure is further included in a core region of the stack structure.
However, in the conventional manufacturing process of the 3D NAND memory, the operation is complicated, and the sidewall of the channel hole is easily affected, thereby causing a reduction in production efficiency and a reduction in 3D NAND memory performance.
Therefore, how to reduce the manufacturing cost of the three-dimensional memory, simplify the manufacturing steps of the 3D NAND memory, and improve the performance of the three-dimensional memory is a technical problem to be solved.
Disclosure of Invention
The invention provides a manufacturing method of a three-dimensional memory, which is used for solving the problem that the existing three-dimensional memory has higher manufacturing cost, simplifying the manufacturing steps of the three-dimensional memory and effectively improving the performance of the three-dimensional memory.
In order to solve the above problems, the present invention provides a method for manufacturing a three-dimensional memory, comprising the steps of:
providing a substrate, wherein the substrate is provided with a stacked structure and a channel hole penetrating through the stacked structure along the direction vertical to the substrate, and the stacked structure comprises a plurality of gate layers which are sequentially arranged along the direction vertical to the substrate;
forming a NAND string on a sidewall surface of the channel hole;
and depositing a gate layer material on the top of the NAND string along the channel hole to form a channel hole plug.
Preferably, the step of forming the NAND string on the sidewall surface of the channel hole includes:
forming a blocking layer on the surface of the side wall of the channel hole;
forming a charge trapping layer on the surface of the barrier layer;
forming a tunneling layer on the surface of the charge trapping layer;
and forming a channel layer on the surface of the tunneling layer.
Preferably, the specific step of forming the trench hole plug includes:
etching the NAND string back along the channel hole to form a groove;
and depositing a grid layer material in the groove to form the channel hole plug.
Preferably, the specific step of etching back the NAND string along the channel hole comprises:
and etching the channel layer along the channel hole back to form the groove.
Preferably, the step of depositing the gate layer material in the recess includes:
depositing a conductive bonding material on the surface of the side wall of the tunneling layer and the top of the channel layer along the groove to form a bonding layer;
and depositing a gate layer material on the surface of the bonding layer along the groove to form the channel hole plug.
Preferably, the method further comprises the following steps before forming the bonding layer:
and depositing a conductive material on the top of the channel layer along the groove to form a conductive layer.
Preferably, the conductive bonding material is titanium nitride; the specific steps of depositing a conductive bonding material along the recess on the sidewall surface of the tunneling layer and the top of the channel layer include:
and depositing titanium nitride on the surface of the side wall of the tunneling layer and the top of the channel layer by adopting an atomic layer deposition process to form the bonding layer.
Preferably, the conductive material is titanium; the specific steps of depositing a conductive material on top of the channel layer along the recess include:
and depositing the titanium on the top of the channel layer by adopting a chemical vapor deposition process to form a conducting layer made of a titanium silicide material.
Preferably, the stacked structure includes a core region and a step region disposed around the core region; the method also comprises the following steps after the channel hole plug is formed:
forming a dielectric layer covering the stacked structure;
and etching the dielectric layer, forming a first contact hole penetrating to the channel hole plug in the core region, and simultaneously forming a second contact hole penetrating to the surface of the grid layer in the step region.
Preferably, the three-dimensional memory is a 3D NAND memory.
The manufacturing method of the three-dimensional memory provided by the invention adopts the trench hole plug made of the same material as the grid layer as the connecting plug which is directly contacted with the NAND string in the three-dimensional memory trench hole, and compared with the traditional polysilicon plug or amorphous silicon plug, the etching selectivity of the three-dimensional memory trench hole plug is the same as the etching selectivity of the grid layer in the three-dimensional memory, so that the etching process of contacting the plug hole in a step area and the etching process of contacting the plug hole in the trench hole area can be integrated into a whole, the manufacturing steps of the three-dimensional memory are simplified, the manufacturing cost of the three-dimensional memory is reduced, the damage to the side wall of the trench hole in the etching process of the contact plug hole in the trench area is avoided, and the performance of the three-.
Drawings
FIG. 1 is a flow chart of a method for fabricating a three-dimensional memory according to an embodiment of the present invention;
FIGS. 2A-2D are schematic diagrams of the main process structures in the fabrication of a three-dimensional memory according to the embodiments of the present invention;
FIG. 3 is a schematic diagram of the overall structure of a three-dimensional memory fabricated in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of a channel hole structure in an embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of a method for manufacturing a three-dimensional memory according to the present invention with reference to the accompanying drawings.
In the manufacturing process of the three-dimensional memory, a total of five steps (i.e., five masks) are generally required to complete the etching of all the contact plug holes in the three-dimensional memory, i.e., the upper contact hole, the middle contact hole, the lower contact hole, the peripheral contact hole and the trench contact hole, which increases the manufacturing cost of the three-dimensional memory. In order to reduce the manufacturing cost of the three-dimensional memory, the contact plug hole etching process of the step area in the three-dimensional memory and the contact plug hole (namely, the channel contact hole) etching process of the channel hole area can be combined into a whole. However, the etch stop layer in the step region contacting the plug hole is a gate layer made of a metal material, and the etch stop layer in the channel region contacting the plug hole is a channel plug made of a polysilicon material. The metal material and the polysilicon material have a large difference in etching selectivity, and in the process of simultaneously etching and forming the contact plug hole of the step region and the contact plug hole of the channel hole region, the channel hole is damaged, for example, over-etching occurs, so that the performance of the three-dimensional memory is reduced.
In order to solve the above problems, the present embodiment provides a method for manufacturing a three-dimensional memory, fig. 1 is a flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present invention, fig. 2A to 2D are schematic diagrams of main process structures in a manufacturing process of a three-dimensional memory according to an embodiment of the present invention, and fig. 3 is a schematic diagram of an overall structure of a three-dimensional memory manufactured according to an embodiment of the present invention. The three-dimensional memory of the present embodiment is preferably a 3D NAND memory. As shown in fig. 1, fig. 2A to fig. 2D, and fig. 3, the method for manufacturing a three-dimensional memory according to the present embodiment includes the following steps:
step S11, providing a substrate 10, where the substrate 10 has a stacked structure and a channel hole 13 penetrating through the stacked structure in a direction perpendicular to the substrate 10, and the stacked structure includes several gate layers 11 arranged in sequence in the direction perpendicular to the substrate 10. The substrate 10 may be a Si substrate, a Ge substrate, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator) substrate. Preferably, the three-dimensional memory is a 3D NAND memory. In this embodiment, the substrate 10 is preferably a Si substrate for supporting device structures thereon.
In step S12, NAND strings 14 are formed on the sidewall surfaces of the channel holes 13.
Preferably, the step of forming the NAND string 14 on the sidewall surface of the channel hole 13 includes:
forming a barrier layer 21 on the sidewall surface of the channel hole 13;
forming a charge trapping layer 22 on the surface of the blocking layer 21;
forming a tunneling layer 23 on the surface of the charge trapping layer 22;
forming a channel layer 24 on the surface of the tunneling layer 23.
The material of the barrier layer 21 may be silicon oxide and/or silicon oxynitride; the charge trapping layer 22 may be a single layer or multiple layers of silicon nitride and/or silicon oxynitride; the tunneling layer 23 may be made of silicon oxide and/or silicon oxynitride; the material of the channel layer 24 may be intrinsic polysilicon.
In step S13, a gate layer material is deposited along the channel hole 13 on top of the NAND string 14, forming a channel hole plug 15.
Preferably, the specific step of forming the trench hole plug 15 includes:
etching back the NAND string 14 along the channel hole 13 to form a recess 40, as shown in fig. 2A;
a gate layer material is deposited in the recess 40 to form the via plug 15, as shown in fig. 2D.
Preferably, the specific step of etching the NAND string 14 back along the channel hole 13 includes:
the channel layer 24 is etched back along the channel hole 13 to form the recess 40, as shown in fig. 2A. For example, the channel layer 24 may be etched back along the channel hole 13 using a dry etching process or a wet etching process to form the recess 40.
Preferably, the step of depositing the gate layer material in the recess 40 includes:
a conductive bonding material is deposited along the recess 40 on the sidewall surface of the tunneling layer 23 and the top of the channel layer 24 to form a bonding layer 25, as shown in fig. 2C.
And depositing a gate layer material on the surface of the bonding layer 25 along the groove 40 to form the channel hole plug 15.
Specifically, the conductive bonding material is titanium nitride; the specific steps of depositing a conductive adhesive material along the recess 40 on the sidewall surface of the tunneling layer 23 and the top of the channel layer 24 include:
and depositing titanium nitride on the surface of the side wall of the tunneling layer 23 and the top of the channel layer 24 by using an atomic layer deposition process to form the bonding layer 25.
Preferably, the method further comprises the following steps before forming the bonding layer 25:
a conductive material is deposited on top of the channel layer 24 along the recess 40 to form a conductive layer 26, as shown in fig. 2B.
Preferably, the conductive material is titanium; the specific steps of depositing a conductive material on top of the channel layer 24 along the recess 40 include:
the titanium is deposited on top of the channel layer 24 using a chemical vapor deposition process to form the conductive layer 26 of titanium silicide material. Specifically, titanium is deposited on top of the channel layer 24 using a chemical deposition process, and the deposited titanium reacts with the polysilicon material forming the channel layer 24 to form the titanium silicide material on top of the channel layer 24.
Preferably, the stacked structure comprises a core area I and a step area II arranged around the core area I; the following steps are further included after forming the trench plug 15 in the trench hole 13:
forming a dielectric layer covering the stacked structure;
and etching the dielectric layer, forming a first contact hole 16 penetrating to the channel hole plug 15 in the core region I, and simultaneously forming a second contact hole 17 penetrating to the surface of the gate layer 11 in the stacked structure in the step region II.
Specifically, the etch stop layer of the first contact plug hole 16 corresponding to the channel hole 13 is the channel hole plug 15, and the etch stop layer of the second contact plug hole 17 corresponding to the step region is the gate layer 11, and meanwhile, since the channel hole plug 15 and the gate layer 11 are made of the same material and have the same etch selectivity, the channel hole plug and the gate layer can be simultaneously formed in the same etch process, so as to simplify the three-dimensional memory manufacturing process.
Furthermore, the present embodiment further provides a three-dimensional memory, and the structure of the three-dimensional memory provided by the present embodiment is shown in fig. 3, and fig. 4 is a schematic structural diagram of a channel hole in the present embodiment.
As shown in fig. 3 and 4, the three-dimensional memory provided by the present embodiment includes: a substrate 10 having a stacked structure and a channel hole 13 penetrating the stacked structure in a direction perpendicular to the substrate 10, the stacked structure including a plurality of gate layers 11 sequentially arranged in the direction perpendicular to the substrate 10; a NAND string 14 covering a sidewall surface of the channel hole 13; and a channel hole plug 15 located in the channel hole 13, wherein the top of the NAND string 14 is electrically connected to the channel hole plug 15, and the material of the channel hole plug 15 is the same as that of the gate layer 11. Preferably, the three-dimensional memory is a 3DNAND memory.
Specifically, the stacked structure includes gate layers 11 and interlayer insulating layers 12 alternately stacked in a direction perpendicular to the substrate 10. The number of stacked layers of the stacked structure may be 32, 64 or other layers, and can be set by those skilled in the art according to actual needs. Generally, the more the number of stacked layers of a stacked structure, the higher the integration of the three-dimensional memory. The material of the gate layer 11 is preferably a metal material, such as tungsten. The material of the interlayer insulating layer 12 may be an oxide material.
The stacked structure includes a core region i and a step region ii provided around the core region i, and the channel hole 13 is located in the core region i. The step area II comprises a plurality of layers of steps. In the stacked structure, an adjacent one of the interlayer insulators 12 and one of the gate layers 11 form an insulator/gate layer pair. The step region ii includes a plurality of steps arranged in a direction perpendicular to the substrate 10, each step has one or more pairs of insulator/gate layers, and the pair of insulator/gate layers in the lower step protrudes from the pair of insulator/gate layers in the upper step in a horizontal direction.
With the three-dimensional memory structure provided by the present embodiment, in the subsequent etching process of the contact plug hole, the etch stop layer of the first contact plug hole 16 corresponding to the channel hole 13 is the channel hole plug 15, and the etch stop layer of the second contact plug hole 17 corresponding to the step region is the gate layer 11, and meanwhile, since the channel hole plug 15 and the gate layer 11 are made of the same material and have the same etch selectivity, the etching process of the first contact plug hole 16 and the etching process of the second contact plug hole 17 can be integrated into one, so that the manufacturing process of the three-dimensional memory is simplified, the manufacturing cost of the three-dimensional memory is reduced, the structure of the channel hole in the three-dimensional memory is not damaged, and the performance of the three-dimensional memory is effectively improved.
Preferably, the material of the channel hole plug 15 is tungsten. Since the material of the gate layer 11 in the three-dimensional memory is usually tungsten, the material of the trench hole plug 15 is also tungsten.
Preferably, in a radial direction along the channel hole 13, the NAND string 14 includes a barrier layer 21, a charge trap layer 22, a tunneling layer 23, and a channel layer 24 sequentially stacked on a sidewall surface of the channel hole 13; the channel hole plugs 15 are stacked on the surface of the channel layer 24 in a direction perpendicular to the substrate 10.
The material of the barrier layer 21 may be silicon oxide and/or silicon oxynitride; the charge trapping layer 22 may be a single layer or multiple layers of silicon nitride and/or silicon oxynitride; the tunneling layer 23 may be made of silicon oxide and/or silicon oxynitride; the material of the channel layer 24 may be intrinsic polysilicon.
Preferably, the trench hole plug 15 covers a sidewall surface of the tunneling layer 23. Specifically, the channel hole plug 15 is located in a region surrounded by the sidewall surface of the tunneling layer 23 and the top of the channel layer 24, so as to reduce the resistance in the channel hole 13.
Preferably, the three-dimensional memory further comprises: and an adhesive layer 25 covering the sidewall surface of the tunneling layer 23 and the top of the channel layer 24 for electrically connecting the channel plug 15 and the NAND string 14. More preferably, the material of the bonding layer 25 is titanium nitride.
Since the channel hole plug 15 is made of the same material as the gate layer 11 (e.g., tungsten), and has poor adhesion to the tunneling layer 23 and the channel layer 24, in order to enhance the electrical connection between the channel hole plug 15 and the NAND string 14, the adhesion layer 25 is disposed between the channel hole plug 15 and the NAND string 14. Moreover, when the channel hole plug 15 is formed by a chemical vapor deposition process, the NAND string 14 may be damaged by a reaction gas (e.g., fluorine-containing gas) used, and thus, the NAND string 14 may be protected by the adhesive layer 25.
Preferably, the thickness of the adhesive layer 25 is 3nm to 6 nm. More preferably, the thickness of the adhesive layer 25 is 4 nm. The bonding layer 25 may be formed using an atomic layer deposition process.
Preferably, the three-dimensional memory further comprises: a conductive layer 26 between the top of the channel layer 24 and the channel hole plug 15 for reducing resistance within the channel hole 13. Preferably, the material of the conductive layer is titanium silicide. Specifically, the conductive layer 26 is disposed between the adhesive layer 25 and the channel layer 24, for reducing the contact resistance of the adhesive layer 25 and the channel layer 24. The conductive layer 26 may be formed using a chemical vapor deposition process.
In the method for manufacturing the three-dimensional memory provided by the embodiment, the trench hole plug made of the same material as the gate layer is used as the connecting plug in the trench hole in the three-dimensional memory, and compared with the conventional polysilicon plug or amorphous silicon plug, the etching selectivity of the trench hole plug is close to that of the gate layer made of the same metal material in the three-dimensional memory, so that the etching process of the step region contact plug hole and the etching process of the trench hole region contact plug hole can be combined into a whole, the manufacturing steps of the three-dimensional memory are simplified, the manufacturing cost of the three-dimensional memory is reduced, the damage to the side wall of the trench hole in the etching process of the contact plug hole in the trench region is avoided, and the performance of the three-dimensional memory is remarkably improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. A method of fabricating a three-dimensional memory, comprising the steps of:
providing a substrate, wherein the substrate is provided with a stacked structure and a channel hole penetrating through the stacked structure along the direction vertical to the substrate, and the stacked structure comprises a plurality of gate layers which are sequentially arranged along the direction vertical to the substrate;
forming a NAND string on a sidewall surface of the channel hole;
and depositing a gate layer material on the top of the NAND string along the channel hole to form a channel hole plug.
2. The method of claim 1, wherein the step of forming a NAND string on the sidewall surface of the channel hole comprises:
forming a blocking layer on the surface of the side wall of the channel hole;
forming a charge trapping layer on the surface of the barrier layer;
forming a tunneling layer on the surface of the charge trapping layer;
and forming a channel layer on the surface of the tunneling layer.
3. The method of claim 2, wherein the step of forming the trench via plug comprises:
etching the NAND string back along the channel hole to form a groove;
and depositing a grid layer material in the groove to form the channel hole plug.
4. The method of claim 3, wherein etching the NAND string back along the channel hole comprises:
and etching the channel layer along the channel hole back to form the groove.
5. The method of claim 4, wherein the step of depositing the gate layer material in the recess comprises:
depositing a conductive bonding material on the surface of the side wall of the tunneling layer and the top of the channel layer along the groove to form a bonding layer;
and depositing a gate layer material on the surface of the bonding layer along the groove to form the channel hole plug.
6. The method of claim 5, further comprising the step of, prior to forming the bonding layer:
and depositing a conductive material on the top of the channel layer along the groove to form a conductive layer.
7. The method of claim 5, wherein the conductive bonding material is titanium nitride; the specific steps of depositing a conductive bonding material along the recess on the sidewall surface of the tunneling layer and the top of the channel layer include:
and depositing titanium nitride on the surface of the side wall of the tunneling layer and the top of the channel layer by adopting an atomic layer deposition process to form the bonding layer.
8. The method of manufacturing a three-dimensional memory according to claim 6, wherein the conductive material is titanium; the specific steps of depositing a conductive material on top of the channel layer along the recess include: and depositing the titanium on the top of the channel layer by adopting a chemical vapor deposition process, wherein the deposited titanium reacts with a polycrystalline silicon material forming the channel layer to form a conducting layer made of a titanium silicide material.
9. The method of claim 1, wherein the stacked structure comprises a core region and a step region disposed around the core region; the method also comprises the following steps after the channel hole plug is formed:
forming a dielectric layer covering the stacked structure;
and etching the dielectric layer, forming a first contact hole penetrating to the channel hole plug in the core region, and simultaneously forming a second contact hole penetrating to the surface of the grid layer in the step region.
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