CN107994029B - Preparation method of 3D NAND flash memory adopting novel trench hole electric connection layer material and flash memory - Google Patents
Preparation method of 3D NAND flash memory adopting novel trench hole electric connection layer material and flash memory Download PDFInfo
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- CN107994029B CN107994029B CN201711138109.1A CN201711138109A CN107994029B CN 107994029 B CN107994029 B CN 107994029B CN 201711138109 A CN201711138109 A CN 201711138109A CN 107994029 B CN107994029 B CN 107994029B
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The invention provides a preparation method of a 3D NAND flash memory adopting a novel trench hole electric connection layer material and a flash memory, wherein the method comprises the following steps: depositing a substrate stack on a substrate; etching the stacked structure to form a channel hole, wherein the channel hole is communicated with the substrate and forms a silicon groove with a certain depth; depositing a graphene epitaxial layer in the silicon groove; forming a channel hole side wall stacking structure; etching the stacked structure; and depositing a graphene connecting layer, wherein the graphene connecting layer connects the graphene layer in the channel hole side wall stacking structure with the graphene epitaxial layer. Since the thin graphene thin film has very high mobility and very high mechanical strength, it helps to increase the read current and improve the channel pore structure stability.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a channel hole structure in a 3D NAND flash memory structure and a preparation method thereof.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to solve the difficulties encountered by flat flash memories and to maximize the lower production cost of a unit cell, various three-dimensional (3D) flash memory structures, such as 3D NOR (3D NOR) flash memory and 3D NAND (3D NAND) flash memory, have come into force. At present, in the development process of 3D NAND, with the increase of the number of stacked layers, higher requirements are put forward on the preparation processes such as etching, deposition, and the like.
Currently, a process for preparing a channel hole sidewall stack structure of a 3D NAND flash memory includes:
s1: depositing a stacking structure on the side wall of the channel hole and the surface of the silicon epitaxial layer, wherein the stacking structure on the side wall of the channel hole comprises an oxide-nitride-oxide (ONO) structure of a blocking layer, a storage layer and a tunneling layer and an external polysilicon and oxide layer;
s2: etching the channel hole side wall stacking structure, specifically, etching downwards along the bottom wall of the channel hole side wall stacking structure, leading to the silicon epitaxial layer and forming a second silicon groove with a certain depth; simultaneously removing the channel hole side wall stacking structure covering the top surface of the substrate stacking structure to expose the top surface of the substrate stacking structure, and removing the oxide layer on the outermost side of the channel hole side wall stacking structure
S3: and depositing a polycrystalline silicon connecting layer, and depositing a polycrystalline silicon layer on the side wall of the channel hole side wall stacking structure and the surface of the second silicon groove so as to communicate the polycrystalline silicon layer in the channel hole side wall stacking structure with the silicon epitaxial layer.
Therefore, the connecting layer material in the prior art adopts polysilicon; however, as the number of stacked layers increases, a read current (read current) is being seriously critical, and the use of polysilicon as an electrical connection layer limits the conductivity and increases the resistivity of a channel, so that the channel hole performance is difficult to improve due to the defect.
Therefore, for 3D NAND flash memories, especially when the number of stacked layers is high, how to find an alternative material for the electrical connection layer has been a direction of intense research by those skilled in the art.
Disclosure of Invention
The invention aims to provide a preparation method of a 3D NAND flash memory adopting a novel channel hole electric connection layer material and a flash memory, wherein the problems in the prior art are solved by adopting a graphene material to replace polycrystalline silicon as the channel hole electric connection layer material; the electrical performance of the 3D NAND flash memory is improved.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a preparation method of a 3D NAND flash memory adopting a novel trench hole electric connection layer material comprises the following steps:
providing a substrate;
depositing a substrate stack on the substrate;
etching the substrate stacking structure, specifically, etching the stacking structure to form a channel hole, wherein the channel hole is communicated with the substrate and forms a silicon groove with a certain depth;
depositing a graphene epitaxial layer in the silicon groove;
forming a channel hole side wall stacking structure;
etching the stacked structure;
and depositing a graphene connecting layer, wherein the graphene connecting layer connects the graphene layer in the channel hole side wall stacking structure with the graphene epitaxial layer.
Further, a plurality of interlaminar dielectric layers and sacrificial dielectric layers or control gate layers which are stacked in a staggered mode are formed on the surface of the substrate, and the sacrificial dielectric layers or the control gate layers are formed between the adjacent interlaminar dielectric layers; the interlayer dielectric layer is an oxide, the sacrificial dielectric layer is a nitride, and the control gate layer is a polycrystalline silicon layer or a graphene layer.
Further, after the graphene epitaxial layer is formed, a channel hole side wall stacking structure is formed, specifically, a stacking structure is deposited on the side wall of the channel hole and the surface of the graphene epitaxial layer, the channel hole side wall stacking structure comprises a blocking layer, a storage layer and an oxide-nitride-oxide (ONO) structure of a tunneling layer, a graphene layer is formed outside an outer layer of oxide, and an oxide layer is deposited outside the graphene layer.
Further, etching the channel hole side wall stacking structure, specifically, etching downwards along the bottom wall of the channel hole side wall stacking structure, leading to the graphene epitaxial layer and forming a groove with a certain depth; and simultaneously removing the channel hole side wall stacking structure covering the top surface of the substrate stacking structure to expose the top surface of the substrate stacking structure, and removing the oxide layer on the outermost side of the channel hole side wall stacking structure.
And further, depositing a graphene connecting layer, and depositing graphene layers on the side wall of the channel hole side wall stacking structure and the surface of the groove so as to communicate the graphene layers in the channel hole side wall stacking structure with the graphene epitaxial layer.
Further, filling the plug, specifically, depositing silicon nitride inside the graphene connection layer as a trench hole filling plug.
Further, the graphene deposition adopts an inductively coupled plasma-chemical vapor deposition (ICP-CVD) process, and uses acetylene (C2H2) as a raw material.
A3D NAND flash memory adopting a novel trench hole electric connection layer material is prepared by the method.
Compared with the prior art, the invention has the following beneficial effects:
first, graphene has higher mobility than polysilicon, thus contributing to an increase in read current, which may provide better electrical performance.
Second, graphene has very high mechanical strength, thus contributing to improved stability of the channel pore structure.
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Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a schematic view of a 3D NAND flash memory structure using a novel trench hole electrical connection layer material according to the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a preparation method of a 3D NAND flash memory adopting a novel trench hole electric connection layer material, which comprises the following steps with reference to FIG. 1:
s100, providing a liner 100;
s200, depositing a substrate stacking structure on the substrate 100; a plurality of layers of interlaminar dielectric layers and control gate layers which are stacked in a staggered mode are formed on the surface of the substrate, and the control gate layers are formed between the adjacent interlaminar dielectric layers; the interlayer dielectric layer is an oxide 200, and the control gate layer is a polysilicon layer 300.
S300, etching the substrate stack structure, specifically, etching the interlayer dielectric layer oxide 200 and the polysilicon control gate layer 300 to form a channel hole, where the channel hole is communicated to the substrate and forms a silicon trench (not shown) with a certain depth;
s400, depositing a graphene epitaxial layer 400 in the silicon groove;
s500, forming a trench sidewall stacking structure, specifically, depositing a stacking structure on the sidewall of the trench and the surface of the graphene epitaxial layer 400, where the trench sidewall stacking structure includes an oxide-nitride-oxide (ONO) structure 500 of a blocking layer, a storage layer, and a tunneling layer, then depositing a graphene layer on the outer surface of the outer layer oxide, and then depositing an oxide layer on the outer surface.
S600, etching the channel hole side wall stacking structure, specifically, etching downwards along the bottom wall of the channel hole side wall stacking structure, and leading to the graphene epitaxial layer to form a groove with a certain depth; and simultaneously removing the channel hole side wall stacking structure covering the top surface of the substrate stacking structure to expose the top surface of the substrate stacking structure, and removing the oxide layer on the outermost side of the channel hole side wall stacking structure.
S700, depositing a graphene connecting layer 600, and depositing graphene layers on the side wall of the channel hole side wall stacking structure and the surface of the groove so as to communicate the graphene layers in the channel hole side wall stacking structure with the graphene epitaxial layer
And S800, filling the plug 700, specifically, depositing silicon nitride inside the graphene connection layer to serve as a channel hole filling plug.
In the above process, the graphene deposition is a process of inductively coupled plasma-chemical vapor deposition (ICP-CVD), and acetylene (C2H2) is used as a raw material.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (8)
1. A preparation method of a 3D NAND flash memory adopting a novel trench hole electric connection layer material is characterized by comprising the following steps:
providing a substrate;
depositing a substrate stack on the substrate;
etching the substrate stack structure to form a channel hole, wherein the channel hole is communicated with the substrate and forms a silicon groove with a certain depth;
depositing a graphene epitaxial layer in the silicon groove;
forming a channel hole side wall stacking structure;
etching the channel hole side wall stacking structure;
and depositing a graphene connecting layer, wherein the graphene connecting layer connects the graphene layer in the channel hole side wall stacking structure with the graphene epitaxial layer.
2. The method according to claim 1, wherein a plurality of alternately stacked interlayer dielectric layers and sacrificial dielectric layers or a plurality of alternately stacked interlayer dielectric layers and control gate layers are formed on the surface of the substrate, and the sacrificial dielectric layers or the control gate layers are formed between adjacent interlayer dielectric layers; the interlayer dielectric layer is an oxide, the sacrificial dielectric layer is a nitride, and the control gate layer is a polycrystalline silicon layer or a graphene layer.
3. The method of claim 2, further comprising forming a channel hole sidewall stack structure after forming the graphene epitaxial layer, in particular, depositing a stack structure on a sidewall of the channel hole and a surface of the graphene epitaxial layer, the channel hole sidewall stack structure comprising an oxide-nitride-oxide structure (ONO) of a barrier layer, a storage layer, and a tunneling layer, then forming a graphene layer outside an outer oxide, and then depositing an oxide layer outside.
4. The preparation method according to claim 3, wherein the trench hole sidewall stack structure is etched, specifically, etched downwards along a bottom wall of the trench hole sidewall stack structure, and reaches the graphene epitaxial layer to form a groove with a certain depth; and simultaneously removing the channel hole side wall stacking structure covering the top surface of the substrate stacking structure to expose the top surface of the substrate stacking structure, and removing the oxide layer on the outermost side of the channel hole side wall stacking structure.
5. The preparation method of claim 4, wherein a graphene connection layer is deposited, and a graphene layer is deposited on the side wall of the channel hole side wall stacked structure and the surface of the groove to connect the graphene layer in the channel hole side wall stacked structure and the graphene epitaxial layer.
6. The method according to claim 4, wherein the plug is filled, in particular, silicon nitride is deposited inside the graphene connection layer as a trench hole filling plug.
7. The method of any one of claims 1-5, wherein depositing graphene is by inductively coupled plasma-ionizationChemical vapor deposition (ICP-CVD) process with acetylene (C)2H2) Is used as a raw material.
8. A 3D NAND flash memory using a novel trench hole electrical connection layer material, wherein the electrical connection layer material is graphene, and the flash memory is prepared by the method of any one of claims 1 to 6.
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| CN103680611A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | 3D (three-dimensional) NAND memory and manufacturing method thereof |
| CN106129010A (en) * | 2016-09-07 | 2016-11-16 | 武汉新芯集成电路制造有限公司 | A kind of method forming 3D nand flash memory |
| CN107017258A (en) * | 2016-01-28 | 2017-08-04 | 三星电子株式会社 | IC apparatus and its manufacture method including vertical memory device |
| CN107293550A (en) * | 2014-01-17 | 2017-10-24 | 旺宏电子股份有限公司 | Memory component and preparation method thereof |
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| JP5694272B2 (en) * | 2012-10-25 | 2015-04-01 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| US9397110B2 (en) * | 2014-05-21 | 2016-07-19 | Macronix International Co., Ltd. | 3D independent double gate flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103680611A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | 3D (three-dimensional) NAND memory and manufacturing method thereof |
| CN107293550A (en) * | 2014-01-17 | 2017-10-24 | 旺宏电子股份有限公司 | Memory component and preparation method thereof |
| CN107017258A (en) * | 2016-01-28 | 2017-08-04 | 三星电子株式会社 | IC apparatus and its manufacture method including vertical memory device |
| CN106129010A (en) * | 2016-09-07 | 2016-11-16 | 武汉新芯集成电路制造有限公司 | A kind of method forming 3D nand flash memory |
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