CN108493189A - 3D NAND detection structures and forming method thereof - Google Patents
3D NAND detection structures and forming method thereof Download PDFInfo
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- CN108493189A CN108493189A CN201810239039.7A CN201810239039A CN108493189A CN 108493189 A CN108493189 A CN 108493189A CN 201810239039 A CN201810239039 A CN 201810239039A CN 108493189 A CN108493189 A CN 108493189A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2637—Circuits therefor for testing other individual devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
The present invention relates to a kind of 3D NAND test structures and forming method thereof, which includes：Semiconductor substrate is provided, the semiconductor substrate surface is formed with stacked structure and the dielectric layer around the stacked structure, the stacked structure is stacked by sacrificial layer and separation layer, including nucleus and the staircase areas around the nucleus, and the dielectric layer covers the stacked structure；Form the gate via to semiconductor substrate surface through the nucleus；The sacrificial layer is removed, forms opening between the separation layer；It forms the control grid of the full opening of filling and the first metal plug of the full gate via of filling, first metal plug is electrically connected with the control grid of each layer.The 3D NAND test structures that the above method is formed are connected short circuit between all control grids by the first metal plug, to can only be tested all storage units by the first metal plug.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to a kind of 3D NAND detection structures and forming method thereof.
Background technology
With the continuous development of 3D NAND technologies, the storage organization of 3D NAND more than 64 layers, storage array chip and
Concurrent development helps to further increase development efficiency peripheral cmos circuit chip simultaneously.Even if the storage array chip in different generations
Similar cmos circuit chip can also be shared to obtain higher memory capacity and density of memory cells.
Other than with the relevant basic research of technique, in the case where technology node reaches a higher generation, how quickly
It is extremely important to be read out test.Currently, the reading detection process of 3D nand memories is broadly divided into three phases：First rank
Section is that the switching current of storage unit is read by semi-artificial nano-probe；Second stage is by fabrication parameter testing
Resolution chart carry out functional memory cell detection；Phase III is to obtain block function and yield detection.
For the three phases of above-mentioned reading detection process, no matter which kind of method is used, is required for well region, control grid
And/or stepped region plug, raceway groove through-hole structure and array common source configuration are connected to test lead by metal interconnection structure.
In the prior art, after storage organization is formed completely, it is also necessary to by electrical path all in back-end process, packet
It includes：After well region, control grid and/or stepped region plug, raceway groove through-hole structure and array common source configuration etc. are completely formed
It can be tested, and it also requires forming metal interconnecting wires at top with connecting test circuit.Therefore, it is impossible to quickly in time
Ground obtains the testing result of 3D NAND, extends 3D NAND exploitations and the period is released in market.
Therefore, it is necessary to design a kind of 3D NAND detection structures, quickly detection is realized.
Invention content
The technical problem to be solved by the invention is to provide a kind of 3D NAND detection structures and forming method thereof, to realize
The early stage of 3D NAND detections is quickly detected.
To solve the above problems, the present invention proposes a kind of forming method of 3D NAND detection structures, including：Offer is partly led
Body substrate, the semiconductor substrate surface are formed with stacked structure and the dielectric layer around the stacked structure, the stacking knot
Structure is stacked by sacrificial layer and separation layer, including nucleus and the staircase areas around the nucleus, the medium
Layer covers the stacked structure；Form the gate via to the semiconductor substrate surface through the nucleus；Removal institute
Sacrificial layer is stated, forms opening between the separation layer；Control grid and the filling for forming the full opening of filling are full described
First metal plug of gate via, first metal plug are electrically connected with the control grid of each layer.
Optionally, the forming method further includes：Form the interlayer dielectric layer for covering the dielectric layer；It is situated between in the interlayer
The metallic vias positioned at the first metal plug top surface is formed in matter layer, for carrying out nano-probe test.
Optionally, the forming method of the control grid and first metal plug includes：It is described opening and it is described
Deposition of gate material in gate via, the full opening of the grid material filling and the gate via；It is formed described in being located at
The control grid in opening and first metal plug in the gate via.
Optionally, it while forming the gate via, is formed through the nucleus to semiconductor substrate surface
Common source groove；After forming the control grid, first metal plug, the full common source groove of filling is formed
Common source configuration.
Optionally, the forming method further includes：After removing the sacrificial layer, in the gate via and described total
Doped region is formed in the semiconductor substrate of source electrode channel bottom and is located at the gate via and the common source groove
The oxide layer of the semiconductor substrate surface of bottom.
Optionally, the semiconductor substrate surface is also formed with the peripheral circuit positioned at stacked structure periphery, described
Peripheral circuit is covered by the dielectric layer；The forming method further includes：It is formed through the dielectric layer to the peripheral circuit
Contact area the second metal plug.
Optionally, there is the channel structure through the nucleus to the semiconductor substrate in the stacked structure.
Technical scheme of the present invention also provides a kind of 3D NAND detection structures, including：Semiconductor substrate, the semiconductor
Substrate surface is formed with storage stack structure and the dielectric layer around the storage stack structure, and the storage stack structure is by controlling
Grid and separation layer processed stack, including nucleus and the staircase areas around the nucleus, the dielectric layer cover
Cover the storage stack structure；Through the first metal plug of the nucleus to the semiconductor substrate surface, described
One metal plug is electrically connected with the control grid of each layer.
Optionally, further include：Cover the interlayer dielectric layer of the dielectric layer；Being located in the interlayer dielectric layer is described
The metallic vias of first metal plug top surface, for carrying out nano-probe test.
Optionally, further include：Through the common source configuration of the nucleus to semiconductor substrate surface.
Optionally, further include：The semiconductor positioned at first metal plug and the common source configuration bottom serves as a contrast
Doped region in bottom and the oxygen positioned at the gate via and the semiconductor substrate surface of the common source channel bottom
Change layer.
Optionally, the semiconductor substrate surface is also formed with the peripheral circuit positioned at the storage stack structure peripheral,
The peripheral circuit is covered by the dielectric layer；Further include：Through the contact area of the dielectric layer to the peripheral circuit
Second metal plug.
Optionally, there is the channel junction through the nucleus to the semiconductor substrate in the storage stack structure
Structure.
In the forming method of the 3D NAND detection structures of the present invention, in the nucleus for the stacked structure for forming 3D NAND
Form the gate via through nucleus；It is formed simultaneously control grid and fills the first metal plug of gate via, it is described
First metal plug is connected to all control grids of storage array.It can be to all storages by first metal plug
Unit is detected, without forming the metal plug for connecting each layer and controlling grid in staircase areas, after forming upper layer
Detection circuit and resolution chart are held, processing step can be simplified, saved time and cost.Also, forming step with it is existing
The technological process of 3D nand memories is compatible with.
There is the first metal for being through to semiconductor substrate surface in the nucleus of the 3D NAND detection structures of the present invention
Plug, all control grids are connected by the first metal plug short circuit, can be realized to all storage units in early stage
Detection, the especially detection of switching current can be into before the storage stack superstructure forms back-end metal layer
Row detection, can greatly shorten the performance detection period of 3D NAND, and cost-effective.
Description of the drawings
Fig. 1 is the flow diagram of the forming method of the 3D NAND detection structures of the embodiment of the invention；
Fig. 2 to Fig. 8 is the structural representation of the forming process of the 3D NAND detection structures of the embodiment of the invention
Figure.
Specific implementation mode
Below in conjunction with the accompanying drawings to a kind of specific embodiment party of 3D NAND detection structures provided by the invention and forming method thereof
Formula elaborates.
Referring to FIG. 1, the structural representation of the forming method for the 3D NAND detection structures of a specific mode of the invention
Figure.
The forming method of the 3D NAND detection structures includes the following steps：
Step S101：Semiconductor substrate is provided, the semiconductor substrate surface is formed with stacked structure and surrounds the heap
The dielectric layer of stack structure, the stacked structure are stacked by sacrificial layer and separation layer, including nucleus and surround the core
The staircase areas in heart district domain, the dielectric layer cover the stacked structure.
Step S102：Form the gate via to the semiconductor substrate surface through the nucleus；Described in removal
Sacrificial layer forms opening between the separation layer.
Step S103：Form the control grid of the full opening of filling and the first metal of the full gate via of filling
Plug, first metal plug are electrically connected with the control grid of each layer.
It is please referred to Fig.2 below to Fig. 8, is the forming process of the 3D NAND detection structures of the embodiment of the invention
Structural schematic diagram.
Referring to FIG. 2, providing semiconductor substrate 100,100 surface of the semiconductor substrate is formed with 200 He of stacked structure
Around the dielectric layer 110 of the stacked structure 200, the stacked structure 200 stacked by sacrificial layer 2002 and separation layer 2001 and
At, including nucleus 220 and the staircase areas 210 around the nucleus 220, the dielectric layer 110 cover the heap
Stack structure 200.
Also there is the channel structure through the nucleus 220 to semiconductor substrate 100 in the stacked structure 200
201。
The semiconductor substrate 100 can be monocrystalline substrate, Ge substrates, SiGe substrate, SOI or GOI etc.；According to device
Actual demand, suitable semiconductor substrate 100 can be selected, be not limited thereto.It is described partly to lead in the specific implementation mode
Body substrate 100 is monocrystalline silicon wafer crystal.
It can be oxidation that 2002 material of sacrificial layer of the stacked structure 200, which can be silicon nitride, 2001 material of separation layer,
Silicon.The channel structure 201 includes the substrate epitaxial layer 2011 for being formed in raceway groove hole bottom and the raceway groove in raceway groove hole
Material layer 2012.In one example, the layer of channel material 2012 may include function side wall and covering function side wall surface
Polysilicon layer and raceway groove dielectric layer positioned at the polysilicon layer surface and the full raceway groove hole of filling.The function side wall is O-N-O
The lamination layer structure of (oxide-nitride-oxide).However, the structure of the layer of channel material 2012 and non-present invention
Limitation, such as polysilicon layer can be solid construction.
In the specific implementation mode, the stacked structure 200 includes two straton stacked structures, respectively bottom stacked structure
200a and upper layer stacked structure 200b, passes through dielectric layer between the bottom stacked structure 200a and upper layer stacked structure 200b
110 isolation；The channel structure 201 includes the bottom channel structure being located in the bottom stacked structure 200a and is located at described
Top-layer channel structure in the stacked structure 200b of upper layer.Stacked structure 200 can be improved by forming multiple sub- stacked structures
Whole height improves density of memory cells.
Specifically, in the specific implementation mode, the forming method of the stacked structure 200 and dielectric layer 110 is included in half
100 surface of conductor substrate stacks gradually to form sacrificial layer 2002 and separation layer 2001, then by the sacrificial layer 2002 and isolation
The fringe region etching of layer 2001 into a ladder, forms bottom stacked structure 200a；Then described in the covering of deposition underlying dielectric layer
Bottom stacked structure 200a is simultaneously planarized；Bottom channel structure is formed in the bottom stacked structure 200a again；Again described
Bottom channel structure surface is covered spacer medium layer and then is formed using same method in the spacer medium layer surface
Layer heap stack structure 200b forms the top dielectric layer for covering the upper layer stacked structure 200b and stacks knot through the upper layer
The top-layer channel structure of structure 200b being connect with the bottom channel structure.The top-layer channel structure and bottom channel structure are whole
Body is as channel structure 201.The underlying dielectric layer, spacer medium layer and top dielectric layer are integrally used as dielectric layer 110.
In other specific implementation modes of the present invention, the stacked structure 200 can also only include that a straton stacks knot
The sub- stacked structure of structure or three layers or more.
Run through the dielectric layer 110 and staircase areas 210 to the insulated column of semiconductor substrate 100 referring to FIG. 3, being formed
202。
The forming method of the insulated column 202 includes：Etch the dielectric layer 110, staircase areas 210 to semiconductor substrate
100 surfaces form pseudo- through-hole；Insulating dielectric materials are filled in the pseudo- through-hole, and are planarized, is formed and is located at the puppet
Insulated column 202 in through-hole.The insulated column 202, can be to the separation layer during subsequently removal sacrificial layer 2002
2001 play a supporting role.
In the specific implementation mode, the material of the insulated column 202 can be silica.Due to the stacked structure 200
Height it is higher so that the depth of the pseudo- through-hole of formation is larger, in order to improve the insulating dielectric materials in the pseudo- through-hole
Filling quality, atom layer deposition process may be used and fill insulating dielectric materials in the pseudo- through-hole.
Referring to FIG. 4, forming the gate via 213 through the nucleus 220 to 100 surface of semiconductor substrate.
In the specific mode, while forming gate via 213, is also formed and run through the nucleus
220 to 100 surface of semiconductor substrate common source groove 203.
Specifically, the method for forming the common source groove 203 includes：It is formed in the dielectric layer and stacked structure surface
Graphical hard mask layer, the graphical hard mask layer define the common source groove 203 and gate via 213 position and
Size；The stacked structure 200 is sequentially etched to semiconductor substrate by mask of the graphical hard mask layer, forms the grid
Pole through-hole 213 and common source groove 203.The figure of gate via 213 defined in the graphical hard mask layer can in shape
During 3D nand memories, the mask pattern for defining top layer selection grid through-hole is consistent, with existing 3D nand memories
Process compatible can be cost-effective without additional light shield.
Referring to FIG. 5, remove the sacrificial layer 2002 along the common source groove 203 and gate via 213, it is described every
Opening 204 is formed between absciss layer 2001.
Wet-etching technology may be used and remove the sacrificial layer 2002, specifically, what the wet-etching technology used
Etching solution can be hot phosphoric acid solution.
After removing the sacrificial layer 2002, the semiconductor in 213 bottom of the common source groove 203 and gate via
Source dopant region 205 is formed in substrate 100；And the semiconductor substrate in 213 bottom of the common source groove 203 and gate via
100 surfaces form oxide layer 206.
Ion implanting is carried out at the same time to the bottom of the common source groove 203 and gate via 213, forms source dopant region
205.The ion implanting uses n-type doping ion P.
After forming the source dopant region 205, to partly leading for 213 bottom of the common source groove 203 and gate via
100 surface of body substrate carries out oxidation processes, forms oxide layer 206.The oxidation processes can be moisture-generation process in situ or
The oxidation technologies such as person's thermal oxide.The oxide layer 206 is as the common source knot subsequently formed in the common source groove 203
Separation layer between structure, the first metal plug formed in gate via and the source dopant region 205.
Referring to FIG. 6, the deposition of gate material in the opening 204, gate via 213, the grid material filling is full
The opening 204 and gate via 213；Using the dielectric layer 110 as stop-layer, the grid material is planarized,
Form the control grid 301 being located in the opening 204 and the first metal plug 315 in the gate via 213.
In the specific implementation mode, metal may be used in the grid material, such as includes gold of the tungsten (W) as principal component
Belong to material.Atom layer deposition process may be used and deposit the grid material, to ensure the control grid 301 and the first metal
Plug 315 has higher deposition quality, avoids the problems such as cavity occur in control grid 301 and the first metal plug 315.
In other specific described modes, the grid material can also be other conductive materials such as polysilicon, aluminium (Al), silver-colored (Ag).
Before depositing the grid material, can also first it sink in the opening 204 and 213 inner wall surface of gate via
Product one layer of titanium nitride (TiN) adhesion layer, with improve subsequent gate material with opening 204 inner walls and 213 inner wall of gate via it
Between adhesion property.
The control grid 301 is stacked with to form storage stack structure with separation layer 2001, including upper layer storage stack
Structure 200d and bottom storage stack structure 200c.
In the specific mode, the grid material fills the common source groove 203 simultaneously.Forming the control
After grid 301 and the first metal plug 315, removal is located at the grid material in the common source groove 203, then described total
Common source configuration is formed in source electrode groove 302, include positioned at 203 sidewall surfaces of common source groove insulation side wall 304 and fill out
Common source 305 full of the common source groove 203.
First metal plug 315 is electrically connected with the control grid 301 of each layer, therefore in detection process, passes through institute
All control grids 301 can be connected to simultaneously by stating the first metal plug 315, while be examined to all storage units
It surveys.
Referring to FIG. 7,100 surface of the semiconductor substrate is also formed with the periphery positioned at 200 periphery of the stacked structure
Circuit (not shown), the peripheral circuit are covered by the dielectric layer 110.After forming the common source configuration, shape
At the second metal plug 401 of the contact area through the dielectric layer 110 to peripheral circuit.
The method for forming second metal plug 401 includes：Pattern mask is formed on 110 surface of the dielectric layer
Layer, the Patterned masking layer define size and the position of the peripheral through holes in peripheral region；It is with the Patterned masking layer
Mask etches the dielectric layer 110, forms peripheral through holes；Metal material is filled in the peripheral through holes, and is carried out flat
Change, forms second metal plug 401.
Referring to FIG. 8, forming the interlayer dielectric layer 120 for covering the dielectric layer 110；In the interlayer dielectric layer 120
The metallic vias 501 positioned at 315 top surface of the first metal plug is formed, for carrying out nano-probe test.This is specific
In embodiment, be formed simultaneously multiple metallic vias 501 (as shown in Figure 8), respectively with the first metal plug 315, the second metal
Plug 401, channel structure 201, common source 305 contact, but this be it is exemplary and and it is unrestricted.On the contrary, according to survey
Examination need, can also only be formed in the first metal plug 315, the second metal plug 401, channel structure 201, common source 305
Any one or more structures contact metallic vias, and non-present invention limitation.
Subsequently during being detected, nano-probe can directly be connect with the metallic vias 501, no longer need to shape
At the back-end metal line or resolution chart on upper layer, processing step can be simplified, saved time and cost.
In the forming method of the 3D NAND detection structures of the present invention, in the nucleus for the stacked structure for forming 3D NAND
Form the gate via through nucleus；It is formed simultaneously control grid and fills the first metal plug of gate via, it is described
First metal plug is connected to the control grid of storage array.It can be to all storage units by first metal plug
It is detected.Without forming the metal plug for connecting each layer and controlling grid in staircase areas, examined without the rear end for forming upper layer
Slowdown monitoring circuit and resolution chart can simplify processing step, save time and cost.Also, forming step and existing 3D
The technological process of nand memory is compatible with.
The specific mode of the present invention, also provides a kind of 3D NAND detection structures.
Referring to FIG. 8, the 3D NAND detection structures include：Semiconductor substrate 100,100 surface of the semiconductor substrate
It is formed with storage stack structure and the dielectric layer 110 around the storage stack structure, the storage stack structure is by control gate
Pole 301 and separation layer 2001 stack, including nucleus 220 and the staircase areas 210 around the nucleus 220,
The dielectric layer 110 covers the storage stack structure.
In the specific mode, the storage stack structure includes two sub- storage stack structures, respectively bottom heap
Stack structure 200c and upper layer stacked structure 200d, passes through Jie between the bottom stacked structure 200c and upper layer stacked structure 200d
Matter layer 110 is isolated.In other specific described modes, the stacked structure can also only include a straton storage stack structure or
Three layers or more of sub- storage stack structure.Also have through the nucleus 220 to semiconductor in the storage stack structure
The channel structure 201 of substrate 100.In the specific implementation mode, the channel structure 201 includes being located at bottom storage stack structure
Bottom channel structure in 200c and the top-layer channel structure in the upper layer storage stack structure 200d.
The 3D NAND detection structures include the first gold medal to 100 surface of semiconductor substrate through the nucleus 220
Belong to plug 315, first metal plug 315 is electrically connected with the control grid 301 of each layer.Pass through first metal plug
315 can be detected all storage units.
The 3D NAND detection structures further include the common source to 100 surface of semiconductor substrate through the nucleus 220
Pole structure, the common source configuration include insulation side wall 304 and common source 305.
The 3D NAND detection structures further include running through the dielectric layer 110 and staircase areas 210 to semiconductor substrate
100 insulated column 202 plays a supporting role to the storage stack structure.
It is also mixed with source electrode in the semiconductor substrate 100 of 315 bottom of the common source configuration bottom and the first metal plug
Also there is oxygen between miscellaneous area 205 and 305 bottom of the common source and 315 bottom of the first metal plug and semiconductor substrate 100
Change layer 206.
Further, 100 surface of the semiconductor substrate is also formed with positioned at the periphery of the storage stack structure peripheral
Circuit, the peripheral circuit are covered by the dielectric layer 110；Further include：Through the contact of the dielectric layer 110 to peripheral circuit
Second metal plug 401 in region.
Further, further include：Cover the interlayer dielectric layer 120 of the dielectric layer 110；In the interlayer dielectric layer 120
The interior gold for being located at first metal plug 315, the second metal plug 401, channel structure 201,305 top surface of common source
Belong to via 501, for carrying out nano-probe test.Nano-probe can directly be connect with the metallic vias 501, is no longer needed to
The back-end metal line or resolution chart for forming upper layer, can simplify processing step, save time and cost.The specific embodiment party
In formula, there are multiple metallic vias 501 (as shown in Figure 8) in the interlayer dielectric layer 120, respectively with the first metal plug 315,
Second metal plug 401, channel structure 201, common source 305 contact, but this be it is exemplary and and it is unrestricted.On the contrary
Ground, can have according to test needs, in the interlayer dielectric layer 120 with the first metal plug 315, the second metal plug 401,
The metallic vias of any one or more structures contact in channel structure 201, common source 305, and the limitation of non-present invention.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (13)
1. a kind of forming method of 3D NAND detection structures, which is characterized in that including：
Semiconductor substrate is provided, the semiconductor substrate surface is formed with stacked structure and the medium around the stacked structure
Layer, the stacked structure is stacked by sacrificial layer and separation layer, including nucleus and the ladder around the nucleus
Region, the dielectric layer cover the stacked structure；
Form the gate via to the semiconductor substrate surface through the nucleus；
The sacrificial layer is removed, forms opening between the separation layer；
It forms the control grid of the full opening of filling and fills the first metal plug of the full gate via, described first
Metal plug is electrically connected with the control grid of each layer.
2. the forming method of 3D NAND detection structures according to claim 1, which is characterized in that the forming method is also
Including：Form the interlayer dielectric layer for covering the dielectric layer；It is formed in the interlayer dielectric layer and is inserted positioned at first metal
The metallic vias for filling in top surface, for carrying out nano-probe test.
3. the forming method of 3D NAND detection structures according to claim 1, which is characterized in that the control grid and
The forming method of first metal plug includes：The deposition of gate material in the opening and the gate via, the grid
The pole full opening of material filling and the gate via；Form the control grid being located in the opening and positioned at described
First metal plug in gate via.
4. the forming method of 3D NAND detection structures according to claim 1, which is characterized in that it is logical to form the grid
While hole, the common source groove to semiconductor substrate surface through the nucleus is formed；Formed the control grid,
After first metal plug, the common source configuration of the full common source groove of filling is formed.
5. the forming method of 3D NAND detection structures according to claim 4, which is characterized in that the forming method is also
Including：After removing the sacrificial layer, in the semiconductor substrate of the gate via and the common source channel bottom
Interior formation doped region and the oxygen positioned at the gate via and the semiconductor substrate surface of the common source channel bottom
Change layer.
6. the forming method of 3D NAND detection structures according to claim 1, which is characterized in that the semiconductor substrate
Surface is also formed with the peripheral circuit positioned at stacked structure periphery, and the peripheral circuit is covered by the dielectric layer；It is described
Forming method further includes：Form the second metal plug to the contact area of the peripheral circuit through the dielectric layer.
7. the forming method of 3D NAND detection structures according to claim 1, which is characterized in that in the stacked structure
With the channel structure through the nucleus to the semiconductor substrate.
8. a kind of 3D NAND detection structures, which is characterized in that including：
Semiconductor substrate, the semiconductor substrate surface are formed with storage stack structure and Jie around the storage stack structure
Matter layer, the storage stack structure are stacked by control grid and separation layer, including nucleus and surround the core space
The staircase areas in domain, the dielectric layer cover the storage stack structure；
Through the first metal plug of the nucleus to the semiconductor substrate surface, first metal plug and each layer
Control grid electrical connection.
9. 3D NAND detection structures according to claim 8, which is characterized in that further include：Cover the layer of the dielectric layer
Between dielectric layer；The metallic vias positioned at the first metal plug top surface in the interlayer dielectric layer, for carrying out
Nano-probe is tested.
10. 3D NAND detection structures according to claim 8, which is characterized in that further include：Through the nucleus
To the common source configuration of semiconductor substrate surface.
11. 3D NAND detection structures according to claim 10, which is characterized in that further include：Positioned at first metal
Doped region in the semiconductor substrate of plug and the common source configuration bottom and positioned at the gate via and described
The oxide layer of the semiconductor substrate surface of common source channel bottom.
12. 3D NAND detection structures according to claim 8, which is characterized in that the semiconductor substrate surface is also formed
There are the peripheral circuit positioned at the storage stack structure peripheral, the peripheral circuit to be covered by the dielectric layer；Further include：Run through
The dielectric layer to the contact area of the peripheral circuit the second metal plug.
13. 3D NAND detection structures according to claim 8, which is characterized in that have in the storage stack structure and pass through
The nucleus is worn to the channel structure of the semiconductor substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109037225A (en) * | 2018-09-19 | 2018-12-18 | 长江存储科技有限责任公司 | Memory construction |
| CN110783342A (en) * | 2019-11-05 | 2020-02-11 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device |
| CN113707665A (en) * | 2019-01-02 | 2021-11-26 | 长江存储科技有限责任公司 | Memory and forming method thereof |
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