CN107644836A - Wafer three-dimensional integration lead technique and its structure for three-dimensional storage - Google Patents
Wafer three-dimensional integration lead technique and its structure for three-dimensional storage Download PDFInfo
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- CN107644836A CN107644836A CN201710773134.0A CN201710773134A CN107644836A CN 107644836 A CN107644836 A CN 107644836A CN 201710773134 A CN201710773134 A CN 201710773134A CN 107644836 A CN107644836 A CN 107644836A
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Abstract
The present invention provides a kind of wafer three-dimensional integration lead technique and its structure, the technique and can be applied in the wafer three-dimensional integration technique of three-dimensional storage wafer.By setting dielectric layer 13 between the first wafer 11 and three-dimensional storage part 14, and the contact hole 15 for metal interconnection is arranged to contact with the dielectric layer 13.The present invention proposes a kind of new lead technique so that can realize back side lead through thicker device layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of wafer three-dimensional integration lead technique and its knot
Structure, the technique can be applied in the wafer three-dimensional integration technique of three-dimensional storage wafer.
Background technology
The continuous diminution of semiconductor device improves constantly integrated level, chip area every square centimeter at present
On can integrate more than 1,000,000,000 transistors, and the total length of metal interconnecting wires is even more to have reached tens kilometers.This not only causes
Wiring becomes complex, it is often more important that the delay of metal interconnection, power consumption, noise etc. all with characteristic size reduction without
Disconnected increase, particularly globally interconnected RC (resistance capacitance) delays, has had a strong impact on the performance of integrated circuit.Therefore, metal is mutual
Company, which has been substituted transistor, turns into the principal element for determining performance of integrated circuits.
Chip system (SoC, System on a Chip) technology wishes to realize the repertoire of system on a single chip, such as
Array, simulation, radio frequency, photoelectricity and MEMS (Microelectromechanical Systems, MEMS), SoC hair
Maximum difficulty is different process compatible problems in exhibition, for example, realize SoC may need standard COMS, RF, Bipolar and
The techniques such as MEMS, the backing material of these manufacturing process are all different, as a consequence it is hardly possible to by its Integrated manufacture on a chip is led to.
Even if backing material identical module, the manufacture feasibility of each circuit module is also considered in the mill.
As electronic equipment and memory are towards miniaturization and slimming development, the volume and thickness of chip there has also been more
High requirement.The three-dimensionally integrated of wafer is a kind of scheme for effectively reducing chip volume and thickness, this technology by two or
Multiple function phases are same or different chips is integrated by bonding, i.e., a big planar circuit are divided into some logics
Upper related functional module is distributed in multiple adjacent chip layers, is then interconnected by penetrating the three-dimensional perpendicular of substrate by multilayer
Integrated chip.It is this to be integrated in the performance for keeping that chip is improved while chip volume；Shorten simultaneously between functional chip
Metal interconnection so that heating, power consumption, delay are greatly reduced；The bandwidth between functional module is greatly improved, is keeping
The performance of chip is improved while prior art node.Three-dimensional interconnection can be with integrated multi-layer different process or various substrates material
Integrated circuit, provide good solution for the SoC of heterogeneous chip.Three-dimensional interconnection is all physical interconnections, be can solve the problem that
The problems such as heterogeneous integrated, high-bandwidth communication of multi-chip and interconnection delay.
At present, the three-dimensional integration technology of wafer is used widely first in imaging sensor.In memory, system combination
Etc. also begin to gradually play its advantage.As shown in figure 1, lead technology in existing wafer three-dimensional integration is mainly used from the
The first layer metal 02 that the back side of one wafer 01 makes front, which is opened, to be exposed, and is completed by way of metal lead wire 03 connects.
When above-mentioned wafer three-dimensional integration lead technique is applied in three-dimensional storage technology, as shown in Fig. 2 because three-dimensional storage is single
Member makes perpendicular to crystal column surface, has between the front face surface of the first wafer 01 and front the first metal layer 02 up to a few micrometers
Three-dimensional storage part layer 04, extreme difficulties are brought for front the first metal layer is drawn.Present invention aim to provide one
Kind new wafer three-dimensional integration lead technique and its structure so that back side lead can be realized through thicker device layer, the work
Skill can apply in the wafer three-dimensional integration technique of three-dimensional storage wafer, so as to solve above-mentioned technical problem.
The content of the invention
The purpose of the present invention is achieved through the following technical solutions.
A kind of wafer three-dimensional integration lead technique, comprises the following steps：
One first wafer is provided, first wafer has the front and back being oppositely arranged, and the front of first wafer is extremely
Contact bore region is provided with small part region；
Dielectric layer is formed in the contact bore region, the dielectric layer has the top surface being oppositely arranged and bottom surface, the dielectric layer
Thickness scope at 0.1 micron to 5 microns, wherein the top surface be towards the side of first wafer frontside, the bottom surface is court
To the side of first wafer rear；
Comprised at least in the front of first wafer on the region of dielectric layer and manufacture semiconductor devices, the semiconductor devices bag
Contact hole is included, one end of the contact hole contacts with the dielectric layer；
By the semiconductor devices side of the first wafer including the semiconductor devices and the second wafer bonding, and by this first
The back side of wafer is thinned, and the wafer substrate thickness after being thinned is at 0.5 micron to 20 microns；
The back side of first wafer after being thinned carries out perforate processing, exposes at least a portion surface of the dielectric layer；
Processing is performed etching to the dielectric layer surface exposed, to expose the contact hole in the semiconductor devices；
Determined in the backside deposition lead metal level of first wafer, and to the lead metal level using lithographic and etching technics
Adopted pin configuration, the contact holes contact of semiconductor devices of the pin configuration with exposure in the dielectric layer.
Preferably, the bottom surface of the dielectric layer is located at first inside wafer, the top surface of the dielectric layer and first wafer
Front flush.
Preferably, the bottom surface of the dielectric layer is located at first inside wafer, and the top surface of the dielectric layer is higher than first wafer
Front.
Preferably, the bottom surface of the dielectric layer and the front flat contact of first wafer, the top surface of the dielectric layer is higher than should
The front of first wafer.
Preferably, the technique for dielectric layer being formed in the contact bore region includes lithographic, etches, deposition, filling and grinding
One of or its any combination.
Preferably, the semiconductor devices is three-dimensional storage, and the three-dimensional storage is including remote first wafer of order just
The three-dimensional storage part layer and the first metal layer in face, the contact hole are located in the three-dimensional storage part layer, one end of the contact hole
Contacted with the dielectric layer, the other end of the contact hole contacts with the first metal layer.
Preferably, one end of the contact hole is located in the inside of the dielectric layer, or one end of the contact hole and the medium
The top surface contact of layer, or one end of the contact hole contact through the dielectric layer and with the bottom surface of the dielectric layer.
Preferably, the back side of first wafer after being thinned carries out perforate processing, expose the dielectric layer at least one
Divide after surface, insulating barrier, the medium at least exposed in the side wall of covering perforate and perforate are made at the back side of first wafer
The surface of layer.
Preferably, after pin configuration is formed, in the backside deposition protective layer of first wafer, and lithographic and quarter are passed through
Etching technique forms protective layer structure.
Preferably, the material of the insulating barrier and/or the protective layer is oxide or nitride or nitrogen oxides.
Preferably, metal material is filled in the contact hole.
Preferably, the metal material includes one of copper, aluminium, tin or tungsten or its any combination.
Preferably, the dielectric layer is medium of oxides layer or nitride dielectric layer.
Preferably, the material of first wafer and/or second wafer is silicon, germanium, III-V semiconducting compound, carbonization
One of silicon on silicon or dielectric substrate or its any combination.
The present invention also provides a kind of wafer three-dimensional integration lead technique for three-dimensional storage, and the technique includes above-mentioned
One wafer three-dimensional integration lead technique of meaning, wherein, the semiconductor devices is three-dimensional storage, and the three-dimensional storage includes order
Three-dimensional storage part layer and the first metal layer away from first wafer frontside, the contact hole are located at the three-dimensional storage part layer
Interior, one end of the contact hole contacts with the dielectric layer, and the other end of the contact hole contacts with the first metal layer；The three-dimensional stores
Device layer includes multiple memory cell repeatedly stackings and formed.
Preferably, the thickness of the three-dimensional storage part layer more than or equal to 1 micron, less than or equal to 50 microns between.
In addition, the present invention also provides a kind of wafer three-dimensional integration pin configuration for three-dimensional storage, wherein, the structure
It is made up of the technique described in any of the above-described.
Advantages of the present invention or beneficial effect are：, can be by crystalline substance by above-mentioned technique provided by the invention and its structure
Round three-dimensionally integrated lead technique is applied in the wafer three-dimensional integration technique of three-dimensional storage wafer, by wafer and three-dimensional
Dielectric layer is set between memory device layer, and the contact hole for metal interconnection is arranged to contact with the dielectric layer, is being formed
During lead link structure, back side lead can be realized through thicker device layer, reduce cost of manufacture, improve production
Product yield.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 shows wafer three-dimensional integration pin configuration schematic diagram in background of invention；
Fig. 2 is shown in background of invention is applied to three-dimensional storage by existing wafer three-dimensional integration pin configuration
The schematic diagram of pin configuration；
Fig. 3-9 shows the flow knot of the wafer three-dimensional integration lead technique for three-dimensional storage of the embodiment of the present invention
Structure schematic diagram.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in accompanying drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
Embodiment one
With reference to shown in figure 3-9, the embodiment of the present invention one provides a kind of wafer three-dimensional integration lead technique, including following step
Suddenly：
One first wafer 11 is provided, first wafer 11 has the front and back being oppositely arranged, first wafer 11
Contact bore region 12 is provided with positive at least part region；
Dielectric layer 13 is formed in the contact bore region 12, the dielectric layer 13 is medium of oxides layer 13 or nitride dielectric
Layer 13, the scope of the thickness of the dielectric layer form dielectric layer 13 between 0.1 micron to 5 microns in the contact bore region 12
Technique include lithographic, etch, deposition, one of filling and grinding or its any combination, the dielectric layer have the top that is oppositely arranged
Face and bottom surface, the wherein top surface are towards the side of first wafer frontside, and the bottom surface is towards the one of first wafer rear
Side；
Comprised at least in the front of first wafer 11 and semiconductor devices 14, the semiconductor are manufactured on the region of dielectric layer 13
Device 14 includes contact hole 15, and one end of the contact hole 15 is contacted with the dielectric layer 13, and metal material is filled in the contact hole 15,
The metal material is one of copper, aluminium, tin or tungsten or its any combination；
The semiconductor devices 14 is three-dimensional storage, and it is positive away from first wafer 11 that the three-dimensional storage includes order
Three-dimensional storage part layer 141 and the first metal layer 18, the contact hole 15 are located in the three-dimensional storage part layer 141, the contact hole
15 one end contacts with the dielectric layer 13, and the other end of the contact hole 15 contacts with the first metal layer 18.
The side of semiconductor devices 14 of the first wafer 11 including the semiconductor devices 14 is bonded with the second wafer 16, and
The back side of first wafer 11 is thinned, the wafer substrate thickness after being thinned is 0.5 micron to 20 microns；
The back side of first wafer 11 after being thinned carries out perforate processing, exposes at least a portion table of the dielectric layer 13
Face；
Processing is performed etching to the surface of dielectric layer 13 exposed, to expose the contact hole 15 in the semiconductor devices 14；
Lithographic and etching technics are utilized in the backside deposition lead metal level of first wafer 11, and to the lead metal level
Pin configuration 17 is defined, the pin configuration 17 contacts with the contact hole 15 of the semiconductor devices 14 in dielectric layer 13, should
The material of lead metal level is one of copper, silver, aluminium, tin or tungsten or its any combination；
The material of first wafer 11 and/or second wafer 16 is silicon, germanium, III-V semiconducting compound, carborundum
Or one of silicon in dielectric substrate or its any combination.
Embodiment two
In this embodiment, the part different from above example will be described, same section will not be described in great detail.
With reference to shown in figure 3, the dielectric layer 13 has the bottom surface being oppositely arranged and top surface, and the bottom surface is farther relative to top surface
From the side of the first metal layer 18.In the step of forming dielectric layer 13, first, by lithographic and etching technics this
The contact bore region 12 of the front face surface of one wafer 11 forms a shallow trench, recycles deposition and fill process in the shallow trench
The dielectric layer 13 is formed, the dielectric layer 13 can also be subsequently ground by grinding technics makes its planarization.By above-mentioned
After processing step, the bottom surface of the dielectric layer 13 of formation is located inside first wafer 11, the top surface of the dielectric layer 13 with this
The front flush of one wafer 11.
The concrete technology step of above-mentioned formation dielectric layer is first, hard mask layer to be formed on the front of the first wafer, according to
It is secondary to etch the hard mask layer and the first wafer, groove is formed, hard mask layer is, for example, to be formed using chemical vapor deposition method
Silicon nitride layer, or using high density plasma CVD (High Density Plasma Chemical
Vapor Deposition, HDPCVD) technique formed silicon oxide layer.The hard mask layer and the first wafer are etched, forms ditch
Groove can use any prior art well known to those skilled in the art.
Then, metallization medium layer, the dielectric layer fill up groove in the groove and on hard mask layer；Described Jie
Matter layer material inserts the technique of dielectric material for example with high-density plasma such as silica, silicon nitride, silicon oxynitride
Chemical vapor deposition (High Density Plasma Chemical Vapor Deposition, HDPCVD) method.
Then, the dielectric layer on hard mask layer is removed；The technique for removing the dielectric layer on hard mask layer for example passes through
The method for chemically-mechanicapolish polishing (Chemical Mechanical Polishing, CMP), after CMP, hard mask layer surface with
The dielectric layer of upper deposition is completely removed, and is all exposed so as to the upper surface of hard mask layer.
Then, rapid thermal oxidation processing is carried out, the environment temperature for carrying out rapid thermal oxidation is 400~800 degrees Celsius, is used
This step can eliminate corner damage to caused by atomic structure in previous process of groove, avoid making in follow-up technique
Damaged into groove corner.Preferably, the environment temperature residing for groove is 500-700 degrees Celsius.One in the present invention is specific real
Apply in mode, by the environment temperature linear heat residing for groove to 400~800 degrees Celsius in 60 seconds~140 seconds.
In specific implementation, the environment temperature residing for groove can for example select 450 degrees Celsius, and 480 degrees Celsius, 550 is Celsius
Degree, 600 degrees Celsius, 660 degrees Celsius, 640 degrees Celsius, 750 degrees Celsius etc..Such as 70 seconds time of linear heating environment temperature,
75 seconds, 80 seconds, 95 seconds, 103 seconds, 115 seconds, 125 seconds, 130 seconds.
In described rapid thermal oxidation process, in addition to the environment where groove be passed through oxygen-containing gas technique walk
Suddenly, described oxygen-containing gas such as oxygen (O2), ozone (O3) etc. have oxidability gas.
In described rapid thermal oxidation process, the dielectric layer in the groove is among high-temperature oxygen environment, high temperature
Oxygen molecule concentration under environment is larger and molecular activity is higher, and due to the original molecule of the groove dielectric layer edge
Structure is more loose, therefore caused free state silicon ion will be substantially oxidized in this course during the CMP, oxidation
Original oxide molecule recombines to form stable point at high temperature in dielectric layer in the oxide and groove that generate afterwards
Sub-key so that the oxide structure of the edge of the dielectric layer in the groove by it is original it is loose become to consolidate, it is fine and close, so as to
The corner damage of dielectric layer in the groove can be repaired effectively, the process of the high-temperature oxydation be generally also commonly called as
High temperature quenches.
Finally, hard mask layer is removed.The technique of the hard mask layer is removed for example with wet etching (Wet Etch), institute
The chemical etching reagent used is the known technology of those skilled in the art according to the different and different of hard mask material layer.
Embodiment three
In this embodiment, the part different from above example will be described, same section will not be described in great detail.
The dielectric layer 13 has the bottom surface that is oppositely arranged and a top surface, and the bottom surface is further from first metal relative to top surface
The side of layer 18.In the step of forming dielectric layer 13, first, by lithographic and etching technics in first wafer 11 just
The contact bore region 12 on face surface forms a shallow trench, recycles deposition and fill process to form the dielectric layer in the shallow trench
13, the dielectric layer 13 can also be subsequently ground by grinding technics makes its planarization.After above-mentioned processing step, shape
Into the bottom surface of the dielectric layer 13 be located inside first wafer 11, the top surface of the dielectric layer 13 is higher than first wafer 11 just
Face.
Example IV
In this embodiment, the part different from above example will be described, same section will not be described in great detail.
The dielectric layer 13 has the bottom surface that is oppositely arranged and a top surface, and the bottom surface is further from first metal relative to top surface
The side of layer 18.In the step of forming dielectric layer 13, first, connect by depositing operation in the positive of first wafer 11
The dielectric layer 13 is formed on the surface of contact hole region 12, the dielectric layer 13 can also be subsequently ground by grinding technics makes it
Planarization.After above-mentioned processing step, the bottom surface of the dielectric layer 13 of formation and the front flat contact of first wafer 11,
The top surface of the dielectric layer 13 is higher than the front of first wafer 11.
Embodiment five
In this embodiment, the part different from above example will be described, same section will not be described in great detail.
With reference to shown in figure 3, one end of the contact hole 15 is located in the inside of the dielectric layer 13.Or the contact hole 15
One end contacts with the top surface of the dielectric layer 13, or the contact hole 15 one end through the dielectric layer 13 and with the dielectric layer 13
Bottom surface contacts.
Embodiment six
In this embodiment, the part different from above example will be described, same section will not be described in great detail.
With reference to shown in figure 6, the back side of first wafer 11 after being thinned carries out perforate processing, exposes the dielectric layer 13
After at least a portion surface, insulating barrier 19 is made at the back side of first wafer 11, at least covers side wall and the perforate of perforate
In the surface of dielectric layer 13 exposed.The material of the insulating barrier 19 is oxide or nitride or nitrogen oxides.
Embodiment seven
In this embodiment, the part different from above example will be described, same section will not be described in great detail.
With reference to shown in figure 9, after pin configuration 17 is formed, in the backside deposition protective layer 20 of first wafer 11, and
The structure of protective layer 20 is formed by lithographic and etching technics.The material of the protective layer 20 is oxide or nitride or nitrogen oxidation
Thing.
Embodiment eight
In this embodiment, the part different from above example will be described, same section will not be described in great detail.
With reference to shown in figure 3-9, the embodiment provides a kind of wafer three-dimensional integration lead technique for three-dimensional storage, should
Technique includes any one wafer three-dimensional integration lead technique of above-described embodiment one to seven, wherein, the semiconductor devices 14 is three
Memory is tieed up, the three-dimensional storage includes order away from the positive gold medal of three-dimensional storage part layer 141 and first of first wafer 11
Belonging to layer 18, the contact hole 15 is located in the three-dimensional storage part layer 141, and one end of the contact hole 15 contacts with the dielectric layer 13,
The other end of the contact hole 15 contacts with the first metal layer 18；The three-dimensional storage part layer 141 includes multiple memory cell weights
Stack and formed again.Preferably, the thickness of the three-dimensional storage part layer 141 more than or equal to 1 micron, less than or equal to 50 microns it
Between, it is more preferably, greater than equal to 5 microns.
Embodiment nine
In this embodiment, the part different from above example will be described, same section will not be described in great detail.With reference to figure 9
Shown, the embodiment provides a kind of wafer three-dimensional integration pin configuration for three-dimensional storage, wherein, the structure is by above-mentioned reality
The technique described in any one of example one to eight is applied to be made.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (17)
1. a kind of wafer three-dimensional integration lead technique, it is characterised in that comprise the following steps：
One first wafer is provided, first wafer has the front and back being oppositely arranged, the front at least portion of first wafer
Contact bore region is provided with subregion；
Dielectric layer is formed in the contact bore region, the dielectric layer is with the top surface and bottom surface, the wherein top surface being oppositely arranged
Towards the side of first wafer frontside, the bottom surface is towards the side of first wafer rear；
Comprised at least in the front of first wafer on the region of dielectric layer and manufacture semiconductor devices, the semiconductor devices includes connecing
Contact hole, one end of the contact hole contact with the dielectric layer；
By the semiconductor devices side of the first wafer including the semiconductor devices and the second wafer bonding, and by first wafer
The back side be thinned；
The back side of first wafer after being thinned carries out perforate processing, exposes at least a portion surface of the dielectric layer；
Processing is performed etching to the dielectric layer surface exposed, to expose the contact hole in the semiconductor devices；
Drawn in the backside deposition lead metal level of first wafer, and to the lead metal level using lithographic and etching technics definition
Cable architecture, the contact holes contact of semiconductor devices of the pin configuration with exposure in the dielectric layer.
2. wafer three-dimensional integration lead technique as claimed in claim 1, it is characterised in that the bottom surface of the dielectric layer be located at this
One inside wafer, the front flush of the top surface of the dielectric layer and first wafer.
3. wafer three-dimensional integration lead technique as claimed in claim 1, it is characterised in that the bottom surface of the dielectric layer be located at this
One inside wafer, the top surface of the dielectric layer are higher than the front of first wafer.
4. wafer three-dimensional integration lead technique as claimed in claim 1, it is characterised in that the bottom surface of the dielectric layer with this first
The front flat contact of wafer, the top surface of the dielectric layer are higher than the front of first wafer.
5. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, it is characterised in that in the contact hole
The technique of dielectric layer is formed in region includes lithographic, etches, deposition, one of filling and grinding or its any combination.
6. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, it is characterised in that the semiconductor device
Part is three-dimensional storage, and the three-dimensional storage includes three-dimensional storage part layer and first gold medal of the order away from first wafer frontside
Belong to layer, the contact hole is located in the three-dimensional storage part layer, and one end of the contact hole contacts with the dielectric layer, the contact hole it is another
One end contacts with the first metal layer.
7. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, it is characterised in that the contact hole
One end is located in the inside of the dielectric layer, and either one end of the contact hole contacts or the contact hole with the top surface of the dielectric layer
One end through the dielectric layer and being contacted with the bottom surface of the dielectric layer.
8. wafer three-dimensional integration lead technique as claimed in claim 1, it is characterised in that first wafer after being thinned
The back side carries out perforate processing, and after at least a portion surface for exposing the dielectric layer, insulation is made at the back side of first wafer
The surface of the dielectric layer exposed in layer, at least side wall of covering perforate and perforate.
9. wafer three-dimensional integration lead technique as claimed in claim 1, it is characterised in that after pin configuration is formed,
The backside deposition protective layer of first wafer, and protective layer structure is formed by lithographic and etching technics.
10. the wafer three-dimensional integration lead technique as described in any one of claim 8 or 9, it is characterised in that the insulating barrier
And/or the material of the protective layer is oxide or nitride or nitrogen oxides.
11. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, it is characterised in that in the contact hole
Fill metal material.
12. wafer three-dimensional integration lead technique as claimed in claim 11, it is characterised in that the metal material include copper, aluminium,
One of tin or tungsten or its any combination.
13. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, it is characterised in that the dielectric layer is
Medium of oxides layer or nitride dielectric layer.
14. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, it is characterised in that first wafer
And/or the material of second wafer be one of silicon in silicon, germanium, III-V semiconducting compound, carborundum or dielectric substrate or
It is combined.
15. a kind of wafer three-dimensional integration lead technique for three-dimensional storage, the technique is included as claim 1 to 14 is any
Wafer three-dimensional integration lead technique described in one, it is characterised in that the semiconductor devices is three-dimensional storage, and the three-dimensional stores
Device includes three-dimensional storage part layer and the first metal layer of the order away from first wafer frontside, and the contact hole is located at the three-dimensional and deposited
In memory device layer, one end of the contact hole contacts with the dielectric layer, and the other end of the contact hole contacts with the first metal layer；Should
Three-dimensional storage part layer includes multiple memory cell repeatedly stackings and formed.
16. it is used for the wafer three-dimensional integration lead technique of three-dimensional storage as claimed in claim 15, it is characterised in that this three
Tie up memory device layer thickness more than or equal to 1 micron, less than or equal to 50 microns between.
17. a kind of wafer three-dimensional integration pin configuration for three-dimensional storage, it is characterised in that the structure is by such as claim
Technique described in 1 to 16 any one is made.
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| CN109742081A (en) * | 2019-01-02 | 2019-05-10 | 长江存储科技有限责任公司 | Memory and forming method thereof |
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| CN109742081A (en) * | 2019-01-02 | 2019-05-10 | 长江存储科技有限责任公司 | Memory and forming method thereof |
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