CN107644841B - Wafer three-dimensional integration lead technique and its structure for three-dimensional storage - Google Patents
Wafer three-dimensional integration lead technique and its structure for three-dimensional storage Download PDFInfo
- Publication number
- CN107644841B CN107644841B CN201710775904.5A CN201710775904A CN107644841B CN 107644841 B CN107644841 B CN 107644841B CN 201710775904 A CN201710775904 A CN 201710775904A CN 107644841 B CN107644841 B CN 107644841B
- Authority
- CN
- China
- Prior art keywords
- wafer
- dielectric layer
- layer
- dimensional
- technique
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Abstract
The present invention provides a kind of wafer three-dimensional integration lead technique and its structure, the technique and can be applied in the wafer three-dimensional integration technique of three-dimensional storage wafer.By the way that the dielectric layer 13 with a thickness of 1 micron is arranged between the first wafer 11 and three-dimensional storage part 14, and the contact hole 15 for being used for metal interconnection is set as contacting with the dielectric layer 13, present invention aim to provide a kind of new wafer three-dimensional integration lead technique and its structure, allow to realize back side lead across thicker device layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of wafer three-dimensional integration lead technique and its knots
Structure, the technique can be applied in the wafer three-dimensional integration technique of three-dimensional storage wafer.
Background technique
Integrated level is continuously improved in the continuous diminution of semiconductor device, chip area every square centimeter at present
On can integrate more than 1,000,000,000 transistors, and the total length of metal interconnecting wires is even more to have reached tens kilometers.This not only makes
Wiring becomes complex, it is often more important that delay, power consumption, noise etc. of metal interconnection all with the reduction of characteristic size without
Disconnected to increase, especially globally interconnected RC (resistance capacitance) delay has seriously affected the performance of integrated circuit.Therefore, metal is mutual
Company, which has been substituted transistor, becomes the principal element for determining performance of integrated circuits.
Chip system (SoC, System on a Chip) technology wishes the repertoire for realizing system on a single chip, such as
Array, simulation, radio frequency, photoelectricity and MEMS (Microelectromechanical Systems, MEMS), SoC hair
Maximum difficulty is different process compatible problem in exhibition, for example, realize SoC may need standard COMS, RF, Bipolar and
The substrate material of the techniques such as MEMS, these manufacturing process is all different, as a consequence it is hardly possible to by its Integrated manufacture on a logical chip.
Even if the identical module of substrate material will also consider the manufacture feasibility of each circuit module during manufacturing.
As electronic equipment and memory are towards miniaturization and slimming development, there has also been more for volume and thickness to chip
High requirement.The three-dimensionally integrated of wafer is a kind of scheme for effectively reducing chip volume and thickness, this technology by two or
The same or different chip of multiple functions is integrated by bonding, i.e., a big planar circuit is divided into several logics
Upper relevant functional module is distributed in multiple adjacent chip layers, is then interconnected by penetrating the three-dimensional perpendicular of substrate by multilayer
Integrated chip.It is this to be integrated in the performance for keeping that chip is improved while chip volume；It shortens between functional chip simultaneously
Metal interconnection so that fever, power consumption, delay are greatly reduced；The bandwidth between functional module is greatly improved, is keeping
The performance of chip is improved while prior art node.Three-dimensional interconnection can integrate multilayer different process or various substrates material
Integrated circuit, provide good solution for the SoC of heterogeneous chip.Three-dimensional interconnection is all physical interconnections, is able to solve
The problems such as heterogeneous integrated, high-bandwidth communication of multi-chip and interconnection delay.
Currently, the three-dimensional integration technology of wafer is used widely first in imaging sensor.In memory, system combination
Etc. also start gradually to play its advantage.As shown in Figure 1, the lead technology in existing wafer three-dimensional integration is mainly used from
The first layer metal 02 of front production is opened at one wafer, 01 back side to be exposed, and is completed in such a way that metal lead wire 03 connects.
When above-mentioned wafer three-dimensional integration lead technique to be applied in three-dimensional storage technology, as shown in Fig. 2, since three-dimensional storage is single
Member makes perpendicular to crystal column surface, has between 01 front face surface of the first wafer and front the first metal layer 02 up to a few micrometers
Three-dimensional storage part layer 04, for the first metal layer extraction in front is brought extreme difficulties.Present invention aim to provide one
Kind new wafer three-dimensional integration lead technique and its structure allow to realize back side lead, the work across thicker device layer
Skill can be applied in the wafer three-dimensional integration technique of three-dimensional storage wafer, to solve above-mentioned technical problem.
Summary of the invention
The purpose of the present invention is what is be achieved through the following technical solutions.
A kind of wafer three-dimensional integration lead technique, comprising the following steps:
One first wafer is provided, which has the front and back being oppositely arranged, and the front of first wafer is extremely
Contact bore region is provided on small part region；
Dielectric layer is formed in the contact bore region, which has the top and bottom being oppositely arranged, wherein the top
Face is towards the side of first wafer frontside, which is towards the side of first backside of wafer；
The manufacturing semiconductor devices on the region that the front of first wafer includes at least dielectric layer, the semiconductor devices packet
Contact hole is included, one end of the contact hole is contacted with the dielectric layer；
By include the semiconductor devices the first wafer semiconductor devices side and the second wafer bonding, and by this first
The back side of wafer carries out thinned, exposes the dielectric layer after being thinned；
The first protective layer is deposited on the backside surface of first wafer after being thinned；
Metal connecting structure, the metal connecting structure are formed in the back side of first wafer position corresponding with the contact hole
It is electrically connected with the corresponding contact hole；
In the backside deposition lead metal layer of first wafer, and it is fixed using lithographic and etching technics to the lead metal layer
Adopted pin configuration, the pin configuration are electrically connected with the metal connecting structure.
Preferably, the bottom surface of the dielectric layer is located at first inside wafer, the top surface of the dielectric layer and first wafer
Front flush.
Preferably, the bottom surface of the dielectric layer is located at first inside wafer, and the top surface of the dielectric layer is higher than first wafer
Front.
Preferably, the front flat contact of the bottom surface of the dielectric layer and first wafer, the top surface of the dielectric layer is higher than should
The front of first wafer.
Preferably, the technique for dielectric layer being formed in the contact bore region includes lithographic, is etched, deposition, filling and grinding
One of or any combination thereof.
Preferably, the semiconductor devices be three-dimensional storage, the three-dimensional storage include sequence far from first wafer just
The three-dimensional storage part layer and the first metal layer in face, the contact hole are located in the three-dimensional storage part layer, one end of the contact hole
It is contacted with the dielectric layer, the other end of the contact hole is contacted with the first metal layer.
Preferably, one end of the contact hole is located in the inside of the dielectric layer or one end of the contact hole and the medium
The top surface contact of layer or one end of the contact hole pass through the dielectric layer and contact with the bottom surface of the dielectric layer.
Preferably, the technique packet of metal connecting structure is formed in the back side of first wafer position corresponding with the contact hole
Lithographic is included, is etched, one of metal filling and chemical mechanical grinding or any combination thereof.
Preferably, after forming pin configuration, in the second protective layer of backside deposition of first wafer, and pass through lithographic
The second protective layer structure is formed with etching technics.
Preferably, the material of first protective layer and/or second protective layer is oxide or nitride or nitrogen oxides.
Preferably, metal material is filled in the contact hole.
Preferably, which includes one of copper, aluminium, tin or tungsten or any combination thereof.
Preferably, which is medium of oxides layer or nitride dielectric layer.
Preferably, the material of first wafer and/or second wafer is silicon, germanium, three-five semiconducting compound, carbonization
One of silicon on silicon or insulating substrate or any combination thereof.
Preferably, the material of the metal connecting structure includes one of copper, aluminium, tin or tungsten or any combination thereof.
The present invention also provides a kind of wafer three-dimensional integration lead techniques for three-dimensional storage, which includes above-mentioned
It anticipates a wafer three-dimensional integration lead technique, wherein the semiconductor devices is three-dimensional storage, which includes sequence
Three-dimensional storage part layer and the first metal layer far from first wafer frontside, the contact hole are located at the three-dimensional storage part layer
Interior, one end of the contact hole is contacted with the dielectric layer, and the other end of the contact hole is contacted with the first metal layer；Three-dimensional storage
Device layer includes multiple storage unit repeatedly stackings and is formed.
Preferably, the thickness degree of the three-dimensional storage part layer is being more than or equal to 1 micron, is being less than or equal between 50 microns.
In addition, the present invention also provides a kind of wafer three-dimensional integration pin configurations for three-dimensional storage, wherein the structure
It is made of technique described in any of the above embodiments.
Advantages of the present invention or beneficial effect are: the above-mentioned technique and its structure provided through the invention, can will be brilliant
Round three-dimensionally integrated lead technique is applied in the wafer three-dimensional integration technique of three-dimensional storage wafer, by wafer and three-dimensional
Dielectric layer is set between memory device layer, and the contact hole for being used for metal interconnection is set as contacting with the dielectric layer, is being formed
During lead wire connection structure, thicker device layer can be passed through and realize back side lead, reduce the production cost, improve production
Product yield.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 shows wafer three-dimensional integration pin configuration schematic diagram in background of invention；
Fig. 2 shows existing wafer three-dimensional integration pin configuration is applied to three-dimensional storage in background of invention
The schematic diagram of pin configuration；
Fig. 3-7 shows the process knot of the wafer three-dimensional integration lead technique for three-dimensional storage of the embodiment of the present invention
Structure schematic diagram.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
Embodiment one
With reference to shown in Fig. 3-7, the embodiment of the present invention one provides a kind of wafer three-dimensional integration lead technique, including following step
It is rapid:
One first wafer 11 is provided, which has the front and back being oppositely arranged, first wafer 11
Contact bore region 12 is provided on at least partly region of front；
In the contact bore region 12 formed dielectric layer 13, it is preferable that the thickness range of the dielectric layer be 0.3 micron extremely
5 microns, it is highly preferred that the thickness of the dielectric layer is about 1 micron, which is medium of oxides layer 13 or nitride dielectric
Layer 13, in the contact bore region 12 formed dielectric layer 13 technique include lithographic, etch, deposition, filling and grinding one of or
Any combination thereof, the dielectric layer have the top and bottom being oppositely arranged, and wherein the top surface is towards first wafer frontside
Side, the bottom surface are towards the side of first backside of wafer；
The manufacturing semiconductor devices 14 on the region that the front of first wafer 11 includes at least dielectric layer 13, the semiconductor
Device 14 includes contact hole 15, and one end of the contact hole 15 is contacted with the dielectric layer 13, fills metal material in the contact hole 15,
The metal material is one of copper, aluminium, tin or tungsten or any combination thereof；
The semiconductor devices 14 is three-dimensional storage, which includes that sequence is positive far from first wafer 11
Three-dimensional storage part layer 141 and the first metal layer 18, the contact hole 15 are located in the three-dimensional storage part layer 141, the contact hole
15 one end is contacted with the dielectric layer 13, and the other end of the contact hole 15 is contacted with the first metal layer 18.
14 side of semiconductor devices of the first wafer 11 including the semiconductor devices 14 is bonded with the second wafer 16, and
The back side of first wafer 11 is carried out it is thinned, be thinned after wafer substrate with a thickness of 0.5 micron to 5 microns, be thinned after
The dielectric layer 13 is exposed, the insulating layer of thin-film deposition in subsequent through-hole is thus reduced；
The first protective layer 19 is deposited on the backside surface of first wafer after being thinned, the material of first protective layer is
Oxide or nitride or nitrogen oxides；
Metal connecting structure 22 is formed in the back side of first wafer 11 position corresponding with the contact hole 15, which connects
Binding structure 22 is electrically connected with the corresponding contact hole 15, and the technique for forming the metal connecting structure 22 includes lithographic, etching, metal
One of filling and chemical mechanical grinding or any combination thereof；
Drawn in the backside deposition lead metal layer of first wafer 11, and to the lead metal layer using lithographic etching definition
Cable architecture 17, the pin configuration 17 are electrically connected with the metal connecting structure 22, and the material of the lead metal layer is copper, silver, aluminium, tin
Or one of tungsten or any combination thereof；
The material of first wafer 11 and/or second wafer 16 is silicon, germanium, three-five semiconducting compound, silicon carbide
Or one of silicon in insulating substrate or any combination thereof.
Embodiment two
In this embodiment, the part different from above embodiments will be described, same section will not be described in great detail.
Refering to what is shown in Fig. 3, the dielectric layer 13 has the bottom surface and top surface being oppositely arranged, which is farther relative to top surface
Side from the first metal layer 18.Preferably, the thickness range of the dielectric layer is 0.3 micron to 5 microns, it is highly preferred that
The thickness of the dielectric layer is about 1 micron.In the step of forming dielectric layer 13, firstly, by lithographic and etching technics at this
The contact bore region 12 of the front face surface of first wafer 11 forms a groove, the depth of the groove cannot too shallowly can not be too deep,
The dielectric layer that depth is shallowly formed very much is too thin cannot to effectively complete the technique for being subsequently formed metal connecting structure, depth too deep at
Dielectric layer it is too thick certain difficulty is also brought for subsequent production metal connecting structure, therefore, the depth of the groove is preferably about 1
Micron recycles deposition and fill process to form the dielectric layer 13 in the groove, it is subsequent can also be by grinding technics to this
Dielectric layer 13, which carries out grinding, makes its planarization.After above-mentioned processing step, the bottom surface of the dielectric layer 13 of formation be located at this
Inside one wafer 11, the front flush of the top surface of the dielectric layer 13 and first wafer 11, the thickness of the dielectric layer 13 is about 1 micro-
Rice.
The specific process step of above-mentioned formation dielectric layer is, firstly, hard mask layer is formed on the front of the first wafer, according to
It is secondary to etch the hard mask layer and the first wafer, groove is formed, hard mask layer is, for example, to be formed using chemical vapor deposition process
Silicon nitride layer, or use high density plasma CVD (High Density Plasma Chemical
Vapor Deposition, HDPCVD) technique formed silicon oxide layer.The hard mask layer and the first wafer are etched, ditch is formed
Slot can use any prior art well known to those skilled in the art.
Then, metallization medium layer, the dielectric layer fill up groove in the groove and on hard mask layer；Jie
Matter layer material such as silica, silicon nitride, silicon oxynitride etc. inserts the technique of dielectric material for example, by using high-density plasma
Chemical vapor deposition (High Density Plasma Chemical Vapor Deposition, HDPCVD) method.
Then, removal is located at the dielectric layer on hard mask layer；The technique of dielectric layer on removal hard mask layer for example passes through
The method for chemically-mechanicapolish polishing (Chemical Mechanical Polishing, CMP), after CMP, hard mask layer surface with
The dielectric layer of upper deposition is completely removed, so that the upper surface of hard mask layer is all exposed.
Then, rapid thermal oxidation processing is carried out, the environment temperature for carrying out rapid thermal oxidation is 400~800 degrees Celsius, is used
This step can eliminate corner damage caused by atomic structure in previous process of groove, avoid making in subsequent technique
It is damaged at groove corner.Preferably, environment temperature locating for groove is 500-700 degrees Celsius.It is specific real at of the invention one
It applies in mode, by environment temperature linear heat locating for groove to 400~800 degrees Celsius in 60 seconds~140 seconds.
In specific implementation, environment temperature locating for groove can for example select 450 degrees Celsius, and 480 degrees Celsius, 550 is Celsius
Degree, 600 degrees Celsius, 660 degrees Celsius, 640 degrees Celsius, 750 degrees Celsius etc..The time of linear heating environment temperature such as 70 seconds,
75 seconds, 80 seconds, 95 seconds, 103 seconds, 115 seconds, 125 seconds, 130 seconds.
It further include the technique step that oxygen-containing gas is passed through to the environment where groove in the rapid thermal oxidation process
Suddenly, the oxygen-containing gas such as oxygen (O2), ozone (O3) etc. with oxidability gas.
In the rapid thermal oxidation process, the dielectric layer in the groove is in high-temperature oxygen environment, high temperature
Oxygen molecule concentration under environment is larger and molecular activity is higher, and the molecule original due to the groove dielectric layer edge
Structure is more loose, therefore the free state silicon ion generated during the CMP will be substantially oxidized in this course, aoxidizes
Original oxide molecule recombines to form stable point at high temperature in the dielectric layer in oxide and groove generated afterwards
Sub-key so that the oxide structure of the edge of the dielectric layer in the groove by it is original it is loose become to consolidate, it is fine and close, thus
Dielectric layer in the groove corner damage can effectively be repaired, the process of the high-temperature oxydation be generally also commonly called as
High temperature quenching.
Finally, removal hard mask layer.The technique of the hard mask layer is removed for example, by using wet etching (Wet Etch), institute
The chemical etching reagent used is different according to the difference of hard mask material layer, is the known technology of those skilled in the art.
Embodiment three
In this embodiment, the part different from above embodiments will be described, same section will not be described in great detail.
The dielectric layer 13 has the bottom surface and top surface that are oppositely arranged, which is relative to top surface further from first metal
The side of layer 18.Preferably, the thickness range of the dielectric layer is 0.3 micron to 5 microns, it is highly preferred that the thickness of the dielectric layer
About 1 micron of degree.In the step of forming dielectric layer 13, firstly, by lithographic and etching technics in first wafer 11
The contact bore region 12 of front face surface forms a groove, and deposition and fill process is recycled to form the dielectric layer in the groove
13, it is subsequent can also by grinding technics to the dielectric layer 13 carry out grinding make its planarization.After above-mentioned processing step, shape
At the bottom surface of the dielectric layer 13 be located inside first wafer 11, the top surface of the dielectric layer 13 is being higher than first wafer 11 just
Face, the thickness of the dielectric layer 13 are about 1 micron.
Example IV
In this embodiment, the part different from above embodiments will be described, same section will not be described in great detail.
The dielectric layer 13 has the bottom surface and top surface that are oppositely arranged, which is relative to top surface further from first metal
The side of layer 18.Preferably, the thickness range of the dielectric layer is 0.3 micron to 5 microns, it is highly preferred that the thickness of the dielectric layer
About 1 micron of degree.In the step of forming dielectric layer 13, firstly, by depositing operation in the positive of first wafer 11
Contact forms the dielectric layer 13 on 12 surface of bore region, subsequent to carry out grinding to the dielectric layer 13 by grinding technics and make
It is planarized.After above-mentioned processing step, the bottom surface of the dielectric layer 13 of formation connects with the positive level of first wafer 11
Touching, the top surface of the dielectric layer 13 are higher than the front of first wafer 11, and the thickness of the dielectric layer 13 is about 1 micron.
Embodiment five
In this embodiment, the part different from above embodiments will be described, same section will not be described in great detail.
Refering to what is shown in Fig. 3, one end of the contact hole 15 is located in the inside of the dielectric layer 13.Alternatively, the contact hole 15
One end contacted with the top surface of the dielectric layer 13 or one end of the contact hole 15 pass through the dielectric layer 13 and with the dielectric layer 13
Bottom surface contact.Preferably, the thickness range of the dielectric layer is 0.3 micron to 5 microns, it is highly preferred that the thickness of the dielectric layer
About 1 micron.
Embodiment six
In this embodiment, the part different from above embodiments will be described, same section will not be described in great detail.
Refering to what is shown in Fig. 7, after forming pin configuration 17, in the second protective layer of backside deposition of first wafer 11,
And second protective layer is formed by the second protective layer structure 20 by lithographic and etching technics.The material of second protective layer is oxygen
Compound or nitride or nitrogen oxides.
Embodiment seven
In this embodiment, the part different from above embodiments will be described, same section will not be described in great detail.
With reference to shown in Fig. 3-7, which provides a kind of wafer three-dimensional integration lead technique for three-dimensional storage, should
Technique includes one to six any one wafer three-dimensional integration lead technique of above-described embodiment, wherein the semiconductor devices 14 is three
Memory is tieed up, which includes sequence far from the positive three-dimensional storage part layer 141 of the first wafer 11 and the first gold medal
Belong to layer 18, which is located in the three-dimensional storage part layer 141, and one end of the contact hole 15 is contacted with the dielectric layer 13,
The other end of the contact hole 15 is contacted with the first metal layer 18；The three-dimensional storage part layer 141 includes multiple storage unit weights
It stacks and is formed again.Preferably, the thickness of the three-dimensional storage part layer 141 be more than or equal to 1 micron, be less than or equal to 50 microns it
Between, it is more preferably, greater than equal to 5 microns.Preferably, the thickness range of the dielectric layer is 0.3 micron to 5 microns, more preferably
Ground, the thickness of the dielectric layer are about 1 micron.
Embodiment eight
In this embodiment, the part different from above embodiments will be described, same section will not be described in great detail.With reference to Fig. 7
Shown, which provides a kind of wafer three-dimensional integration pin configuration for three-dimensional storage, wherein the structure is by above-mentioned reality
Technique described in one to seven any one of example is applied to be made.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (17)
1. a kind of wafer three-dimensional integration lead technique, which comprises the following steps:
One first wafer is provided, which has the front and back being oppositely arranged, the front at least portion of first wafer
Contact bore region is provided on subregion；
Dielectric layer is formed in the contact bore region, which has the top and bottom being oppositely arranged, and wherein the top surface is
Towards the side of first wafer frontside, which is towards the side of first backside of wafer；
The manufacturing semiconductor devices on the region that the front of first wafer includes at least dielectric layer, the semiconductor devices include connecing
Contact hole, one end of the contact hole are contacted with the dielectric layer, and described one end axially extending in the dielectric layer along contact hole
And between the bottom surface and top surface of the dielectric layer；
By include the semiconductor devices the first wafer semiconductor devices side and the second wafer bonding, and by first wafer
The back side carry out thinned, expose the dielectric layer after being thinned；
The first protective layer is deposited on the backside surface of first wafer after being thinned；
Form metal connecting structure in corresponding with the contact hole position in the back side of first wafer, the metal connecting structure with it is right
The contact hole electrical connection answered；
Drawn in the backside deposition lead metal layer of first wafer, and to the lead metal layer using lithographic and etching technics definition
Cable architecture, the pin configuration are electrically connected with the metal connecting structure.
2. wafer three-dimensional integration lead technique as described in claim 1, which is characterized in that the bottom surface of the dielectric layer be located at this
One inside wafer, the front flush of the top surface of the dielectric layer and first wafer.
3. wafer three-dimensional integration lead technique as described in claim 1, which is characterized in that the bottom surface of the dielectric layer be located at this
One inside wafer, the top surface of the dielectric layer are higher than the front of first wafer.
4. wafer three-dimensional integration lead technique as described in claim 1, which is characterized in that the bottom surface of the dielectric layer and this first
The front flat contact of wafer, the top surface of the dielectric layer are higher than the front of first wafer.
5. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, which is characterized in that in the contact hole
It includes lithographic that the technique of dielectric layer is formed in region, is etched, deposition, one of filling and grinding or any combination thereof.
6. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, which is characterized in that the semiconductor device
Part is three-dimensional storage, which includes three-dimensional storage part layer and first gold medal of the sequence far from first wafer frontside
Belong to layer, which is located in the three-dimensional storage part layer, and one end of the contact hole is contacted with the dielectric layer, the contact hole it is another
One end is contacted with the first metal layer.
7. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, which is characterized in that in first crystalline substance
It includes lithographic that round back side position corresponding with the contact hole, which forms the technique of metal connecting structure, etching, metal filling and change
Learn one of mechanical lapping or any combination thereof.
8. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, which is characterized in that forming lead
After structure, the second protective layer is formed in the second protective layer of backside deposition of first wafer, and by lithographic and etching technics
Structure.
9. wafer three-dimensional integration lead technique as claimed in claim 8, which is characterized in that first protective layer and/or this
The material of two protective layers is oxide or nitride or nitrogen oxides.
10. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, which is characterized in that in the contact hole
Fill metal material.
11. wafer three-dimensional integration lead technique as claimed in claim 10, which is characterized in that the metal material include copper, aluminium,
One of tin or tungsten or any combination thereof.
12. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, which is characterized in that the dielectric layer is
Medium of oxides layer or nitride dielectric layer.
13. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, which is characterized in that first wafer
And/or the material of second wafer be one of silicon in silicon, germanium, three-five semiconducting compound, silicon carbide or insulating substrate or
Any combination thereof.
14. the wafer three-dimensional integration lead technique as described in Claims 1-4 any one, which is characterized in that metal connection
The material of structure includes one of copper, aluminium, tin or tungsten or any combination thereof.
15. a kind of wafer three-dimensional integration lead technique for three-dimensional storage, which includes as claim 1 to 14 is any
Wafer three-dimensional integration lead technique described in one, which is characterized in that the semiconductor devices is three-dimensional storage, three-dimensional storage
Device includes three-dimensional storage part layer and the first metal layer of the sequence far from first wafer frontside, which is located at the three-dimensional and deposits
In memory device layer, one end of the contact hole is contacted with the dielectric layer, and the other end of the contact hole is contacted with the first metal layer；It should
Three-dimensional storage part layer includes multiple storage unit repeatedly stackings and is formed.
16. being used for the wafer three-dimensional integration lead technique of three-dimensional storage as claimed in claim 15, which is characterized in that this three
The thickness for tieing up memory device layer is being more than or equal to 1 micron, is being less than or equal between 50 microns.
17. a kind of wafer three-dimensional integration pin configuration for three-dimensional storage, which is characterized in that the structure is by such as claim
1 to 16 described in any item techniques are made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710775904.5A CN107644841B (en) | 2017-08-31 | 2017-08-31 | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710775904.5A CN107644841B (en) | 2017-08-31 | 2017-08-31 | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107644841A CN107644841A (en) | 2018-01-30 |
| CN107644841B true CN107644841B (en) | 2019-01-01 |
Family
ID=61110156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710775904.5A Active CN107644841B (en) | 2017-08-31 | 2017-08-31 | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107644841B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109817573B (en) * | 2019-01-22 | 2022-06-03 | 长江存储科技有限责任公司 | Memory and forming method thereof |
| CN109860103A (en) * | 2019-01-22 | 2019-06-07 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
| CN111244099A (en) * | 2020-01-20 | 2020-06-05 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2930840B1 (en) * | 2008-04-30 | 2010-08-13 | St Microelectronics Crolles 2 | METHOD FOR RECOVERING CONTACT ON A REAR-FACING LIGHT CIRCUIT |
| US9219032B2 (en) * | 2012-07-09 | 2015-12-22 | Qualcomm Incorporated | Integrating through substrate vias from wafer backside layers of integrated circuits |
| CN104810396B (en) * | 2014-01-23 | 2018-02-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method |
-
2017
- 2017-08-31 CN CN201710775904.5A patent/CN107644841B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107644841A (en) | 2018-01-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107644837B (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| CN107644838B (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| CN107887395B (en) | NAND memory and preparation method thereof | |
| CN111211133B (en) | Memory device using comb routing structure to reduce metal line loading | |
| US6897125B2 (en) | Methods of forming backside connections on a wafer stack | |
| KR100656218B1 (en) | System on a package fabricated on a semiconductor or dielectric wafer | |
| TWI416679B (en) | Semiconductor structure and manufacturing method thereof | |
| US8283207B2 (en) | Methods for forming through-substrate conductor filled vias, and electronic assemblies formed using such methods | |
| US7645701B2 (en) | Silicon-on-insulator structures for through via in silicon carriers | |
| US8796138B2 (en) | Through substrate vias | |
| US20110057321A1 (en) | 3-d multi-wafer stacked semiconductor structure and method for manufacturing the same | |
| TW200812063A (en) | Semiconductor integrated circuit devices having high-Q wafer back-side capacitors | |
| US20150332968A1 (en) | Semiconductor Having A High Aspect Ratio Via | |
| TW201635468A (en) | Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner scheme | |
| CN104040684B (en) | High-performance wire structures on thick sheet | |
| CN107644841B (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| US20030068884A1 (en) | Inductance and via forming in a monolithic circuit | |
| JPH11251316A (en) | Manufacture of multi-chip semiconductor device | |
| US8940631B1 (en) | Methods of forming coaxial feedthroughs for 3D integrated circuits | |
| CN104867865B (en) | A kind of wafer three-dimensional integration lead technique | |
| CN107644839B (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| CN107644836A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| CN107644840A (en) | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage | |
| CN107068617A (en) | The method of semiconductor devices and its manufacture method and dividing semiconductor device | |
| KR100694424B1 (en) | Multi chip package device and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |