KR20160118114A

KR20160118114A - A semiconductor device and a method of fabricating the same

Info

Publication number: KR20160118114A
Application number: KR1020150072028A
Authority: KR
Inventors: 강주헌; 차준호; 현충일
Original assignee: 삼성전자주식회사
Priority date: 2015-03-31
Filing date: 2015-05-22
Publication date: 2016-10-11

Abstract

A semiconductor memory device according to an embodiment of the present invention includes a substrate, a stacked structure including vertically stacked gate electrodes on the substrate, a vertical channel portion passing through the gate electrodes, A common source plug disposed on the substrate, the common source plug electrically connected to the impurity region, and the cell contact plug connected to each of the gate electrodes, wherein an upper portion of the common source plug and the cell contact plug The upper portions of the electrodes may be located at different levels.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device and a method of fabricating the same,

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the same.

In order to satisfy excellent performance and low cost, it is required to increase the degree of integration of semiconductor devices. In particular, the degree of integration of a semiconductor memory device is an important factor in determining the price of a product. Since the degree of integration of the conventional two-dimensional semiconductor memory device is mainly determined by the area occupied by the unit memory cell, the degree of integration of the fine pattern formation technology is greatly affected. However, the integration of the two-dimensional semiconductor memory device is increasing, but is still limited, because of the need for expensive equipment to miniaturize the pattern.

In order to overcome such a limitation, a three-dimensional semiconductor memory device having three-dimensionally arranged memory cells has been proposed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device with improved reliability.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device with improved reliability.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

The upper portions of the cell contact plugs may be located at a level higher than the upper portion of the common source plug.

And a first isolation insulating film and a second isolation insulating film sequentially stacked on the stacked structure, wherein the first isolation insulating film is an uppermost insulating film among the films penetrated by the common source plug, It may be the uppermost insulating film among the films penetrated by the contact plugs.

The second isolation insulating film may extend over the common source plug to cover the upper surface of the common source plug.

The upper portion of the vertical channel portion may be located at a lower level than the upper portions of the common source plug and the cell contact plugs.

Wherein the substrate includes a cell region in which the vertical channel portion is disposed, a contact region in which the cell contact plugs are arranged, and the peripheral circuit region, A peripheral gate pattern disposed on the substrate in the peripheral circuit region, a peripheral impurity region provided in the substrate on one side of the peripheral gate pattern, and a peripheral impurity region disposed on the substrate, electrically connected to the peripheral gate pattern and the peripheral impurity region And may further include peripheral contact plugs connected thereto.

The upper portions of the peripheral contact plugs may be located at the same level as the upper portions of the cell contact plugs.

A semiconductor memory device according to another embodiment of the present invention includes a substrate including a cell region, a stacked structure including gate electrodes vertically stacked on the substrate in the cell region, a vertical channel portion passing through the gate electrodes, A common source plug disposed on the substrate and electrically connected to the impurity region, and a cell contact plug connected to each of the gate electrodes, wherein the impurity region is provided in the vertical The upper portion of the channel portion, the upper portion of the common source plug, and the upper portions of the cell contact plugs may be located at different levels.

The upper portion of the vertical channel portion may be located at a lower level than the upper portion of the common source plug.

The upper portion of the vertical channel portion may be located at a lower level than the upper portion of the common source plug and the upper portion of the common source plug may be located at a lower level than the upper portions of the cell contact plugs.

The vertical channel portion, the common source plug, and the upper portions of the cell and the peripheral contact plugs included in the semiconductor memory device according to the embodiment of the present invention may be disposed at different levels. Thus, the reliability of the semiconductor memory device can be further improved.

1 is a plan view showing a semiconductor memory device according to embodiments of the present invention.
FIG. 2 is a cross-sectional view taken along the line I-I 'and II-II' of FIG. 1, illustrating a semiconductor memory device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view taken along the line I-I 'and II-II' of FIG. 1, illustrating a semiconductor memory device according to another embodiment of the present invention.
FIGS. 4A to 4M are cross-sectional views taken along line I-I 'and II-II' of FIG. 1, illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.
5 is a schematic block diagram illustrating an example of an electronic system including a semiconductor memory device formed in accordance with embodiments of the present invention.
6 is a schematic block diagram illustrating an example of a memory system having a semiconductor memory device formed in accordance with embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

1 is a plan view showing a semiconductor memory device according to embodiments of the present invention. FIG. 2 is a cross-sectional view taken along the line I-I 'and II-II' of FIG. 1, illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIGS. 1 and 2, a laminated structure ST may be disposed on a substrate 10. In FIG. The stacked structure ST may be disposed on the cell array region CR and the contact region WCTR of the substrate 10. [ The laminated structure ST may extend in one direction D3. The substrate 10 may be a single crystal epitaxial layer grown on a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline silicon substrate.

Peripheral transistors may be disposed on the substrate 10 of the peripheral circuit region PR. Peripheral transistors may include PMOS transistors and NMOS transistors. The PMOS transistor and the NMOS transistor may be provided on the active region of the substrate 10 defined by the device isolation film. The PMOS and NMOS transistors may constitute word line drivers, sense amp, row and column decoders, and control circuits.

In one embodiment, the peripheral transistors may include a peripheral gate insulation pattern 21 and a peripheral gate pattern 22, which are sequentially stacked on the substrate 10 of the peripheral circuit region PR. The peripheral gate pattern 22 may be used as gate electrodes of peripheral transistors constituting a peripheral circuit, and may be formed of an impurity-doped polysilicon or a metal material. Peripheral impurity regions 23 used as the source and drain regions of the peripheral transistors may be provided in the active region of the substrate 10 on both sides of the peripheral gate pattern 22. [

A peripheral insulating pattern 30 covering the peripheral transistors on the substrate 10 may be provided. The peripheral insulating pattern 30 may be formed of a silicon oxide film and the peripheral circuits of the peripheral circuit region PR may be buried by the peripheral insulating pattern 30. [

The cell array region CR of the substrate 10 and the stacked structure ST disposed on the contact region WCTR may include the insulating patterns 111a to 117a and the gate electrodes 140. [ The insulating patterns 111a-117a and the gate electrodes 140 may be alternately and repeatedly stacked in a second direction D2 perpendicular to the substrate 10. [ A gate insulating pattern 11a may be interposed between the substrate 10 and the laminated structure ST. The gate insulating pattern 11a may include, for example, a silicon oxide film.

The gate electrodes 140 are stacked in the second direction D2 and extend in the one direction D3. The lengths of the gate electrodes 140 to the one direction D3 may be different from each other. For example, the length of the gate electrodes 140 may become shorter as the distance from the substrate 10 increases. That is, the gate electrodes 140 on the contact region WCTR may have a stepped shape. Accordingly, the ends of each of the gate electrodes 140 can be exposed on the contact region WCTR of the substrate 10. [

The gate electrodes 140 may include a ground selection gate electrode 141, cell gate electrodes 142-146, and a string selection gate electrode 147. [ In detail, the ground selection gate electrode 141 can correspond to the lowermost gate electrode. The string select gate electrode 147 may correspond to the top gate electrode. Cell gate electrodes 142 to 126 may be disposed between the ground selection gate electrode 141 and the string selection gate electrode 147. The gate electrodes 140 may be formed of a conductive material such as doped silicon, a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride) , Tantalum, and the like).

Each of the insulating patterns 111a-117a may be provided between the gate electrodes 140. [ The insulating patterns 111a-117a are stacked in the second direction D2 and extend in the one direction D3. The lengths of the respective insulating patterns 111a-117a in the one direction D3 may be different from each other. For example, the length of the insulating patterns 111a-117a may become shorter as the distance from the substrate 10 increases. The insulating patterns 111a-117a may have the same length as each of the gate electrodes 140 disposed under each of the insulating patterns 111a-117a. For example, the lowermost insulating pattern 111a may extend in one direction D3 with the same length as the lowermost gate electrode 141. [ Accordingly, the insulating patterns 111a-117a can cover the ends of each of the gate electrodes 140 exposed on the contact region WCTR.

The interlayer insulating pattern 125a may be disposed on the contact region WCTR and the peripheral circuit region PR of the substrate 10. [ In detail, the interlayer insulating pattern 125a may cover the ends of the insulating patterns 111a-116a disposed on the contact area WCTR of the substrate 10. [ The interlayer insulating pattern 125a may cover the upper surface of the peripheral insulating pattern 30 on the peripheral circuit region PR of the substrate 10. [ The interlayer insulation pattern 125a may be located at the same level as the upper surface of the uppermost insulation pattern 117a. The interlayer insulating pattern 125a may include, for example, a silicon oxide film.

A vertical channel portion VC that electrically connects the substrate 10 through the stacked structure ST on the cell array region CR of the substrate 10 may be provided. The plurality of vertical channel portions VC may be arranged in a zigzag manner in one direction D3. The vertical channel portion VC may conformally cover the side wall and the bottom surface of the channel trench 120 passing through the laminated structure ST. The vertical channel portion VC may be composed of a single film or a plurality of films. The vertical channel portion (VC) may be one of a polycrystalline silicon film, an organic semiconductor film, and carbon nanostructures.

And may further include a semiconductor column SP between the substrate 10 and the vertical channel portion VC. The semiconductor pillar SP is grown from the substrate 10 by selective epitaxial growth using the substrate 10 exposed on the bottom surface of the channel trench 120 as a seed, . The semiconductor column SP may be, for example, an intrinsic semiconductor or a semiconductor having a p-type conductivity.

A vertical insulating film VI may be provided between the vertical channel portion VC and the stacked structure ST. The vertical insulating film VI may conformally cover a part of the side wall and the bottom surface of the channel trench 120. The vertical insulating film VI may include a single film or a plurality of films. For example, the vertical insulating film VI may include at least one of thin films (for example, a tunnel insulating film, a capping insulating film, and a blocking insulating film) used as a memory element of a charge trap type nonvolatile memory transistor. The vertical insulating film VI may include at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. A horizontal insulating film PI may be interposed between the vertical insulating film VI and the gate electrodes 140. [ In detail, the horizontal insulating film PI on the sidewalls of the gate electrodes 140 may extend on the upper and lower surfaces of the gate electrodes 140. [ The horizontal insulating film PI may be a blocking insulating film of a charge trap type nonvolatile memory transistor. In this case, the horizontal insulating film PI may be a silicon oxide film. Alternatively, the horizontal insulating film PI may further include a trap insulating film or a tunnel insulating film. The vertical insulating film (VI) and the horizontal insulating film (PI) can constitute a data storage film.

Insulation pillar 121 may be provided in channel trench 120. Insulation pillar 121 may comprise an insulating material (e.g., silicon oxide or silicon nitride). The conductive pads D may be disposed in the upper portion of the vertical channel portion VC, the vertical insulating film VI, and the insulating pillar 121. [ The conductive pad D may include a conductive material or an impurity of a different conductive type from the vertical channel portion VC. The upper surface of the vertical channel portion VC including the conductive pad D and the upper surface of the uppermost insulating pattern 117a may be located at the same level.

The impurity region 20 may be provided in the substrate 10 of the cell array region CR and the contact region WCTR. The impurity region 20 may extend in the substrate 10 in one direction D3. The impurity region 20 may be a common source line. In this case, the impurity region 20 may have a different conductivity type from the substrate 10.

The first isolation insulating film 131 may be disposed on the front surface of the substrate 10. Specifically, the first isolation insulating film 131 covers the upper surface of the uppermost insulating pattern 117a on the cell array region CR, and the interlayer insulating pattern 125a on the contact region WCTR and the peripheral circuit region PR Can be covered. The first isolation insulating film 131 covers the upper portion of the vertical channel portion VI and can contact the upper surface of the conductive pad D. The first isolation insulating film 131 may include, for example, an insulating material (a silicon oxide film).

The spacer 149, the barrier pattern 151a, and the common source plug 153a may be disposed in the common source trench 133 which penetrates the laminated structure ST and exposes the impurity region 20. [ Specifically, the common source trench 133 penetrates the cell array region CR of the substrate 10 and the first isolation insulating film 131 and the laminated structure ST on the contact region WCTR to form the impurity region 20 Can be exposed. The common source trench 133 is in the form of a line extending in one direction D3 and may be arranged in the first direction D1.

The spacers 149 may be disposed on the sidewalls of the common source trenches 133. The spacer 149 may be, for example, a silicon oxide film. The barrier pattern 151a may conformally cover the sidewalls of the spacers 149 in the common source trench 133 and the bottom surface of the common source trench 133. [ That is, the barrier pattern 151a may have a 'U' shape. The barrier pattern 151a may include, for example, a metal nitride film such as titanium nitride or tantalum nitride.

The common source plug 153a can completely fill the common source trench 133. [ The common source plug 153a may vertically penetrate the first isolation insulating film 131 and the stacked structure ST and may have a line shape extending in one direction D3. The plurality of common source plugs 153a may be arranged in the first direction D1. Although not shown in the drawing, the common source plug 153a may be electrically connected to a dummy vertical channel portion passing through the laminated structure ST. The common source plug 153a may comprise, for example, a metal (tungsten, copper or aluminum) or a transition metal (titanium or tantalum).

The upper surface of the common source plug 153a may be located at the same level as the upper surface of the first isolation insulating film 131. [ That is, the first isolation insulating film 131 may be the uppermost film among the films through which the common source plug 153a passes. The upper surface of the common source plug 153a may be located at a higher level than the upper surface of the vertical channel portion VC.

A second isolation insulating film 155 may be provided on the entire surface of the first isolation insulating film 131. The second isolation insulating film 155 may cover the upper surface of the common source plug 153a, the barrier pattern 151a and the spacer 149. [ The second isolation insulating film 155 may include, for example, an insulating material (a silicon oxide film, a silicon nitride film, or a silicon oxynitride film).

The first insulating film 131 and the interlayer insulating film 125a are formed on the contact region WCTR of the substrate 10 and contact the ends of the gate electrodes 140, Contact plugs (CGCP) can be placed. Then, the second isolation insulating film 155, the first isolation insulating film 131, and the interlayer insulating pattern 125a are passed through the peripheral circuit region PR of the substrate 10, Peripheral contact plugs PGCP that contact the impurity region 23 can be disposed. The cell contact plugs CGCP and the peripheral contact plugs PGCP may include a conductive material and may include, for example, tungsten (W), copper (Cu), or aluminum (Al).

The upper surfaces of the cell contact plugs CGCP and the peripheral contact plugs PGCP may be located at the same level as the upper surface of the second isolation insulating film 155. [ And, the upper surfaces of the cell contact plugs CGCP and the peripheral contact plugs PGCP may be located at a higher level than the upper surface of the common source plug 153a. That is, the upper portion of the vertical channel portion VC may be located at a lower level than the upper portion of the common source plug 153a, and the upper portion of the common source plug 153a may be connected to the cell contact plugs CGCP and peripheral contact plugs Lt; RTI ID = 0.0 > PGCP). &Lt; / RTI >

Contact pads 159 that contact the cell contact plugs CGCP and the peripheral contact plugs PGCP may be disposed on the second isolation insulating film 155. [ An additional isolation insulating film 160 covering the contact pads 159 may be disposed on the entire surface of the second isolation insulating film 155. A bit line contact plug BLCP which sequentially passes through the first, second and additional isolation insulating films 131, 155 and 160 and contacts the conductive pad D is formed on the cell array region CR of the substrate 10 . A bit line BL connected to the bit line contact plug BLCP may be disposed on the additional isolation insulating film 160. The plurality of bit lines BL may be arranged in one direction D3 while traversing the stacked structure ST in the first direction D1.

The first contacts MC1 and the second contacts MC2 that penetrate the additional isolation insulating film 160 may be disposed on the contact region WCTR and the peripheral circuit region PR of the substrate 10. [ Global word lines GWL may be disposed on the additional isolation insulating film 160 to contact the first contacts MC1 and the second contacts MC2, respectively.

FIG. 3 is a cross-sectional view taken along the line I-I 'and II-II' of FIG. 1, illustrating a semiconductor memory device according to another embodiment of the present invention.

2 and 3, the upper surface of the vertical channel portion VC passes through the first isolation insulating film 131 and the stacked structure ST on the cell array region CR of the substrate 10, May be located at a lower level than the upper surface of the common source plug 153a connected to the common source plug 30a. The cell contact plugs (not shown) connected to the gate electrodes 140 through the second isolation insulating film 155, the first isolation insulating film 131, and the interlayer insulating pattern 125a on the contact region WCTR of the substrate 10 CGCP) may be located at a higher level than the common source plug 153a. Then, the peripheral gate pattern (first gate insulating film) 140 is formed through the additional isolation insulating film 160, the second isolation insulating film 155, the first isolation insulating film 131 and the interlayer insulating pattern 125a on the peripheral circuit region PR of the substrate 10 22 and the peripheral contact plugs PGCP connected to the peripheral impurity regions 23 may be located at a level higher than the upper surface of the cell contact plugs CGCP. That is, the upper portion of the vertical channel portion VC may be located at a lower level than the upper portion of the common source plug 153a, and the upper portion of the common source plug 153a may be connected to the cell contact plug CGCP and the peripheral contact plugs PGCP As shown in FIG. And, the upper portion of the cell contact plugs CGCP may be located at a lower level than the upper portion of the peripheral contact plugs PGCP.

FIGS. 4A to 4M are cross-sectional views taken along line I-I 'and II-II' of FIG. 1, respectively, illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 4A, the substrate 10 may include a cell array region CR, a contact region WCTR, and a peripheral circuit region PR. The active region of the substrate 10 can be defined by an element isolation film. It is possible to form peripheral circuits for writing and reading the memory cells on the substrate 10 of the peripheral circuit region PR.

The peripheral circuit region PR may be formed of a word line driver, a sense amplifier, row and column decoders, and control circuits. According to one embodiment, peripheral transistors constituting peripheral circuits may be formed on the substrate 10 of the peripheral circuit region PR, as shown in the figure. The substrate 10 may be a single crystal epitaxial layer grown on a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline silicon substrate.

In one embodiment, the peripheral transistors may be formed as follows. The peripheral gate insulating film and the peripheral gate film may be sequentially stacked on the entire surface of the substrate 10. [ The peripheral gate insulating film may be used as a gate insulating film of peripheral transistors, or may be a silicon oxide film formed by a thermal oxidation process. The laminated peripheral gate insulating film and the peripheral gate film may be sequentially patterned to form the peripheral gate insulating pattern 21 and the peripheral gate pattern 22 sequentially stacked on the substrate 10. [ The peripheral gate pattern 22 may be used as gate electrodes of peripheral transistors constituting a peripheral circuit, and may be formed of an impurity-doped polysilicon or a metal material. Subsequently, peripheral impurity regions 23 used as the source and drain regions of the peripheral transistors in the active region of the substrate 10 on both sides of the peripheral gate pattern 22 can be formed. On the other hand, when the peripheral gate pattern 22 is formed, the bottom gate insulating film 11 may not be patterned. That is, the lower gate insulating film 11 can cover the upper surface of the substrate 10 in the cell array region CR.

Next, the peripheral insulating pattern 30 may be formed on the substrate 10 on which the peripheral transistors are formed. The peripheral insulating pattern 30 may be formed of a silicon oxide film and the peripheral circuits of the peripheral circuit region PR may be buried by the peripheral insulating pattern 30. [

The peripheral insulating pattern 30 may be formed by forming peripheral circuits in the peripheral circuit region PR and then depositing an insulating film on the entire surface of the substrate 10 and removing the insulating film from the cell array region CR. That is, the peripheral insulating pattern 30 may be locally formed on the peripheral circuit region PR to expose the substrate 10 of the cell array region CR and the contact region WCTR.

The peripheral etch stop layer 32 may be formed on the peripheral insulation pattern 30 as shown in FIG. The peripheral etch stop film 32 may be formed of a material having an etch selectivity (e.g., a silicon nitride film) with respect to the peripheral insulating pattern 30. [

The laminated structure ST can be formed on the front surface of the substrate 10 on which the peripheral insulating pattern 30 is formed. That is, the laminated structure ST may be formed on the cell array region CR, the contact region WCTR, and the peripheral circuit region PR of the substrate 10. [ The stacked structure ST may include sacrificial films SC and insulating films 111-117. Sacrificial films (SC) and insulating films (111-117) may alternately and repeatedly be stacked on the substrate (10). The sacrificial layers SC may include a material having an etching selectivity to the insulating films 111-117. For example, the sacrificial films SC may be a silicon nitride film, and the insulating films 111-117 may be a silicon oxide film.

Referring to FIG. 4B, the first trenches 120 may be formed by etching the stacked structure ST on the cell array region CR of the substrate 10. [ Specifically, the first trenches 120 are formed on the surface of the contact region WTCR and the peripheral circuit region PR of the substrate 10 and on the front surface of the cell array region CR, (Not shown), and sequentially etching the insulating films 111-117 and the sacrificial films SC of the multilayer structure ST exposed to the mask pattern. The etching process for forming the first trenches 120 can be performed until the substrate 10 is exposed on the upper surface. Although not shown in the drawings, the upper surface of the substrate 10 may be recessed by overetching.

Referring to FIG. 4C, the semiconductor pillars SP may be formed on the substrate 10 exposed to the first trenches 120. In detail, the semiconductor pillars SP are selectively grown from the substrate 10 by selective epitaxial growth using the substrate 10 exposed to the first trenches 120 as a seed, . The semiconductor column SP may be, for example, an intrinsic semiconductor or a semiconductor having a p-type conductivity.

A vertical insulating film VI that conformally covers the sidewalls of the first trenches 120 on which the semiconductor pillars SP are formed and a part of the upper surface of the semiconductor pillars SP may be formed. The vertical insulating film VI may be formed using, for example, chemical vapor deposition (CVD) and atomic layer deposition (ALD). The vertical insulating film VI may include a single film or a plurality of films. For example, the vertical insulating film VI may include at least one of thin films (for example, a data storage film) used as a memory element of a charge trap type nonvolatile memory transistor. The vertical insulating film VI may include at least one of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

A vertical channel portion VC that conformally covers the sidewalls of the vertical insulating film VI and the upper surface of the semiconductor pillars SP may be formed in the first trenches 120. [ The vertical channel portion (VC) may be formed using, for example, chemical vapor deposition (CVD) and atomic layer deposition (ALD). The vertical channel portion (VC) may be, for example, one of a polysilicon film, an organic semiconductor film and carbon nanostructures.

After forming the vertical channel portion (VC), a further hydrogen annealing step may be performed in which the vertical channel portion (VC) is heat-treated in a gas atmosphere containing hydrogen or deuterium. In this process, crystal defects present in the vertical channel portion VC can be healed by the hydrogen annealing step.

The insulating pillars 121 can be formed by filling the first trenches 120 formed with the vertical channel portions VC. The insulating pillars 121 may be formed using, for example, SOG (SOG) technology. Insulation pillar 121 may comprise an insulating material (e.g., silicon oxide or silicon nitride).

The conductive pads D may be formed on the vertical insulating film VI, the vertical channel portion VC, and the insulating pillar 121. For example, the conductive pad D may be formed by recessing the upper region of the vertical insulating film VI, the vertical channel portion VC, and the insulating column 121, and then filling the recessed region with a conductive material . As another example, the conductive pad D may be formed by doping an upper region of the vertical insulating film VI, the vertical channel portion VC, and the insulating column 121 with the impurity of the conductive type different from the vertical channel portion VC .

Referring to FIG. 4D, a mask pattern 123 may be formed on the cell array region CR of the substrate 10. The stacked structure ST on the substrate 10 of the contact region WCTR may be formed in a stepped structure by etching the sacrificial films SC and the insulating films 117 exposed to the mask pattern 123 .

In order to form the laminated structure ST in a stepped structure, the process of reducing the horizontal area of the mask pattern 123 and the process of reducing the horizontal area of the mask pattern 123 are performed, and the insulating films 111-117 and the sacrificial films The process of reducing the amount of SC etched can be repeated.

In detail, the mask pattern 123 formed at the beginning is formed on a part of the cell array region CR and the contact region WCTR of the substrate 10 and is formed on the peripheral circuit region PR of the substrate 10 The uppermost insulating film 117 and a portion of the uppermost insulating film 117 on the contact region WCTR of the substrate 10 can be exposed. All of the insulating films 111-117 and the sacrificial films SC on the substrate 10 in the peripheral circuit region PR exposed to the mask pattern 123 and the contact regions exposed in the mask pattern 123 The insulating films 111-117 and the sacrificial films SC on a part of the wafer WCTR can be removed. The peripheral circuit pattern 30 can be exposed on the substrate 10 of the peripheral circuit area PR and a part of the upper surface of the substrate 10 on the contact area WCTR can be exposed.

Subsequently, the horizontal area of the mask pattern 123 is reduced, and the insulating films 111-117 and the sacrificial layer (not shown) on a part of the contact region WCTR of the substrate 10 exposed to the reduced- (SC) can be etched. In this case, in the second etching process, less etching can be performed than the etching of the insulating films 111-117 and the sacrificial films SC in the first etching process. For example, in the second etching process, the insulating films 112-117 and the sacrificial films SC stacked on the uppermost insulating film 111 are etched by leaving the lowermost sacrificial film SC and the lowermost insulating film 111, The upper surface of the lowermost insulating film 111 can be exposed.

When the amount of etching of the insulating films 111-117 and the sacrificial films SC is reduced while reducing the horizontal area of the mask pattern 123 in this manner, The ends of each of the insulating films 111-117 that remain on the cell array region CR and cover each of the sacrificial films SC and the sacrificial films SC may be positioned horizontally at different positions have. In other words, as the sacrificial films SC and the insulating films 111-117 are further away from the substrate 10, the horizontal area can be reduced.

After the etching process is completed, the mask pattern 123 can be removed. On the other hand, there may be a step between the structures formed in the laminated structure ST on the substrate 10 of the cell array region CR and the contact region WCTR and the peripheral circuit region PR. For example, the upper surface of the uppermost insulating film 117 of the laminated structure ST and the upper surface of the peripheral insulating pattern 30 on the peripheral circuit region CR may have different heights.

Referring to FIG. 4E, an interlayer insulating layer 125 may be formed on the front surface of the substrate 10. [ The interlayer insulating film 125 may be formed on the structures of the stacked structure ST and the peripheral circuit region PR of the cell array region CR and the contact region WCTR. The upper surface of the interlayer insulating film 125 may have a step due to the step difference between the structures formed on the substrate 10. [ For example, the upper surface of the interlayer insulating film 125 on the cell array region CR is located at a higher level than the upper surface of the interlayer insulating film 125 on the contact region WCTR and the peripheral circuit region PR, The upper surface of the interlayer insulating film 125 on the first interlayer insulating film PR may be located at the lowest level. The upper surface of the interlayer insulating film 125 on the peripheral circuit region PR may have an inclined surface gradually lowered from the cell array region CR of the substrate 10 to the peripheral circuit region PR.

The interlayer insulating layer 125 may be formed by a method such as PVD (Physical Vapor Deposition) method, CVD (Chemical Vapor Deposition) method, SACVD (Sub-Atmospheric Chemical Vapor Deposition) method, LPCVD (Low Pressure Chemical Vapor Deposition) Enhanced Chemical Vapor Deposition (HDP) or High Density Plasma Chemical Vapor Deposition (HDP).

The interlayer insulating film 125 may be formed of a material having etch selectivity with respect to the sacrificial films SC in the process of removing the sacrificial films SC which is performed in the subsequent process. The interlayer insulating film 125 may be formed of a high density plasma (HDP) oxide film, TEOS (TetraEthylOrthoSilicate), PE-TEOS (Plasma Enhanced TetraEthylOrthoSilicate), O 3 -TeOS (O 3 -Tetra Ethyl Ortho Silicate) A phosphosilicate glass (PSG), a borosilicate glass (BSG), a borophosphosilicate glass (BPSG), a fluoride silicate glass (FSG), a spin on glass (SOG), a toned silaZene or a combination thereof. Further, the interlayer insulating film 125 may include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

A polishing stop film 127 may be formed on the interlayer insulating film 125. The polishing stopper film 127 is a sacrificial film for preventing the dishing phenomenon from occurring in the contact region WCTR and the peripheral circuit region PR in the chemical mechanical polishing process of the interlayer insulating film 125.

The abrasive stopper film 127 may use a deposition process such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The polishing stop film 127 may be formed of a material having a lower removal rate than the removal rate of the interlayer insulating film 125. The polishing stop film 127 may be formed of a material such as a silicon nitride film (SiN), a silicon oxynitride film (SiON), a silicon carbide (SiC), a silicon oxycarbide (SiOC), a conductive film, SiLK, a black diamond, CORAL, an anti-reflective coating film, or a combination thereof.

4F, a part of the interlayer insulating film 125 of the cell array region CR is removed so that a step between the interlayer insulating film 125 on the cell array region CR and the interlayer insulating film 125 on the contact region WCTR Can be reduced. A photoresist pattern (not shown) for exposing the cell array region CR is formed on the polishing stopper film 127 and a photoresist pattern is formed on the polishing stopper film 127 and the interlayer insulating film 125 A part can be etched. The upper portion of the interlayer insulating film 125 on the contact region WCTR can be projected beyond the upper portion of the interlayer insulating film 125 on the cell array region CR and the peripheral circuit region PR.

Referring to FIG. 4G, a planarization process may be performed on the interlayer insulating film 125 to form the interlayer insulating pattern 125a. The planarization process can be performed until the upper surface of the conductive pad D on the cell array region CR is exposed. The interlayer insulating pattern 125a may be formed on the contact region WCTR and the peripheral circuit region PR of the substrate 10. [

The polishing stopper film 127 formed on the contact area WCTR is removed so that the upper surface of the interlayer insulating pattern 125a is exposed and the polishing stopper film 127 on the peripheral circuit area PR remains can do. On the other hand, since the polishing stopper film 127 on the contact region WCTR is removed before the interlayer insulating film 125 during the planarization process, a part of the upper surface of the interlayer insulating pattern 125a on the contact region WCTR is covered with the uppermost insulating pattern 117a. &Lt; / RTI >

After the planarization process, the polishing stop film 127 on the peripheral circuit region PR can be selectively removed.

Referring to FIG. 4H, a first isolation insulating film 131 is formed to expose a portion of the stacked structure ST on the cell array region CR, and the exposed first stacked insulating film 131 is etched using the first isolation insulating film 131 as an etch mask. The second trenches 133 can be formed by etching the structure ST. Referring to FIG. 1, from a plan viewpoint, the second trenches 133 may be in the form of a line extending in one direction D3. The gate insulating pattern 11a, the sacrificial patterns SCa and the insulating patterns 111a-117a may be formed on the substrate 10 as the second trenches 133 are formed. The etching process for forming the second trenches 133 can perform the anisotropic etching process.

The sidewalls of the sacrificial patterns SCa may be exposed to the sidewalls of the second trenches 133. The process for forming the second trenches 133 may be a process for exposing the sacrificial patterns SCa to conduct a selective etching process for selectively removing only the sacrificial patterns SCa in a subsequent process. The first isolation insulating film 131 may be formed of a material having sacrifice patterns SCa and etch selectivity. For example, the first isolation insulating film 131 may include a silicon oxide film.

Referring to FIG. 4I, the sacrifice patterns SCa exposed in the second trenches 133 may be selectively removed to form the recess regions RR. In detail, the recess regions RR can be formed between the vertically stacked insulating patterns 111a-117a. Since the sacrificial patterns SCa include the insulating patterns 111a-117a and the material having etching selectivity, they may not be removed together when the sacrificial patterns SCa are removed. The selective etching may be wet etching and / or isotropic dry etching. For example, if the sacrificial patterns SCa are silicon nitride films and the insulating patterns 111a to 117a are silicon oxide films, the etching may be performed using an etchant containing phosphoric acid.

The upper surfaces and lower surfaces of the insulating patterns 111a to 117a and a part of the outer wall of the vertical insulating film VI and a part of the side walls of the semiconductor column SP can be exposed through the recessed regions RR . The recess regions RR may be gap regions extending horizontally from the second trenches 133 to the insulating patterns 111a to 117a.

Referring to FIG. 4J, a horizontal insulating film PI may be formed to cover the surfaces of the films exposed in the recess regions RR. Specifically, the horizontal insulating film PI has upper surfaces and lower surfaces of the insulating patterns 111a to 117a exposed in the recess regions RR, a part of the outer walls of the vertical insulating film VI, SP on the outer surface of the outer wall.

The horizontal insulating film PI may be composed of one thin film or a plurality of thin films, similar to the vertical insulating film VL. The horizontal insulating film PI may be a blocking insulating film of a charge trap type nonvolatile memory transistor. In this case, the horizontal insulating film PI may be a silicon oxide film. Alternatively, the horizontal insulating film PI may further include a trap insulating film or a tunnel insulating film. The horizontal insulating film PI can be formed using a deposition method with good step coverage. For example, the horizontal insulating layer (PI) may be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

The gate electrodes 140 may be formed by filling the recessed regions RR with a conductive material. The step of forming the gate electrodes 140 may include forming a conductive film (not shown) filling the recessed regions RR and then removing the conductive film formed in the second trenches 133 to form the recessed regions RR Leaving a conductive film locally only within the conductive film. In detail, the conductive film may be formed to fill the second trenches 133, in which case the step of forming the gate electrodes 140 includes anisotropically etching the conductive film in the second trenches 133 can do.

Although not shown in the drawing, the conductive films formed in the second trenches 133 are etched to form the gate electrodes 140 locally in the recess region RR, so that the gate electrodes 140 in the recess regions RR The sidewalls of the gate electrodes 140 exposed to the sidewalls of the second trenches 133 are etched through the sidewalls of the insulating patterns 111a-117a exposed on the sidewalls of the second trenches 133, The recesses may be formed in the recess regions RR. The gate electrodes 140 may comprise a conductive material. For example, the gate electrodes 140 may be formed of doped silicon, a metal (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride) For example, titanium, tantalum, or the like).

Referring to FIG. 4K, impurity regions 20 may be formed in the substrate 10 exposed by the second trenches 133. The impurity regions 20 may be formed through the ion implantation process and may be formed into the substrate 10 through the second trenches 133. The impurity regions 20 may have a different conductivity type than the substrate 10.

Spacers 149 may be formed on the sidewalls of the second trenches 133. The spacer 149 may have a function of electrically insulating between the common source plug 153a and the gate electrodes 140 formed in a subsequent process. The spacer 149 may include an insulating material, and may include, for example, a silicon oxide film.

The barrier film 151 and the conductive film 153 can be formed in the second trenches 133. [ The barrier film 151 conformally covers the upper surface of the first isolation insulating film 131 of the sidewall, the bottom surface and the contact area WCTR of the second trenches 133 and the peripheral circuit area PR . The conductive film 153 may fill the second trenches 133 in which the barrier film 151 is formed and cover the barrier film 151 on the first isolation insulating film 131. The barrier film 151 may be formed, for example, by performing chemical vapor deposition (CVD) or atomic layer deposition (ALD). The conductive film 153 may be formed, for example, by performing chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The barrier film 151 may be formed of, for example, a metal nitride film such as titanium nitride or tantalum nitride. The conductive film 153 may be formed of, for example, a metal (tungsten, copper, or aluminum) or a transition metal (titanium or tantalum).

4L, the conductive film 153 and the barrier film 151 are etched until the upper surface of the first isolation insulating film 131 is exposed, and the barrier patterns 151a and 151b are formed in the second trenches 133, The common source plug 153a can be formed. The barrier pattern 151a may have a " U " shape. The common source plug 153a may be electrically connected to the impurity region 20. [ The etching process may be performed using either a chemical mechanical polishing process or an etch-back process. The upper surface of the common source plug 153a may be formed to be located at a higher level than the upper surface of the vertical channel portion VC.

When the first isolation insulating film 131 is removed in the etching process for forming the common source plug 153a, the upper surface of the common source plug 153a may be disposed at the same level as the upper surface of the vertical channel portion VC have. However, when the first isolation insulating film 131 is removed, the conductive pad D is exposed and the upper portion of the conductive pad D on which the impurities of the etched conductive film 153 are exposed is etched to form the conductive pad D, May be damaged. As a result, the electrical characteristics of the gate electrodes 140 may deteriorate. Therefore, in the embodiment of the present invention, the first isolation insulating film 131 may not be removed in order to prevent the above-described problems.

Referring to FIG. 4M, a second isolation insulating film 155 may be formed on the first isolation insulating film 131. The first isolation insulating film 131 and the interlayer insulating pattern 125a exposed on the second isolation insulating film 155 are formed on the contact region WCTR of the substrate 10 using the second isolation insulating film 155 as an etching mask, The insulating patterns 111a to 117a and the horizontal insulating film PI may be sequentially etched to form the contact holes 154. [ At the same time, the first isolation insulating film 131, the interlayer insulating pattern 125a, and the peripheral insulating pattern 30, which are exposed to the second isolation insulating film 155, are sequentially etched on the peripheral circuit region PR of the substrate 10 The contact holes 154 can be formed. The second isolation insulating film 155 may include, for example, an insulating material (a silicon oxide film, a silicon nitride film, or a silicon oxynitride film).

Each of the contact holes 154 formed on the contact region WCTR may expose the end of each of the gate electrodes 140. [ Each of the contact holes 154 formed in the peripheral circuit region PR may expose either the upper portion of the peripheral gate pattern 22 of the PMOS region and the peripheral impurity regions 23 of the NMOS region.

Each of the gate electrodes 140 on the contact region WCTR and the peripheral gate pattern 22 and the substrate 10 of the peripheral circuit region PR have different stepped portions. Accordingly, the time at which each of the contact holes 154 is formed may be different from each other. For example, the contact hole 154 exposing the end of the top gate electrode 147 may be formed earlier than the other contact holes 154, and the peripheral impurity region 23 on the peripheral circuit region PR may be exposed The contact holes 154 may be finally formed after the other contact holes 154 are formed. The contact holes 154 may be formed through an anisotropic etching process (e.g., dry etching).

Since the gate electrodes 140 and the peripheral gate pattern 22 include the etching target films to be etched to form the contact holes 154 and the material having the etching selectivity, Lt; / RTI > Thus, the contact holes 154 that have already been formed during the formation of the contact holes 154 can be removed from the gate electrodes 140 and / or the peripheral gate patterns 22 ). &Lt; / RTI >

The cell contact plugs CGCP and the peripheral contact plugs PGCP can be formed in the contact holes 154. [ In detail, the cell contact plugs CGCP and the peripheral contact plugs PGCP can be formed by depositing a conductive film (not shown) on the second isolation insulating film 155 to fill the contact holes 154 with conductive material have. The conductive film on the second isolation insulating film 155 is etched until the upper surface of the second isolation insulating film 155 is exposed so that the cell contact plugs CGCP and the peripheral contact plugs (PGCP) can be formed. The upper surfaces of the cell and peripheral contact plugs CGCP and PGCP may be located at a higher level than the upper surface of the common source plug 153a and the upper surface of the vertical channel portion VC. The cell and peripheral contact plugs CGCP and PGCP may include a metal film (e.g., tungsten) and a metal barrier film (e.g., metal nitride). The etching process for forming the cell and peripheral contact plugs CGCP and PGCP may be, for example, an etch-back process or a chemical-mechanical polishing process.

According to one embodiment, the cell and peripheral contact plugs CGCP and PGCP may be formed later than the common source plug 153a. When the cell and the peripheral contact plugs CGCP and PGCP are formed before the common source plug 153a, the etching process for forming the contact holes 154 proceeds before the gate electrodes 140 are formed The etching process proceeds without the etching stopper film. Accordingly, it may be difficult to etch the contact holes 154 having different heights at one time. The upper surfaces of the cell and peripheral contact plugs CGCP and PGCP are connected to the common source plug 153a because the cell and peripheral contact plugs CGCP and PGCP must be formed later than the common source plug 153a, ). &Lt; / RTI >

Referring again to FIG. 2, contact pads 159 may be formed on the second isolation insulating film 155. Contact pads 159 may be disposed on the cell and peripheral contact plugs CGCP and PGCP. An additional isolation insulating film 160 may be formed on the second isolation insulating film 155. The additional isolation insulating film 160 may cover the contact pads 159. The additional isolation insulating film 160 may be, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

The bit line contact plug BLCP on the cell array region CR of the substrate 10 and the first contacts MC1 on the contact region WCTR and the second contacts MC2 on the peripheral circuit region PR, May be formed. The bit line contact plug BLCP is electrically connected to the conductive pad D through the additional isolation insulating film 160 on the cell array region CR, the first insulating isolation pattern 131 and the second isolation insulating films 155, Lt; / RTI > The first contacts MC1 may be connected to the contact pads 159 on the contact area WCTR of the substrate 10 and the second contacts MC2 may be connected to the contact pads 159 Lt; / RTI >

Global word lines GWL are formed on the additional isolation insulating film 160 on the bit line BL and the contact region WCTR and the peripheral circuit region PR on the additional isolation insulating film 160 of the cell array region CR . The bit line BL may be connected to the bit line contact plug BLCP and each global word line GWL may be connected to each of the first contacts MC1 and the second contacts MC2. The bit line and global word lines GWL may be formed, for example, from a metal (e.g., tungsten, copper or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride) , Titanium or tantalum).

5 is a schematic block diagram illustrating an example of an electronic system including a semiconductor memory device formed in accordance with embodiments of the present invention.

5, an electronic system 1100 according to embodiments of the present invention includes a controller 1110, an I / O device 1120, a memory device 1130, an interface 1140, (1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via a bus 1150. The bus 1150 corresponds to a path through which data is moved. A memory device 1130 may include a semiconductor memory device according to embodiments of the present invention.

The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The interface 1140 may perform the function of transmitting data to or receiving data from the communication network. Interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1100 may further include a high-speed DRAM device and / or an SLAM device as an operation memory device for improving the operation of the controller 1110. [

Electronic system 1100 can be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a music player, or any electronic product capable of transmitting and / or receiving information in a wireless environment.

6 is a schematic block diagram illustrating an example of a memory system having a semiconductor memory device formed in accordance with embodiments of the present invention.

Referring to FIG. 6, memory system 1200 includes a storage device 1210. Memory device 1210 may include the semiconductor devices described in the above embodiments. Further, the storage device 1210 may further include other types of semiconductor memory devices (ex, a DRAM device and / or an SRAM device, etc.). The memory card 1200 may include a memory controller 1220 that controls the exchange of data between the host and the storage device 1210.

The memory controller 1220 may include a processing unit 1222 that controls the overall operation of the memory system. The memory controller 1220 may also include an SRAM 1221 (SRAM) that is used as the operating memory of the processing unit 1222. In addition, the memory controller 1220 may further include a host interface 1223, a memory interface 1225, The host interface 1223 may have a data exchange protocol between the memory card 1200 and the host. The memory interface 1225 can connect the memory controller 1220 and the memory device 1210. Further, the memory controller 1220 may further include an error correction block 1224 (Ecc). Error correction block 1224 can detect and correct errors in data read from storage device 1210. [ Although not shown, the memory system 1200 may further include a ROM device for storing code data for interfacing with a host. Memory system 1200 may be used as a portable data storage card. For example, the memory system 1200 may be a memory card 1200, or a solid state drive (SSD).

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

10: substrate
20: impurity region
140: gate electrodes
153a: a common source plug 153a;
VC: vertical channel part
CGCP: Cell contact plugs
PGCP: Peripheral contact plugs

Claims

Board;
A stacked structure including gate electrodes vertically stacked on the substrate;
A vertical channel portion passing through the gate electrodes;
An impurity region provided in the substrate on one side of the laminated structure;
A common source plug disposed on the substrate and electrically connected to the impurity region; And
And a cell contact plug connected to each of the gate electrodes,
Wherein an upper portion of the common source plug and upper portions of the cell contact plugs are located at different levels.

The method according to claim 1,
And the upper portions of the cell contact plugs are located at a higher level than the upper portion of the common source plug.

The method according to claim 1,
And a first isolation insulating film and a second isolation insulating film sequentially stacked on the laminated structure,
Wherein the first isolation insulating film is an uppermost insulating film among the films penetrated by the common source plug and the second isolation insulating film is an uppermost insulating film among the films penetrated by the cell contact plugs.

The method of claim 3,
And the second isolation insulating film extends onto the common source plug to cover the upper surface of the common source plug.

The method according to claim 1,
And an upper portion of the vertical channel portion is located at a lower level than the upper portions of the common source plug and the cell contact plugs.

The method according to claim 1,
Wherein the substrate comprises a cell region in which the vertical channel portion is disposed;
A contact region in which the cell contact plugs are disposed; And
The peripheral circuit region,
A peripheral gate pattern disposed on the substrate in the peripheral circuit region;
A peripheral impurity region provided in the substrate on one side of the peripheral gate pattern; And
And peripheral contact plugs disposed on the substrate and electrically connected to the peripheral gate pattern and the peripheral impurity region.

The method according to claim 6,
And upper portions of the peripheral contact plugs are located at the same level as the upper portions of the cell contact plugs.

A substrate comprising a cell region and a contact region;
A stacked structure including gate electrodes vertically stacked on the substrate;
A vertical channel portion passing through the gate electrodes on the cell region;
An impurity region provided in the substrate on one side of the laminated structure;
A common source plug disposed on the substrate and electrically connected to the impurity region; And
And cell contact plugs connected to each of the gate electrodes on the contact region,
The upper portion of the vertical channel portion, the upper portion of the common source plug, and the upper portions of the cell contact plugs are located at different levels.

9. The method of claim 8,
And the upper portion of the vertical channel portion is located at a lower level than the upper portion of the common source plug.

9. The method of claim 8,
Wherein the upper portion of the vertical channel portion is located at a lower level than the upper portion of the common source plug and the upper portion of the common source plug is located at a lower level than the upper portions of the cell contact plugs.