KR20150055189A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a semiconductor device and a method for fabricating the same. The method for fabricating a semiconductor device comprises: providing a substrate including a cell array area, a peripheral circuit area, and a contact area between the cell array area and the peripheral circuit area; forming stacked structures, which include a plurality of electrodes stacked on the substrate, extended in one direction on the substrate of the cell array area, and defining a trench exposing the substrate; forming a peripheral logic structure on the substrate of the peripheral circuit area; forming an insulation layer covering the staked structures and the peripheral logic structure; forming first contact holes exposing the electrodes to the contact area by performing a first patterning process with regard to the insulation layer; forming second contact holes exposing the peripheral logic structure by performing a second patterning process with regard to the insulation layer; and filling the trench, the first contact holes, and the second contact holes with a conductive material.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device and a manufacturing method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a three-dimensional semiconductor device having improved reliability and integration degree and a manufacturing method thereof.

It is required to increase the degree of integration of semiconductor devices in order to meet the excellent performance and low price required by consumers. In the case of semiconductor devices, the degree of integration is an important factor in determining the price of the product, and therefore, an increased degree of integration is required in particular. In the case of a conventional two-dimensional or planar semiconductor device, the degree of integration is largely determined by the area occupied by the unit memory cell, and thus is greatly influenced by the level of the fine pattern forming technique. However, the integration of the two-dimensional semiconductor device is increasing, but is still limited, because of the high-cost equipment required to miniaturize the pattern.

In order to overcome these limitations, three-dimensional semiconductor devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass-produce a three-dimensional semiconductor device, a process technology capable of reducing the manufacturing cost per bit compared to that of a two-dimensional semiconductor device and realizing a reliable product characteristic is required.

A problem to be solved by the present invention is to provide a semiconductor device with improved reliability and integration.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device in which the reliability and the degree of integration are further improved and the manufacturing process is simplified.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: providing a substrate including a cell array region, a peripheral circuit region, and a contact region between the cell array region and the peripheral circuit region; To do; Forming stacked structures extending in one direction on the substrate of the cell array region and defining a trench exposing the substrate, the stacked structures comprising a plurality of electrodes stacked on the substrate; Forming a peripheral logic structure on the substrate of the peripheral circuitry region; Forming an insulating film covering the stacked structures and the peripheral logic structure; Performing a first patterning process on the insulating layer to form first contact holes exposing the electrodes in the contact area; Performing a second patterning process on the insulating layer to form second contact holes exposing the peripheral logic structure; And simultaneously filling the conductive material in the trench, the first contact holes, and the second contact holes.

According to one embodiment, filling the conductive material includes forming a common source line in the trench; Forming first contact plugs in the first contact holes; And forming second contact plugs in the second contact holes, wherein an upper surface of the common source line, an upper surface of the first contact plugs, and an upper surface of the second contact plugs may be coplanar with each other.

According to one embodiment, the second patterning process includes forming a hard mask pattern on the insulating film, the hard mask pattern being formed so as not to completely fill the first contact holes, Air gaps defined by the first contact holes may be formed.

According to one embodiment, forming the peripheral logic structure includes forming a peripheral word line in the substrate of the peripheral circuit area; And forming source and drain impurity regions on both sides of the peripheral word line, wherein the second contact holes can expose at least one of the peripheral word line, the source impurity region, and the drain impurity region.

According to one embodiment, forming vertical structures through the stacked structures and connected to the substrate; And forming a data storage layer between the vertical structures and the electrodes, wherein the vertical structures may include a semiconductor pattern.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate including a cell array region and a peripheral circuit region; Stacked structures extending in one direction on the substrate of the cell array region, the stacked structures comprising a plurality of electrodes stacked on the substrate; A common source structure disposed between the stacked structures adjacent to each other; A peripheral logic structure disposed on the substrate in the peripheral circuit region; And a first contact plug electrically connected to the peripheral logic structure, wherein an upper surface of the common source structure is substantially coplanar with an upper surface of the first contact plugs.

According to one embodiment, the substrate further includes a contact region disposed between the cell array region and the peripheral circuit region, and the semiconductor device further includes second contact plugs disposed in the contact region and connected to the electrodes, Wherein an upper surface of the common source structure is substantially coplanar with an upper surface of the second contact plugs.

According to an embodiment, there is provided a semiconductor device comprising: a common source region formed in the substrate below the common source structure, wherein the common source structure includes insulating spacers covering sidewalls of the stacked structures, And a common source line connected to the region.

According to one embodiment, the peripheral logic structure comprises a peripheral word line on the substrate of the peripheral circuit area; And source and drain impurity regions on both sides of the peripheral word line, and the lower contact plugs may be connected to any one of the peripheral word line, the source impurity region, and the drain impurity region.

According to one embodiment, vertical structures are connected to the substrate through the stacked structures; And a data storage layer interposed between the vertical structures and the electrode, wherein the vertical structures may include a semiconductor pattern.

According to embodiments of the present invention, after forming the trench, the first and second patterning processes may be performed to form the contact holes of the contact region and the peripheral contact holes of the peripheral circuit region. Thereafter, a conductive film filling the trenches, the contact holes, and the peripheral circuit contact holes may be simultaneously formed, and then a planarization process may be performed to form the common source line, the contact plugs, and the lower contact plugs. Thus, the manufacturing process can be simplified compared to the conventional manufacturing method of forming the contact plugs and the lower contact plugs after the common source line is formed first. In addition, it is possible to provide a semiconductor memory device in which the occurrence of defects is reduced due to the simplification of the manufacturing process, and the reliability is improved.

1 is a view for explaining a schematic arrangement structure of a semiconductor memory device according to embodiments of the present invention.
2 is a block diagram of a semiconductor memory device according to embodiments of the present invention.
3 is a simplified circuit diagram showing a cell array of a semiconductor memory device according to embodiments of the present invention.
4 is a perspective view showing a cell array of a semiconductor memory device according to embodiments of the present invention.
5 is a plan view of a semiconductor memory device according to an embodiment of the present invention.
6A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention, taken along line II 'in FIG.
6B is a cross-sectional view of the semiconductor memory device according to one embodiment of the present invention, taken along lines II-II 'and III-III' in FIG.
7A to 15A are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment, and are cross-sectional views taken along a line II 'in FIG. 5.
FIGS. 7B to 15B are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment, and are cross-sectional views taken along lines II-II 'and III-III' of FIG.
16 is a schematic block diagram showing an example of a memory system including a semiconductor memory device according to embodiments of the present invention.
17 is a schematic block diagram showing an example of a memory card having a semiconductor memory device according to an embodiment of the present invention.
18 is a schematic block diagram showing an example of an information processing system for mounting a semiconductor memory device according to the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in this specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional views and / or plan views, which are ideal illustrations of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for an effective description of the technical content. Thus, the shape of the illustrations may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include changes in the shapes that are generated according to the manufacturing process. For example, the etched area shown at right angles may be rounded or may have a shape with a certain curvature. Thus, the regions illustrated in the figures have schematic attributes, and the shapes of the regions illustrated in the figures are intended to illustrate specific types of regions of the elements and are not intended to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a view for explaining a schematic arrangement structure of a semiconductor memory device according to embodiments of the present invention. 2 is a block diagram of a semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1, a semiconductor memory device includes a cell array region CAR, and a peripheral circuit region. The peripheral circuit region includes row decoder regions (ROW DCR), a page buffer region (PBR), and a column decoder region (COL DCR). A contact region CTR may be disposed between the cell array region CAR and the row decoder regions ROW DCR.

Referring to FIGS. 1 and 2, a memory cell array 1 composed of a plurality of memory cells is disposed in a cell array region CAR. The memory cell array 1 includes a plurality of memory cells, a plurality of word lines and bit lines electrically connected to the memory cells. In one embodiment, the memory cell array 1 may include a plurality of memory blocks BLK0 to BLKn, which are data erase units. The memory cell array 1 will be described in detail with reference to FIGS. 3 and 4. FIG.

In the row decoder region (ROW DCR), a row decoder 2 for selecting the word lines of the memory cell array is disposed. A wiring structure for electrically connecting the memory cell array 1 and the row decoder 2 may be disposed in the contact region CTR. The row decoder 2 selects one of the memory blocks BLK0 to BLKn of the memory cell array 1 and selects one of the word lines of the selected memory block in accordance with the address information. The row decoder 2 may provide the word line voltage generated from the voltage generating circuit to the selected word line and the unselected word lines, respectively, in response to the control of the control circuit.

The page buffer area PBR may be provided with a page buffer 3 for reading information stored in the memory cells. The page buffer 3 may temporarily store data to be stored in the memory cells or sense data stored in the memory cells, depending on the operation mode. The page buffer 3 operates as a write driver circuit in a program operation mode and as a sense amplifier circuit in a read operation mode.

A column decoder 4 connected to the bit lines of the memory cell array 1 is disposed in the column decoder region COL DCR. The column decoder 4 can provide a data transmission path between the page buffer 3 and an external device (for example, a memory controller).

3 is a simplified circuit diagram showing a cell array of a semiconductor memory device according to embodiments of the present invention.

3, the cell array of the semiconductor memory device according to the embodiment is disposed between the common source line CSL, the plurality of bit lines BL, and the common source line CSL and the bit lines BL. And a plurality of cell strings CSTR.

The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines BL. The cell strings CSTR may be connected in common to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines BL and one common source line CSL. According to one embodiment, the common source lines CSL may be arranged two-dimensionally in plural. Here, electrically common voltages may be applied to the common source lines CSL, or each common source line CSL may be electrically controlled.

Each of the cell strings CSTR includes a ground selection transistor GST connected to the common source line CSL, a string selection transistor SST connected to the bit line BL, and ground and string selection transistors GST and SST And a plurality of memory cell transistors MCT arranged between the plurality of memory cell transistors MCT. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be connected in common to the sources of the ground selection transistors GST. In addition, the ground selection line GSL, the plurality of word lines WL0-WL3 and the plurality of string selection lines SSL, which are disposed between the common source line CSL and the bit lines BL, As the gate electrodes of the selection transistor GST, the memory cell transistors MCT and the string selection transistors SST, respectively. In addition, each of the memory cell transistors MCT includes a data storage element.

4 is a perspective view showing a cell array of a semiconductor memory device according to embodiments of the present invention.

According to the embodiment shown in FIG. 4, the common source line CSL may be a conductive thin film disposed on the substrate 10 or an impurity region formed in the substrate 10. The bit lines BL may be conductive patterns (e.g., metal lines) that are spaced apart from the substrate 10 and disposed thereon. The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR are connected in parallel to each of the bit lines BL. Whereby the cell strings CSTR are two-dimensionally arranged on the common source line CSL or the substrate 10. [

Each of the cell strings CSTR includes a plurality of ground selection lines GSL1 and GSL2 disposed between the common source line CSL and the bit lines BL, a plurality of word lines WL0 to WL3, And two string selection lines SSL1 and SSL2. In one embodiment, the plurality of string select lines SSL1 and SSL2 may constitute the string select lines SSL of FIG. 3, and the plurality of ground select lines GSL1 and GSL2 may be formed as shown in FIG. It is possible to configure the ground selection lines GSL. The gate selection lines GSL1 and GSL2 and the word lines WL0 to WL3 and the string selection lines SSL1 and SSL2 are connected to the conductive patterns (i.e., gate electrodes) .

In addition, each of the cell strings CSTR may include vertical structures VS vertically extending from the common source line CSL to connect to the bit line BL. The vertical structures VS may be formed to penetrate the ground selection lines GSL1 and GSL2, the word lines WL0 to WL3 and the string selection lines SSL1 and SSL2. In other words, the vertical structures VS can penetrate a plurality of conductive patterns stacked on the substrate 10. [

The vertical structures VS may comprise a semiconductor material or a conductive material. According to one embodiment, the vertical structures VS may be formed of a semiconductor material, and as shown in FIG. 4, a semiconductor body portion SP1 and a semiconductor body portion SP1, which are connected to the semiconductor substrate 10, And a semiconductor spacer SP2 interposed between the data storage layers DS. In addition, the vertical structures VS may include impurity regions at the top thereof. For example, a drain region D may be formed at the top of the vertical structure VS.

A data storage film DS may be disposed between the word lines WL0-WL3 and the vertical structures VS. According to one embodiment, the data storage film DS may be a charge storage film. For example, the data storage film DS may be one of an insulating film including a trap insulating film, a floating gate electrode, or conductive nano dots. The data stored in this data storage film DS can be changed using Fowler-Nordheim tunneling caused by the voltage difference between the vertical structure VS including the semiconductor material and the word lines WL0-WL3 have. Alternatively, the data storage layer DS may be a thin film (e.g., a thin film for a phase change memory or a thin film for a variable resistance memory) capable of storing information based on another operating principle.

According to one embodiment, the data storage layer DS includes a vertical isolation pattern VP extending through the word lines WL0-WL3 and a vertical isolation pattern VP between the word lines WL0-WL3 and the vertical isolation pattern VP. And a horizontal insulation pattern HP extending to the top and bottom surfaces of the lines WL0-WL3.

A dielectric film used as a gate insulating film of the transistor may be disposed between the ground selection lines GSL1 and GSL2 and the vertical structures VS or between the string selection lines SSL1 and SSL2 and the vertical structures VS . Here, the dielectric layer may be formed of the same material as the data storage layer DS or may be a gate insulation layer (for example, a silicon oxide layer) for a typical MOSFET.

In such a structure, the vertical structures VS connect the vertical structure VS with the ground selection lines GSL1 and GSL2, the word lines WL0-WL3 and the string selection lines SSL1 and SSL2, It is possible to constitute a MOSFET (field effect transistor) for use as a channel region. Alternatively, the vertical structures VS constitute a MOS capacitor together with the ground selection lines GSL1 and GSL2, the word lines WL0 to WL3 and the string selection lines SSL1 and SSL2. can do.

In this case, the ground selection lines GSL1 and GSL2, the plurality of word lines WL0 to WL3, and the plurality of string selection lines SSL1 and SSL2 may be used as the gate electrodes of the selection transistor and the cell transistor, respectively. The vertical structures VS are formed by the fringe field from the voltages applied to the ground selection lines GSL1 and GSL2, the word lines WL0 to WL3 and the string selection lines SSL1 and SSL2, Inversion regions may be formed in the substrate. Here, the maximum distance (or width) of the inversion region may be greater than the thickness of the word lines or selection lines that create the inversion region. Thus, the inversion regions formed in the semiconductor column are vertically superimposed to form a current path electrically connecting the selected bit line from the common source line CSL.

That is, the cell string CSTR includes the cell transistors (also referred to as cell transistors) constituted by the ground and string transistors constituted by the lower and upper selection lines GSL1, GSL2, SSL1 and SSL2 and the word lines WL0 to WL3 3 MCT) may be connected in series.

5 is a plan view of a semiconductor memory device according to an embodiment of the present invention. FIG. 6A is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention, taken along line I-I 'of FIG. 6B is a cross-sectional view of the semiconductor memory device according to one embodiment of the present invention, taken along lines II-II 'and III-III' in FIG.

5, 6A and 6B, the substrate 10 may include a cell array area CAR, a peripheral circuit area PERI, and a contact area CTR therebetween. The substrate 10 of the peripheral circuit region PERI may include an active region ACT defined by the device isolation film 11. [

The substrate 10 may be one of a semiconductor material having a semiconductor property (e.g., a silicon wafer), an insulating material (e.g., glass), or a semiconductor or a conductor covered with an insulating material. For example, the substrate 10 may be a silicon wafer having a first conductivity type.

According to one embodiment, a cell array structure may be disposed on the substrate 10 of the cell array area CAR and a peripheral logic structure may be disposed on the substrate 10 of the peripheral circuit area PERI. The cell array structure may have a first height on the top surface of the substrate 10 and may extend from the cell array area CAR to the contact area CTR. The peripheral logic structure may have a second height less than the first height.

The cell array structure includes a plurality of stacked structures ST including vertically stacked electrodes EL on the substrate 10 and vertical structures VS passing through the stacked structures ST . The stacked structures ST may extend in the first direction D1 as shown and may be spaced apart in the second direction D2 by a predetermined distance. Further, the stacked structures ST may have inclined side walls. The stacked structures ST may have a stepwise structure in the contact region CTR for electrical connection between the electrodes EL and the peripheral logic structure. That is, the vertical height of the stacked structures ST in the contact area CTR may gradually increase as the cell array area CAR is adjacent to the cell array area CAR. In other words, the stacked structures ST may have a sloped profile in the contact area CTR.

The stacked structures ST may include insulating films ILD between vertically adjacent electrodes EL. The thicknesses of the insulating films ILD may be equal to each other, or a thickness of a part of the insulating films ILD may be different. The end portions of the electrodes EL may be disposed on the contact region CTR and the stacked structures ST may have a stepped structure in the contact region CTR. Specifically, the farther the electrodes EL are from the upper surface of the substrate 10, the smaller the area of the electrodes EL. One sidewalls of the electrodes EL may be arranged at different horizontal positions in the contact area CTR.

According to one embodiment, the vertical structures VS may be connected to the substrate 10 through the stacked structures ST. The vertical structures VS may comprise a semiconductor material or a conductive material. According to one embodiment, the vertical structures VS may include a semiconductor body portion connected to the substrate 10 and a semiconductor spacer interposed between the semiconductor body portion and the data storage film, as described with reference to Fig. 4 have. The data storage film has a vertical insulation pattern extending vertically between the electrodes EL and the vertical structure VS and a vertical insulation pattern extending between the vertical insulation pattern and the electrodes EL to the upper and lower surfaces of the electrodes EL And may include a horizontal isolation pattern. According to one embodiment, the vertical structures VS can be arranged in one direction in plan view. Alternatively, the vertical structures VS may be arranged in a zigzag fashion in one direction in terms of planar view. According to one embodiment, the conductive pad 115 may be disposed on the top of the vertical structure VS. The conductive pad 115 may be an impurity region doped with an impurity, or may be made of a conductive material. That is, the conductive pad 115 may be the drain region D of FIG.

Further, common source regions 130 may be formed in the substrate 10 between the stacked structures ST. The common source regions 130 may extend in parallel in the first direction D1 and may be spaced apart from each other in the second direction. The common source regions 130 may be formed by doping the substrate 10 and other types of impurities into the substrate 10.

According to one embodiment, a common source structure (CSL) may be disposed between adjacent stacked structures ST. The common source structure CSL includes insulating spacers 142 covering the sidewalls of the stacked structures ST and a common source line 152 connected to the common source region 130 through the insulating spacers 142 . The common source structure CSL may extend in the first direction D1. The insulating spacers 142 may be disposed opposite to each other between the adjacent stacked structures ST.

Insulation spacers 142 may be formed of silicon oxide silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant. The common source line 152 may include at least one selected from a metal (ex, tungsten, copper or aluminum, etc.), a conductive metal nitride (ex, titanium nitride or tantalum nitride) and a transition metal (ex, titanium or tantalum, .

The buried insulating film 100 covering the end portions of the stacked structures ST and the peripheral logic structure may be disposed on the entire surface of the substrate 10. [ The upper surface of the buried insulating film 100 may coplanar with upper surfaces of the stacked structures ST or upper surfaces of the vertical structures VS. A capping insulation pattern 125 may be disposed on the cell array structure and the buried insulating film 100 to co-exist with upper surfaces of the common source structures CSL.

The interlayer insulating layer 160 may be disposed on the capping insulating pattern 125 and the common source structures CSL and may be disposed on the interlayer insulating layer 160 in the second direction D2 across the stacking structures ST. Extending bit lines BL may be disposed. The bit lines BL may be electrically connected to the vertical structures VS through a bit line contact plug BPLG that penetrates the interlayer insulating layer 160 and the capping insulating pattern 125. [

A wiring structure for electrically connecting the cell array structure and the peripheral logic structure to the contact region CTR may be disposed. According to one embodiment, the contact plugs PLG connected to the ends of the electrodes EL through the capping insulating pattern 125 and the buried insulating film 100 may be disposed in the contact region CTR. The vertical length of the contact plugs (PLG) can be reduced as the contact plugs (PLG) are adjacent to the cell array area (CAR). In one embodiment, the top surfaces of the contact plugs PLG can co-exist with the top surfaces of the common source structures CSL.

In addition, connection lines CL that are electrically connected to the contact plugs PLG through the contacts CT may be disposed on the interlayer insulating film 160 of the contact region CTR.

According to one embodiment, the peripheral logic structure of the peripheral circuit region PERI includes the row and column decoders (see 2 and 4 in FIG. 2), the page buffer (as shown in FIG. 2 3) and peripheral circuits such as control circuits. That is, the peripheral logic structure may include NMOS and PMOS transistors, a resistor, and a capacitor, which are electrically connected to the cell array structure.

In detail, the substrate 10 of the peripheral circuit region PERI may be provided with an element isolation film 11 defining an active region ACT. The peripheral logic structure of the peripheral circuit area PERI includes a peripheral word line 23 extending in the first direction across the active area ACT, a source formed in the active area ACT on both sides of the peripheral word line 23, Drain impurity regions 21 and 22, and a peripheral insulation pattern 30 covering peripheral circuits. In addition, the peripheral logic structure may include a resistive pattern 25, and the peripheral insulating pattern 30 may cover the peripheral wordline 23 and the resistive pattern 25. The upper surface of the peripheral insulating pattern 30 may be located below the upper surface of the cell array structure.

According to one embodiment, a plurality of wirings ICL may be disposed on the interlayer insulating film 160 in the peripheral circuit region PERI. The plurality of wirings ICL may extend from the peripheral circuit region PERI to the cell array region CAR. According to one embodiment, the plurality of wirings ICL may be formed of the same conductive material as the bit lines BL of the cell array region CAR.

The plurality of wirings ICL may extend in parallel in the second direction D2 perpendicular to the first direction D1 and the portions of the wirings ICL may be overlapped with the active area ACT . That is, a plurality of wirings ICL may be disposed on one active region ACT.

According to one embodiment, in a vertical view, the first to third lower contact plugs LCP1, LCP2, LCP3 may be disposed between the peripheral logic structure and the plurality of wirings ICL. Each of the first to third lower contact plugs LCP1, LCP2 and LCP3 penetrates the capping insulating pattern 125 and the buried insulating film 100 to form the source impurity region 21, the drain impurity region 22, (23). In addition, the first to third upper contact plugs UCP1, UCP2, UCP3 may be disposed on the capping insulation pattern 125 of the peripheral circuit region PERI. Each of the first to third upper contact plugs UCP1, UCP2 and ULCP3 may be connected to the first to third lower contact plugs LCP1, LCP2 and LCP3 through the interlayer insulating layer 160. [

Thus, the source impurity region 21 can be electrically connected to one of the plurality of wirings ICL through the first lower contact plug LCP1 and the first upper contact plugs UCP1. Similarly, the drain impurity region 22 can be electrically connected to one of the plurality of lines ICL through the second lower contact plug LCP2 and the second upper contact plugs UCP2, and the peripheral word line 23 May be electrically connected to one of the plurality of wirings ICL through the third lower contact plug LCP3 and the third upper contact plugs UCP3. Although the first through third bottom contacts LCP1, LCP2 and LCP3 and the first through third top contacts UCP1, UCP2 and UCP3 are shown in the peripheral circuit region PERI in the embodiment, But is not limited thereto. Lower and upper contact plugs may be further added, and their positions may vary depending on the electrical connection relationship between the wirings (ICL) and peripheral circuits. In one embodiment, the upper surfaces of the first through third lower contact plugs LCP1, LCP2, LCP3 may be substantially coplanar with the upper surfaces of the contact plugs PLG of the contact region CTR. The upper surfaces of the first to third lower contact plugs LCP1, LCP2 and LCP3 may coincide with the upper surfaces of the common source structures CSL of the cell array region CAR.

7A to 15A are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment, and are cross-sectional views taken along a line I-I 'in FIG. FIGS. 7B to 15B are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment, and are cross-sectional views taken along lines II-II 'and III-III' of FIG.

Referring to Figures 7A and 7B, The substrate 10 may include a cell array area CAR, a peripheral circuit area PERI, and a contact area CTR therebetween. The substrate 10 of the peripheral circuit region PERI may include an active region defined by the element isolation film 11 (see ACT in FIG. 5).

The substrate 10 may be one of a semiconductor material having a semiconductor property (e.g., a silicon wafer), an insulating material (e.g., glass), or a semiconductor or a conductor covered with an insulating material. For example, the substrate 10 may be a silicon wafer having a first conductivity type.

According to one embodiment, a peripheral logic structure including peripheral circuits may be formed on the substrate 10 of the peripheral circuit region PERI. Forming a peripheral logic structure may include forming peripheral circuits such as the row and column decoders, page buffers, and control circuits described with reference to FIG. According to one embodiment, peripheral transistors and resistor patterns 25 constituting peripheral circuits may be formed on the substrate 10 of the peripheral circuit region PERI.

Forming the peripheral transistors includes forming the peripheral word lines 23 via the gate insulating film on the substrate 10 and forming the source and drain impurity regions 21, 22 < / RTI > Here, the peripheral word lines 23 may extend in the first direction D1 (see Fig. 5) across the active area. In addition, when forming the peripheral word line 23, a resistance pattern 25 may be formed on the substrate 10 of the peripheral circuit region PERI. The resistance pattern 25 may be formed of the same material as the peripheral word line 23. [ Here, the peripheral word line 23 can be used as the gate electrodes of the MOS transistors constituting the peripheral circuits, and the source and drain impurity regions 21 and 22 can be used as the source and drain electrodes of the MOS transistors. The peripheral word line 23 may be formed of an impurity-doped polysilicon or a metal material, and the gate insulating film may be a silicon oxide film formed by a thermal oxidation process.

Next, the peripheral insulation pattern 30 may be formed on the substrate 10 of the peripheral circuit region PERI where the peripheral transistors and the resistance pattern 25 are formed. The peripheral insulating pattern 30 is formed by forming the peripheral insulating film covering the entire surface of the substrate 10 on which the peripheral word lines 23 and the resist pattern 25 are formed and patterning the peripheral insulating film, CAR and the contact region CTR of the substrate 10. In addition, an etch stop film may be formed which conformally covers the peripheral word lines 23, the resist pattern 25, and the upper surface of the substrate 10 before forming the peripheral insulating film. The peripheral insulating pattern 30 may be formed of at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and silicon oxycarbide. The etch stop film may be formed of an insulating material having etching selectivity with respect to the peripheral insulating pattern 30. [

Subsequently, referring to FIGS. 7A and 7B, The thin film structure 110 can be formed on the substrate 10 of the cell array region CAR.

According to one embodiment, the thin film structure 110 may include sacrificial layers (HL) and insulating films (ILD) alternately and repeatedly stacked on the substrate 10. In one embodiment, the height of the thin film structure 110 may be greater than the height of the surrounding logic structure. For example, the height of the thin film structure 110 may be at least about two times the height of the peripheral logic structure. That is, the upper surface of the peripheral logic structure may be located below the upper surface of the thin film structure 110.

In one embodiment, the thin film structure 110 may have a stepwise structure in the contact region CTR. In other words, the thin film structure 110 may have a sloped profile in the contact area CTR. That is, as the insulating films ILD and the sacrificial films HL are away from the upper surface of the substrate 10, the area of the insulating films ILD and the sacrificial films HL can be reduced. In other words, as the height of the sacrificial layers HL on the upper surface of the substrate 10 increases, the distance between one sidewalls of the sacrificial layers HL and the peripheral circuit region PERI may be increased.

More specifically, the sacrificial layers HL of the thin film structure 110 and the end portions of the insulating layers ILD may be disposed in the contact region CTR and one side walls of the sacrificial layers HL may be formed in the contact region CTR). ≪ / RTI > Further, the horizontal distance between one side walls of the sacrificial films HL may be substantially uniform.

Forming the thin film structure 110 includes forming a preliminary thin film structure including horizontal films and insulating films alternately stacked on the front side of the substrate 10 and patterning the preliminary thin film structure. Here, the patterning of the preliminary thin film structure may include alternately repeating the process of reducing the horizontal area of the mask pattern (not shown) and the process of anisotropically etching the thin film structure. By alternately repeating such processes, the end portions of the insulating films (ILD) in the contact region can be sequentially exposed from the bottom.

In one embodiment, when forming the thin film structure 110, portions of the insulating films ILD and the sacrificial films HL stacked on the cell array region CAR are formed on one side wall Lt; / RTI > In other words, a part of the thin film structure 110 formed on one side wall of the peripheral insulation pattern 30 may remain as a spacer on one side wall of the peripheral insulation pattern 30 without being etched in the anisotropic etching process.

According to one embodiment, the thicknesses of the sacrificial layers HL constituting the thin film structure 110 may be equal to each other, or a part of the thicknesses of the sacrificial layers HL may be different from each other. In addition, the thicknesses of the insulating films ILD constituting the thin film structure 110 may be equal to each other, or a part thereof may have a different thickness.

According to one embodiment, the sacrificial films HL may be formed of materials having etch selectivity to the insulating films (ILD) in a wet etching process. In one example, the insulating films ILD may include at least one of a silicon oxide film and a silicon nitride film. The sacrificial layers HL are selected from a silicon film, a silicon oxide film, a silicon carbide film, and a silicon nitride film, but may be materials different from the insulating films (ILD). The sacrificial films HL may be formed of the same material.

A lower insulating film 105 may be formed between the substrate 10 and the thin film structure 110. [ For example, the lower insulating film 105 may be a silicon oxide film formed through a thermal oxidation process. Alternatively, the lower insulating film 105 may be a silicon oxide film formed using a deposition technique. The lower insulating film 105 may have a thickness thinner than the sacrificial films HL and the insulating films ILD formed thereon.

The buried insulating film 100 may be formed on the substrate 10 after the peripheral logic structure and the cell array structure are formed. The buried insulating film 100 can be conformally deposited along the surface of the structures on the substrate 10 in the cell array region CAR and the peripheral circuit region PERI using a deposition technique. The buried insulating film 100 may be deposited to a thickness larger than the distance between the upper surface of the peripheral logic structure and the upper surface of the cell array structure. The buried insulating film 100 formed by the deposition process may have a height difference between the cell array region CAR and the peripheral circuit region PERI. Accordingly, after the buried insulating film 100 is deposited, a planarization process for the buried insulating film 100 may be performed to remove a height difference between the cell array region CAR and the peripheral circuit region PERI. That is, the buried insulating film 100 may have a planarized upper surface. In one embodiment, the upper surface of the buried insulating film 100 may be coplanar with the upper surface of the uppermost ILD of the thin film structure 110.

For example, the buried insulating film 100 may include a high density plasma (HDP) oxide film, TEOS (TetraEthylOrthoSilicate), PE-TEOS (Plasma Enhanced TetraEthylOrthoSilicate), O3-TEOS (O3-Tetra Ethyl Ortho Silicate) (Phosphosilicate glass), BSG (borosilicate glass), BPSG (borophosphosilicate glass), FSG (fluoride silicate glass), SOG (spin on glass), TOSZ (Tonen SilaZene) or a combination thereof. In addition, the buried insulating film 100 may include silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

Referring to Figures 8A and 8B, Vertical structures (VS) passing through the thin film structure 110 and a data storage film can be formed on the substrate 10 of the cell array region CAR. The vertical structures VS may comprise a semiconductor material or a conductive material.

According to one embodiment, forming the vertical structures VS may include forming openings through the thin film structure 110 and forming a semiconductor pattern in the openings.

The openings may be formed by forming a mask pattern (not shown) on the thin film structure 110 and anisotropically etching the thin film structure 110 using a mask pattern (not shown) as an etch mask. It may be over-etched to the top surface of the substrate 10 in the anisotropic etching process so that the top surface of the substrate 10 exposed to the openings can be recessed to a predetermined depth. Further, the bottom width of the openings may be smaller than the top width of the openings by the anisotropic etching process. Further, the openings may be arranged in one direction in a plan view, or may be arranged in a zigzag form.

In one embodiment, forming a semiconductor pattern within the openings includes forming a semiconductor spacer (SP2, see FIG. 4) that exposes the substrate 10 and covers the sidewalls of the openings, as shown in FIG. 4, and And forming a semiconductor body portion SP1 (see FIG. 4) connected to the semiconductor substrate. The semiconductor pattern may include silicon (Si), germanium (Ge), or a mixture thereof, or may be an impurity-doped semiconductor or an intrinsic semiconductor in a state where the impurity is not doped. In addition, the semiconductor pattern may have a crystal structure including at least one selected from the group consisting of single crystal, amorphous, and polycrystalline. In another embodiment, the semiconductor pattern may be pipe-shaped or macaroni-shaped. Furthermore, a conductive pad 115 may be formed on the top of the vertical structure VS. The conductive pad 115 may be an impurity region doped with an impurity, or may be made of a conductive material. That is, the conductive pad 115 may be the drain region D of FIG.

According to one embodiment, a portion of the data storage film may be formed before forming the vertical structures VS. That is, the vertical insulating pattern of the data storage film described with reference to FIG. 4 may be formed before forming the vertical structures VS. The vertical insulation pattern may be composed of one thin film or a plurality of thin films. According to one embodiment, the vertical isolation pattern may comprise a tunnel insulating layer of a charge trap type flash memory transistor. The tunnel insulating film may be one of materials having a larger bandgap than the charge storage film. For example, the tunnel insulating film may be one of high-k films such as an aluminum oxide film and a hafnium oxide film. In addition, the vertical isolation pattern may comprise a charge storage film of a charge trapped flash memory transistor. The charge storage film may be one of an insulating film rich in trap sites such as a silicon nitride film, a floating gate electrode, or an insulating film including conductive nano dots.

8A and 8B, after the vertical structures VS are formed, a capping insulating film 120 may be formed to cover the vertical structures VS and the upper surface of the thin film structure 110. In addition, the capping insulating film 120 may be formed simultaneously on the buried insulating film 100 of the peripheral circuit region PERI. The capping insulating layer 120 may be formed of the same material as the buried insulating layer 100.

9A and 9B, the thin film structure 110 on which the capping insulating layer 120 is formed may be patterned to form the trenches T exposing the substrate 10 between adjacent vertical structures VS. have.

Specifically, forming the trenches T is performed by forming a mask pattern (not shown) that defines a planar position of the trenches T on the capping insulating film 120, forming a mask pattern (not shown) And anisotropically etching the capping insulating film 120 and the thin film structure 110 using the thin film structure as a mask.

The trenches T may be spaced from the vertical structures VS and may be formed to expose the sidewalls of the sacrificial films HL and the insulating films ILD. In a horizontal view, the trenches T may be formed in a line or a rectangle, and at a vertical depth, the trenches T may be formed to expose the top surface of the substrate 10. [ The top surface of the substrate 10 exposed to the trenches T by overetching can be recessed to a predetermined depth while forming the trenches T. [ Further, the trenches T may have inclined sidewalls by an anisotropic etching process.

As the trenches T are formed, the thin film structure 110 may have a line shape extending in a first direction D1 (see FIG. 5). A plurality of vertical structures (VS) can penetrate the thin film structure (110) in a line form. In addition, the capping insulating layer 120 of FIG. 8 may be patterned to form the capping insulating pattern 125 on the thin film structure 110.

10A and 10B, the sacrificial layers HL exposed to the trenches T may be removed to form the recessed regions R between the insulating films ILD.

Specifically, the recessed regions R are formed by etching the sacrificial films HL isotropically using insulating films ILD, vertical structures VS, and etch recipes having etch selectivity to the substrate 10 . Here, the sacrificial films HL can be completely removed by an isotropic etching process. For example, if the sacrificial films HL are silicon nitride films and the insulating films ILD are silicon oxide films, the etching step may be performed using an etchant containing phosphoric acid.

The recessed regions R may extend horizontally from the trench T to the insulating films ILD and may extend either horizontally along the sidewall portions of the vertical isolation pattern VP You can expose people. That is, the recess regions R can be defined by vertically adjacent insulating films ILD and one side wall of the vertical insulation pattern VP (see FIG. 4). In addition, the vertical isolation pattern VP (see FIG. 4) can be used as an etch stop layer during an isotropic etching process to form the recessed regions R.

11A and 11B, an insulating pattern covering the inner walls of the recessed regions R (see FIGS. 10A and 10B) and conductive patterns filling the recessed regions R (see FIGS. 10A and 10B) .

Specifically, the insulation pattern covering the inner walls of the recessed regions (R, Figs. 10A and 10B) may correspond to the horizontal insulation pattern HP of the data storage film described with reference to Fig. In one embodiment, the horizontal insulating pattern can be composed of one thin film or a plurality of thin films. According to one embodiment, the horizontal isolation pattern may comprise a blocking insulating film of a charge trapped flash memory transistor. The blocking insulating film may be one of materials having a band gap smaller than the tunnel insulating film and larger than the charge storing film. For example, the blocking insulating film may be one of high-k films such as an aluminum oxide film and a hafnium oxide film.

Further, forming the conductive patterns may include forming electrodes EL that constitute the stacked structures ST in the recessed regions R (see Figs. 10A and 10B) from which the sacrificial films have been removed . The electrodes EL may include a barrier metal film and a metal film. The barrier metal film may be made of a metal nitride film, for example, TiN, TaN or WN. The metal film may be made of metal materials such as, for example, W, Al, Ti, Ta, Co or Cu.

12A and 12B, insulating spacers 142 may be formed in the trenches T to cover the sidewalls of the stacked structures ST.

Specifically, the insulating spacers 142 can be formed by conformally forming a spacer film on the result of FIGS. 11A and 11B, and then performing an anisotropic etching process, that is, an etch back process . The spacer film may be formed of an insulating material. In one example, the spacer film may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant. The spacer film can be deposited using deposition techniques with excellent step coverage, such as chemical vapor deposition (CVD), atomic layer deposition (ALD) methods. In one embodiment, the etch back process for the spacer film can be performed until the substrate 10 between the stacked structures ST is exposed. That is, the insulating spacers 142 cover the sidewalls of the stacked structures ST, and can expose the substrate 10 between the stacked structures ST.

Referring to FIGS. 13A and 13B, a capping insulating pattern 125 and contact holes CH penetrating the buried insulating film 100 may be formed in each of the contact regions CTR.

Specifically, the contact holes CH may be formed by performing a first patterning process for the capping insulating pattern 125 and the buried insulating film 100. [ The first patterning process may include forming a first hard mask film on the result of FIGS. 12A and 12B, and then performing a photolithography process to form the first hard mask pattern 145. The first hard mask layer may be formed of a material that covers the upper surface of the capping insulation pattern 125 and minimizes the filling of the trench T. [ In one example, the first hard mask layer may include an amorphous carbon layer (ACL). As a result, a first air gap AG1 defined by the upper surface of the substrate 10, the sidewalls of the insulating spacers 142, and the lower surface of the first hard mask pattern 145 can be formed. The first air gap AG1 may be a substantially empty space filled with air. In addition, the first patterning process may include anisotropically etching the capping insulation pattern 125 and the buried insulation layer 100 of the contact area CTR using the first hard mask pattern 145 as an etch mask.

According to one embodiment, when forming the contact holes CH, the stacked structures ST have a stepped structure in the contact region CTR, so that the contact holes CH are formed in the electrodes EL ) Can be locally exposed. That is, the etch depths of the contact holes CH may be different from each other during the first patterning process. Thus, the end portions of the electrodes EL in the contact region CTR can be exposed to the contact holes CH. After the formation of the contact holes CH, the first hard mask pattern 145 can be removed.

Referring to FIGS. 14A and 14B, a capping insulating pattern 125 and peripheral contact holes PH penetrating the buried insulating film 100 may be formed in the peripheral circuit region PERI.

Specifically, the peripheral contact holes PH may be formed by performing a second patterning process for the capping insulating pattern 125 and the buried insulating film 100. The second patterning process may be performed by forming a second hard mask film on the resultant from which the first hard mask pattern 145 of FIGS. 13A and 13B is removed, and then performing a photolithography process to form a second hard mask pattern 147 ≪ / RTI > The second hard mask film may be formed of a material that covers the upper surface of the capping insulation pattern 125 and can minimize the filling of the trenches T and the contact holes CH. For example, the second hard mask layer may include an amorphous carbon layer (ACL). As a result, a first air gap AG1 as shown in FIG. 13 can be formed and defined by the upper surface of the substrate 10, the inner wall of the contact hole CH and the lower surface of the second hard mask pattern 147 A second air gap AG2 may be formed. The first and second air gaps AG1 and AG2 may be substantially empty spaces filled with air. In addition, the second patterning process may include anisotropically etching the capping insulation pattern 125 and the buried insulation layer 100 in the peripheral circuit region PERI with the second hard mask pattern 147 as an etch mask.

In one embodiment, the peripheral contact holes PH may comprise first through third peripheral contact holes. The first peripheral contact hole can locally expose the source impurity region 21 through the capping insulating pattern 125 and the buried insulating film 100 of the peripheral circuit region PERI. The second peripheral contact hole can locally expose the drain impurity region 22 through the capping insulating pattern 125 and the buried insulating film 100 of the peripheral circuit region PERI. The third peripheral contact hole may locally expose the peripheral word line 23 through the capping insulating pattern 125 and the buried insulating film 100 of the peripheral circuit area PERI. After the formation of the peripheral contact holes PH, the second hard mask pattern 147 can be removed.

15A and 15B, common source lines 152 may be formed in the trenches T in which the insulating spacers 142 are formed. At the same time, the contact plugs PLG can be formed in the contact holes CH and the lower contact plugs LCP1, LCP2, LCP3 can be formed in the peripheral contact holes PH .

Forming the common source lines 152, the contact plugs PLG and the lower contact plugs LCP1, LCP2 and LCP3 is achieved by forming the trenches T, the contact holes CH, and the peripheral contact holes PH , And performing a planarization process to expose the top surface of the capping insulation pattern 125. The capping insulation pattern 125 may be formed of a conductive material. Accordingly, a common source structure CSL including the insulating spacers 142 and the common source line 152 can be formed, and at the same time, the contact plugs PLG and the lower contact plugs LCP1, LCP2, LCP3, Can be formed . As a result, the upper surfaces of the common source structure (CSL) can cooperate with the upper surfaces of the contact plugs (PLG). In addition, the upper surfaces of the common source structure CSL may coincide with the upper surfaces of the lower contact plugs LCP1, LCP2, and LCP3.

According to one embodiment, the common source line 152, the contact plugs PLG, and the lower contact plugs LCP1, LCP2, LCP3 may be formed of a metallic material (e.g., tungsten). In this case, the formation of the common source line 152, the contact plugs PLG, and the lower contact plugs LCP1, LCP2, LCP3 may be accomplished by forming a barrier metal film (e.g., metal nitride) For example, tungsten).

Continue, Referring again to Figures 6A and 6B, The bit line plugs BPLG connected to the vertical structure VS of the cell array region CAR may be formed after the interlayer insulating film 160 is formed on the capping insulating pattern 125. [ In addition, contacts CT connected to the contact plugs PLG may be formed in the contact region CTR. Also, upper contact plugs UCP1, UCP2, UCP3 connected to the first to third lower contact plugs LCP1, LCP2, LCP3 may be formed in the peripheral circuit area PERI.

Next, a plurality of wirings ICL may be formed on the interlayer insulating film 160 in the peripheral circuit region PERI. Wirings ICL may extend in a second direction D2 (see FIG. 5) across the peripheral word line 23 and extend from the cell array area CAR to the peripheral circuit area PERI. According to one embodiment, the plurality of wirings ICL can electrically connect the memory cells of the cell array area CAR and the peripheral logic circuits of the peripheral circuit area PERI.

The plurality of interconnections ICL may be formed and the bit line BL of the cell array region CAR and the connection lines CL of the contact region CTR may be formed . Wirings ICL of the bit lines BL, the connection lines CL and the peripheral circuit region PERI may be formed by depositing a conductive film on the interlayer insulating film 160 and patterning the conductive film.

According to embodiments of the present invention, after forming the trench, the first and second patterning processes may be performed to form the contact holes of the contact region and the peripheral contact holes of the peripheral circuit region. Thereafter, a conductive film filling the trenches, the contact holes, and the peripheral circuit contact holes may be simultaneously formed, and then a planarization process may be performed to form the common source line, the contact plugs, and the lower contact plugs. Thus, the manufacturing process can be simplified compared to the conventional manufacturing method of forming the contact plugs and the lower contact plugs after the common source line is formed first. In addition, it is possible to provide a semiconductor memory device in which the occurrence of defects is reduced due to the simplification of the manufacturing process, and the reliability is improved.

16 is a schematic block diagram showing an example of a memory system including a semiconductor memory device according to embodiments of the present invention.

16, the memory system 1100 may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, A memory card, or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes an input / output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. Memory 1130 and interface 1140 are in communication with one another via bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process device. Memory 1130 may be used to store instructions executed by the controller. The input / output device 1120 may receive data or signals from outside the system 1100, or may output data or signals outside the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display device.

Memory 1130 includes a non-volatile memory device in accordance with embodiments of the present invention. Memory 1130 may also include other types of memory, volatile memory that may be accessed at any time, and various other types of memory.

The interface 1140 serves to transmit data to and receive data from the communication network.

17 is a schematic block diagram showing an example of a memory card having a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 17, a memory card 1200 for supporting a high capacity data storage capability mounts a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls the exchange of all data between the host and the flash memory device 1210.

The SRAM 1221 is used as the operating memory of the processing unit 1222. The host interface 1223 has a data exchange protocol of a host connected to the memory card 1200. Error correction block 1224 detects and corrects errors contained in data read from multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs all control operations for data exchange of the memory controller 1220. Although it is not shown in the drawing, the memory card 1200 according to the present invention may be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned.

18 is a schematic block diagram showing an example of an information processing system for mounting a semiconductor memory device according to the present invention.

Referring to FIG. 18, the memory system 1310 of the present invention is installed in an information processing system such as a mobile device or a desktop computer. An information processing system 1300 according to the present invention includes a memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350, which are each electrically connected to the system bus 1360 . The memory system 1310 will be configured substantially the same as the memory system described above. The memory system 1310 stores data processed by the central processing unit 1330 or externally input data. Here, the above-described memory system 1310 can be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can store a large amount of data reliably in the memory system 1310. [ As the reliability increases, the memory system 1310 can save resources required for error correction and provide a high-speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention can be provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. It is clear to those who have learned.

Further, the memory device or memory system according to the present invention can be implemented in various types of packages. For example, the memory device or the memory system according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) ), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Processed Stack Package (WSP) or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

Claims (10)

Providing a substrate including a cell array region, a peripheral circuit region, and a contact region between the cell array region and the peripheral circuit region;
Forming stacked structures extending in one direction on the substrate of the cell array region and defining a trench exposing the substrate, the stacked structures comprising a plurality of electrodes stacked on the substrate;
Forming a peripheral logic structure on the substrate of the peripheral circuitry region;
Forming an insulating film covering the stacked structures and the peripheral logic structure;
Performing a first patterning process on the insulating layer to form first contact holes exposing the electrodes in the contact area;
Performing a second patterning process on the insulating layer to form second contact holes exposing the peripheral logic structure; And
And simultaneously filling a conductive material in the trench, the first contact holes, and the second contact holes. The method according to claim 1,
Filling the conductive material may include,
Forming a common source line in the trench;
Forming first contact plugs in the first contact holes; And
And forming second contact plugs in the second contact holes,
Wherein an upper surface of the common source line, an upper surface of the first contact plugs, and an upper surface of the second contact plugs are coplanar with each other. The method according to claim 1,
Wherein the second patterning step includes forming a hard mask pattern on the insulating film,
Wherein the hard mask pattern is formed so as not to completely fill the first contact holes so that air gaps defined by the lower surface of the hard mask pattern and the first contact holes are formed. The method according to claim 1,
Forming the peripheral logic structure,
Forming peripheral word lines in the substrate of the peripheral circuit region; And
And forming source and drain impurity regions on both sides of the peripheral word line,
And the second contact holes expose at least one of the peripheral word line, the source impurity region, and the drain impurity region. The method according to claim 1,
Forming vertical structures through the stacked structures and connected to the substrate; And
Further comprising forming a data storage film between the vertical structures and the electrodes,
Wherein the vertical structures include a semiconductor pattern. A substrate including a cell array region and a peripheral circuit region;
Stacked structures extending in one direction on the substrate of the cell array region, the stacked structures comprising a plurality of electrodes stacked on the substrate;
A common source structure disposed between the stacked structures adjacent to each other;
A peripheral logic structure disposed on the substrate in the peripheral circuit region; And
And a first contact plug electrically connected to the peripheral logic structure,
Wherein an upper surface of the common source structure is in coplanar with an upper surface of the first contact plugs. The method according to claim 6,
Wherein the substrate further includes a contact region disposed between the cell array region and the peripheral circuit region,
The semiconductor device further comprises second contact plugs disposed in the contact regions and connected to the electrodes,
Wherein an upper surface of the common source structure is in coplanar with an upper surface of the second contact plugs. The method according to claim 6,
And a common source region formed in the substrate below the common source structure,
Wherein the common source structure includes insulating spacers covering sidewalls of the stacked structures, and a common source line connected to the common source region through the insulating spacers. The method according to claim 6,
Said peripheral logic structure comprising:
Peripheral word lines on the substrate of the peripheral circuit area; And
Source and drain impurity regions on both sides of the peripheral word line,
And the lower contact plugs are connected to any one of the peripheral word line, the source impurity region, and the drain impurity region. The method according to claim 6,
Vertical structures connected to the substrate through the stacked structures; And
Further comprising a data storage layer interposed between the vertical structures and the electrode,
Wherein the vertical structures comprise a semiconductor pattern.

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