TW202017113A - Three dimensional memory device and method for fabricating the same - Google Patents

Abstract

A 3D memory device includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer and a channel layer. The insulating layers are alternately stacked with the conductive layers on the substrate to form a multi-layers stacking structure, wherein the multi-layers stacking structure has at least one trench penetrating through the insulating layers and the conductive layers. The memory layer covers on the multi-layers stacking structure and at least extends onto a sidewall of the trench. The cannel layer covers on the memory layer and includes an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall, wherein the string portion connects the upper portion with the lower portion and has a doping concentration substantially lower than that of the upper portion and lower portion.

Description

Three-dimensional memory element and manufacturing method thereof

This disclosure is about a non-volatile memory (non-volatile memory) element and its manufacturing method. In particular, it relates to a three-dimensional (3D) non-volatile memory element and a manufacturing method thereof.

Non-Volatile Memory (NVM) components, such as flash memory, have the characteristic that information stored in the memory unit is not lost when the power is removed. It has been widely used in solid-state mass storage applications for portable music players, mobile phones, digital cameras, etc. Three-dimensional non-volatile memory devices, such as vertical-channel (VC) three-dimensional NAND flash memory devices, have many layer stack structures, can achieve higher storage capacity, and have excellent electronic characteristics, such as Good data storage reliability and operating speed.

A typical vertical channel three-dimensional non-volatile memory device includes a multi-layer stack structure in which a plurality of parallel insulating layers and conductive layers are stacked alternately. The multi-layer stack structure includes at least one trench, and the multi-layer stack structure is divided into a plurality of ridge-shaped stack layers (ridge-shaped stacks), so that each ridge-shaped multi-layer stack has a plurality of conductive layers formed by the patterned conductive layer Bands. The three-dimensional non-volatile memory element also includes a memory layer and a channel layer. Among them, the memory layer is located on the side wall of the trench; the channel layer covers the ridge-shaped multilayer stack and the memory layer, and a plurality of memory cells are defined where each conductive strip overlaps the memory layer and the channel layer . The vertically arranged memory cells are vertically connected by a channel layer to form a memory cell string, and are electrically connected to corresponding bit lines through metal contact structures in a multi-layer structure.

However, as the number of insulating layers and conductive layers in the multi-layer structure increases, the number of memory cells in the memory cell string also increases. Not only must the current input to the memory string through the bit line be increased during operation, but also because the etching step to form the trench is not easy to control, the size of the bottom of the trench is reduced, and the width of the channel layer at the bottom of the trench is also reduced. As a result, the resistance of the device channel and the bit line remains high, which seriously affects the operation quality and reliability of the vertical channel stereoscopic non-volatile memory device.

Therefore, there is a need to provide a more advanced three-dimensional memory device and its manufacturing method to improve the problems faced by the conventional technology.

According to an embodiment of the present specification, a three-dimensional memory device is provided, which includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer, and a channel layer. The insulating layer and the conductive layer are alternately stacked on the substrate to form a multi-layer stack structure (multi-layer stack), wherein the multi-layer stack structure has at least one trench passing through the conductive layer and the insulating layer. The memory layer covers the multi-layer stacked structure, and extends to at least one side wall of the trench. The channel layer covers the memory layer, wherein the channel layer includes an upper portion, a tandem portion, and a lower portion. The upper part is adjacent to the opening of the trench; the lower part is adjacent to the bottom of the trench; the tandem part is located on the side wall of the trench for connecting the upper part and the lower part, and has an ion doping concentration substantially smaller than that of the upper part and the lower part.

According to another embodiment of the present specification, a method for manufacturing a three-dimensional memory element is provided, including the following steps: First, a multi-layer stack structure is provided on a substrate, the multi-layer stack structure includes a plurality of insulating layers and a plurality of interleaved stacks One conductive layer. Then, the multi-layer stacked structure is patterned, so that at least one trench is formed in the multi-layer stacked structure, passing through the conductive layer and the insulating layer. A memory layer is formed, covering the multilayer stack structure, and extending to at least one side wall of the trench. Subsequently, a channel layer is formed to cover the memory layer. Before filling the trench with a dielectric material, an ion doping process is performed on the channel layer, a plurality of ion dopants are implanted into the channel layer, and the channel layer is divided into at least an upper portion, a tandem portion, and a lower portion unit. Wherein, the upper portion is adjacent to the opening of the trench; the lower portion is adjacent to the bottom of the trench; the tandem portion is located on the side wall of the trench to connect the upper portion and the lower portion; and the tandem portion has substantially smaller than the upper and lower portions Ion doping concentration.

According to the above embodiments, the present invention is to provide a three-dimensional memory element and a manufacturing method thereof. This method of manufacturing a three-dimensional memory device provides a patterned multilayer stack structure on a substrate, and sequentially forms a memory layer and a channel layer on at least one trench sidewall of the multilayer stack structure. Before the trench is filled with dielectric material, an ion doping process is performed on the channel layer, and a plurality of ion dopants are implanted into the channel layer so that the channel layer is located in the first serial portion on the sidewall of the trench The ion doping concentration is substantially smaller than the ion doping concentration of the channel layer adjacent to the upper portion of the trench opening and the lower portion of the trench bottom.

Due to the doping process, the upper and lower portions of the channel layer at the bottom of the trench have charged ion dopants, which can effectively reduce the resistance of the channel layer and improve the three-dimensional memory device because of the insulating layer and conductivity in the multi-layer structure The increase in the number of layers causes the channel width to shrink locally, causing the channel resistance to rise sharply.

The invention provides a three-dimensional memory element and a manufacturing method thereof, which can improve the problem of the channel width shrinking and the channel resistance caused by the sharp increase of the channel width due to the increase of the number of insulating layers and conductive layers in the multi-layer memory structure. In order to make the above embodiments and other objects, features and advantages of the present invention more obvious and understandable, the following three-dimensional memory elements and their manufacturing methods are specifically cited as preferred embodiments, which will be described in detail in conjunction with the accompanying drawings.

However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, components, methods, and parameters. The proposed preferred embodiments are only used to illustrate the technical features of the present invention, and are not intended to limit the patent application scope of the present invention. Those with ordinary knowledge in this technical field will be able to make equivalent modifications and changes based on the description of the following description without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be denoted by the same element symbols.

Please refer to FIGS. 1A to 1F. FIGS. 1A to 1F are schematic cross-sectional views of a series of manufacturing structures for a three-dimensional memory device 100 according to an embodiment of the present invention. The method for manufacturing the three-dimensional memory device 100 includes the following steps: firstly, a substrate 101 is provided, and a multi-layer stacked structure 110 is formed on the substrate 101 (as shown in FIG. 1A ). In some embodiments of the present invention, the substrate 101 may include a dielectric isolation layer 101a. The multilayer stack structure 110 is formed on the dielectric isolation layer 101a and is in contact with the dielectric isolation layer 101a.

The multilayer stack structure 110 includes a plurality of conductive layers 111-115 and a plurality of insulating layers 121-125. The insulating layers 121-125 and the conductive layers 111-115 are along the Z-axis direction shown in FIG. 1A, and are stacked on each other on the substrate 101 and are parallel to each other. In this embodiment, the conductive layer 111 is located at the bottom layer of the multilayer stacked structure 110, and the insulating layer 125 is located at the top layer of the multilayer stacked structure 110.

The conductive layers 111-115 may be composed of metals, such as gold, copper, aluminum, alloy materials, metal oxides, or other suitable metal materials. In addition, the conductive layers 111-115 may also be composed of undoped polycrystalline or single crystal semiconductor materials, such as polycrystalline or single crystal silicon/germanium. It may also be made of doped semiconductor materials, such as n-type polysilicon doped with phosphorus (phosphor, P) or arsenic (As), or p-type polysilicon doped with boron (boron, B). In this embodiment, the conductive layers 111-115 are made of undoped polycrystalline silicon. The insulating layers 121-125 may be composed of dielectric materials, such as silicon oxide, silicon nitride, oxynitride, silicate, or other materials.

In some embodiments of the present invention, the conductive layers 111-115 and the insulating layers 121-125 may be manufactured by, for example, a low pressure chemical vapor deposition (LPCVD) process. The thickness of the insulating layers 121-125 may be substantially between 30 angstroms (Å) and 800 angstroms. The conductive layer 111 at the lowest layer and the conductive layer 115 at the uppermost layer have a thicker thickness than the other conductive layers 112-114. The thickness of the conductive layers 112-114 may be substantially between 30 angstroms and 800 angstroms. The thickness of the conductive layers 111 and 115 may be substantially between 50 angstroms and 3000 angstroms. However, in other embodiments, the thicknesses of the insulating layer and the conductive layer are not limited thereto.

Next, a patterning process 103 is performed on the multilayer stacked structure 110 to form a plurality of ridge-shaped multilayer stack layers 110a, 110b, and 110c (as shown in FIG. 1B). In some embodiments of the present invention, the patterning process 103 of the multilayer stacked structure 110 includes forming a hard mask curtain layer 102 on the multilayer stacked structure 110 and patterning the hard mask curtain layer 102. Then, the patterned hard mask layer 102 is used as an etching mask, and a part of the multilayer stack structure is removed by anisotropic etching process (for example, reactive ion etching (RIE) process) 110, by forming a trench 104 extending along the Z-axis direction in the multilayer stacked structure 110, the multilayer stacked structure 110 is divided into a plurality of ridge-shaped multilayer layers extending along the Y-axis (vertical X-axis) direction, for example The ridge-shaped multi-layered layers 110a, 110b, and 110c expose a portion of the dielectric isolation layer 101a in the substrate 101 via the trench 104. The hard mask layer 102 may be a silicon nitride layer formed on the topmost insulating layer 125 of the multilayer stack structure 110.

Then, a memory layer 106 is formed on the multilayer stacked structure 110 so as to cover the top of the ridge-shaped multilayer stacks 110a, 110b, and 110c and extend into the bottom 104c of the trench 104 (ie, a portion of the dielectric exposed by the trench 104) The isolation layer 101a) and the trench sidewall 104a. Then conformal deposition is performed on the ridge-shaped multilayer stacks 110a, 110b and 110c to form a channel layer 109 to cover the memory layer 106 (as shown in FIG. 1C).

In some embodiments of the present invention, the memory layer 106 at least includes a composite layer (ie, ONO structure) of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. However, the structure of the memory layer 106 is not limited to this. In other embodiments of the present specification, the composite layer of the memory layer 106 may also be selected from a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide-nitride -oxide, ONONO) structure, a silicon-silicon oxide-nitride-silicon-oxide-silicon (SONOS) structure, a gap-gap engineering silicon-silicon oxide-nitride Silicon-silicon oxide-silicon (bandgap engineered silicon-oxide-nitride-oxide-silicon, BE-SONOS) structure, tantalum nitride-alumina-silicon nitride-silicon oxide-silicon (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS) structure and a metal high dielectric constant energy gap engineering silicon-silicon oxide-silicon nitride-silicon oxide-silicon (metal-high-k bandgap-engineered silicon-oxide-nitride -oxide-silicon, MA BE-SONOS) structure. In this embodiment, the memory layer 106 may be an ONO composite layer made by a low-pressure chemical vapor deposition process, and the thickness is substantially between 60 angstroms and 600 angstroms.

The material constituting the channel layer 109 may include semiconductor materials, such as n-type polysilicon (or n-type epitaxial monocrystalline silicon) doped with phosphorus or arsenic, p-type polysilicon (or p-type epitaxial monocrystalline silicon) doped with boron ), undoped polysilicon, metal silicides (such as titanium silicide (TiSi), cobalt silicide (CoSi) or silicon germanium (SiGe), oxide semiconductors (oxide semiconductors), such as indium zinc oxide (InZnO) or InGaZnO or a combination of two or more of the above materials. In this embodiment, the channel layer 109 is an undoped polysilicon layer, and its thickness is substantially between 30 angstroms and 500 angstroms.

Then, an ion doping process 130 is performed on the channel layer 109, a plurality of ion dopants are implanted into the channel layer 109, and the channel layer is divided into at least an upper portion 109a, a tandem portion 109c, and a lower portion 109b (As shown in Figure 1D). Due to the characteristics of the etching process, the formed trench 104 has an upper wide and lower narrow outline, so most of the doped ions in the ion doping process 130 are more likely to be implanted in the channel layer 109 adjacent to the trench The upper portion 109a of the opening 104b of the trench 104 and the lower portion 109b located at the bottom 104c of the trench 104; and less likely to be doped on the sidewall 104a of the trench 104 to connect the tandem portion 109c of the upper portion 109a and the lower portion 109b. Therefore, the ion doping concentration in the tandem portion 109c of the channel layer 109 is substantially smaller than the ion doping concentration in the upper portion 109a and the lower portion 109b. In some embodiments of the present specification, the lower portion 109b may extend upward from the trench bottom 104c, but it does not substantially exceed the top surface 111a of the bottommost conductive layer 111 of the multilayer stack structure 110.

In some embodiments of the present specification, before the ion doping process 130 is performed, a protective layer 120 may be optionally formed on the sidewall 104a and the bottom 104c of the trench 104 (as shown in FIG. 1D) . In this embodiment, the protective layer 120 may be a silicon dioxide layer manufactured by a thermal oxidation process or a deposition process. The protective layer 120 covers the upper portion 109a, the lower portion 109b, and the tandem portion 109c of the channel layer 109 to adjust the doping depth of the ion doping process 130 and protect the channel layer 109 from ions. The bombardment was damaged.

Next, a dielectric layer 128 is formed to fill the trench 104 and cover the channel layer 109 (as shown in FIG. 1E). In some embodiments of the present specification, the formation of the dielectric layer 128 may include the following steps: First, the trench 104 is filled with an insulating material, such as silicon oxide, and covers the multilayer stack structure 110. After that, a planarization step, such as chemical mechanical polishing, is performed to remove a portion of the insulating material above the multilayer stack structure 110.

After that, at least one contact plug is formed on each of the ridge-shaped multilayer stacks 110a, 110b and 110c, respectively passes through the dielectric layer 128 and the protective layer 120, and is located above the ridge-shaped multilayer stacks 110a, 110b and 110c The upper portion 109a of the channel layer 109 contacts. For example, in this embodiment, the contact plugs 129A and 129B are formed on the ridge-shaped multilayer stack 110a; the contact plug 129C is formed on the ridge-shaped multilayer stack 110b; the contact plugs 129D and 129E are formed on the ridge-shaped multilayer stack On layer 110c.

Next, an etching process is performed again to remove a portion of the dielectric layer 128 and a portion of the upper portion 109a of the channel layer 109 on the top of the ridge multilayer stacks 110a and 110c, and a portion of the upper portion 109a of the channel layer 109 of the ridge multilayer stack 110a Cut into the first pad 109a1 and the second pad 109a2 separately from each other, and then electrically isolate the contact plugs 129A and 129B; and cut the upper part 109a of the channel layer 109 located on the ridge-shaped multilayer stack 110c into each other The separated fourth pad 109a4 and fifth pad 109a5 further electrically isolate the contact plugs 129D and 129E.

In this embodiment, the contact plugs 129A and 129B on the top of the ridge multilayer stack 110a are in electrical contact with the first pad 109a1 and the second pad 109a2, respectively; the contact plugs on the top of the ridge multilayer stack 110b 129C is in electrical contact with the upper portion 109a of the channel layer 109 (hereinafter referred to as the third pad 109a3) located on the top of the ridge multilayer stack 110b; and the contact plugs 129D and 129E located on the top of the ridge multilayer stack 110c are The four pads 109a4 are in electrical contact with the fifth pad 109a5.

The second pad 109a2 communicates with the third pad 109a3 through a part of the channel layer 109 (including the lower portion 109b and the tandem portion 109c) between the ridge-shaped multilayer stacks 110a and 110b, thereby forming a U-shaped channel, which will form A plurality of memory cells 131 at the intersection of the U-shaped channel layer 109, the memory layer 106, and the conductive layers 112-114 are connected in series to form a U-shaped memory cell string 132 between the ridge-shaped multilayer stacks 110a and 110b. Similarly, the fourth pad 109a4 passes through a part of the channel layer 109 (including the lower part 109b and the tandem part 109c) between the ridge multilayer stacks 110b and 110c and the third pad on the top of the ridge multilayer stack 110b 109a3 is turned on, so that another U-shaped memory cell string 133 is formed between the ridge-shaped multilayer stacks 110b and 110c.

In this embodiment, the transistor 134 formed on the intersection of the channel layer 109, the memory layer 106, and the conductive layer 115 of the ridge-shaped multilayer stack 110a is connected in series with a plurality of memory cells 131, which can be used as a U-shaped memory cell string The String Select Line (SSL) switch of column 132. The transistor 135 formed at the intersection of the channel layer 109, the memory layer 106, and the conductive layer 115 of the ridge-shaped multilayer stack 110b is connected in series with a plurality of memory cells 131, and can be used as a ground selection line for the U-shaped memory cell string 132 (Ground Select Line, GSL) switch. The transistors 136 and 137 formed on the intersections of the channel layer 109, the memory layer 106 and the conductive layer 111 of the ridge-shaped multilayer stacks 110a and 110b, respectively, are connected in series with a plurality of memory cells 131 and can be used as a U-shaped memory cell series 132 Inversion Assist Gate (IG) switch.

Subsequently, through a series of subsequent processes, the contact plugs 129B and 129D are connected to the corresponding bit lines (not shown), and the contact plugs 129C are connected to the common source line (not shown) to complete the stereo memory Preparation of device 100 (as shown in FIG. 1F).

Since, as mentioned above, the trench 104 has an outer width and a narrower outer contour, the channel width of the U-shaped memory cell strings 132 and 133 at the bottom 104c of the trench will be tightened, causing a sharp increase in the channel resistance. Through the ion doping process 130, implanting charged ion dopants into the lower portion 109b of the channel layer 109 at the bottom 104c of the trench can effectively reduce the channel resistance of the U-shaped memory cell strings 132 and 133. Similarly, implanting the upper portion 109a of the charged ion doped by the ion doping process 130 can further reduce the overall channel resistance of the U-shaped memory cell strings 132 and 133, which improves the operation quality of the three-dimensional memory device 100 and Technical advantages to reduce power consumption.

It is worth noting that although the three-dimensional memory device 100 shown in FIG. 1F is a three-dimensional memory device having a U-shaped memory cell tandem structure, it is reduced by the ion doping process 130 described in the foregoing embodiment The method of the memory cell serial channel resistance value of the three-dimensional memory device 100 is not limited to be applicable only to the three-dimensional memory device having a U-shaped memory cell serial structure. For example, in other embodiments of the present specification, this method is also suitable for a three-dimensional memory device having a bottom source structure.

Please refer to FIGS. 2A to 2G. FIGS. 2A to 2G are schematic cross-sectional views of a series of manufacturing structures of the three-dimensional memory device 200 according to another embodiment of the present invention. The method for manufacturing the three-dimensional memory device 200 includes the following steps: firstly, a substrate 201 is provided and a multilayer stacked structure 110 is formed on the substrate 201 (as shown in FIG. 2A). In some embodiments of the present invention, the substrate 201 may include a polysilicon layer 201a. The multilayer stacked structure 110 is formed on the polysilicon layer 201a and contacts the polysilicon layer 201a. Since the materials and manufacturing procedures of the multilayer stack structure 110 are described in detail above, they are not repeated here.

Next, a patterning process 203 is performed on the multilayer stacked structure 110 to form a plurality of ridge-shaped multilayer stacked layers 210a, 210b, and 210c (as shown in FIG. 2B). In some embodiments of the present invention, the patterning process 203 of the multilayer stacked structure 210 includes forming a hard mask curtain layer 202 on the multilayer stacked structure 110 and patterning the hard mask curtain layer (not shown). Then, the patterned hard mask layer 202 is used as an etching mask, and the multi-layer stack structure 110 is etched by an anisotropic etching process, such as a reactive ion etching process, so that the multi-layer stack structure 110 is formed along the Z-axis direction The extended trench 204 divides the multilayer stacked structure 110 into a plurality of ridge-shaped multilayer stacks extending along the Y-axis direction, such as ridge-shaped multilayer stacks 210a, 210b, and 210c, and a part of the polysilicon layer in the substrate 201 201a is exposed through the groove 204.

Then, a memory layer 206 is formed on the ridge-shaped multilayer stacks 210a, 210b, and 210c so as to cover the top of the ridge-shaped multilayer stacks 210a, 210b, and 210c and extend into the bottom 204c of the trench 204 (that is, exposed by the trench 204 A portion of the outer polysilicon layer 201a) and the trench sidewall 204a. Then, conformal deposition is performed on the ridge-shaped multilayer stacks 210a, 210b, and 210c to form a first channel film 219a, which covers the memory layer 206 (as shown in FIG. 2C).

Next, a portion of the first channel film 219a and the memory layer 206 at the bottom of the trench 204 are removed by an etching process to expose a portion of the polysilicon layer 201a at the bottom of the trench 204. After that, a conformal deposition is performed again to form a second channel film 219b on the first channel film 219a and the bottom 204c of the trench 204, integrated with the first channel film 219a into a channel layer 209, and located at the bottom of the trench 204 A portion of the polysilicon layer 201a exposed at 204c is turned on (as shown in FIG. 2D).

An ion doping process 230 is performed, and a plurality of ion dopants are implanted into the channel layer 209 (as shown in FIG. 2E). Since the channel layer 209 covers the top of the ridge multilayer stacks 210a, 210b, and 210c and extends into the trench sidewalls 204a and the bottom 204c of the trench 204, most of the doped ions in the ion doping process 230 are more likely to be implanted The access channel layer 209 is adjacent to the upper portion 209a of the opening 204b of the trench 204 and the lower portion 209b of the bottom 204c of the trench 204; it is less likely to be doped on the sidewall 204a of the trench 204 to connect the upper portion 209a and the lower portion The serial portion 209c of 209b. Therefore, the ion doping concentration in the tandem portion 209c of the channel layer 209 is substantially smaller than the ion doping concentration in the upper portion 209a and the lower portion 209b. In some embodiments of the present specification, the lower portion 209b may extend upward from the trench bottom 204c, but it does not substantially exceed the top surface 111a of the bottommost conductive layer 111 of the multilayer stacked structure 110.

After that, a dielectric layer 228 is formed to fill the trench 204 and cover the channel layer 209 (as shown in FIG. 2F).

Next, a plurality of contact plugs 229A-229F are formed on each of the ridge-shaped multilayer stacks 210a, 210b, and 210c, respectively passing through the dielectric layer 228, and communicating with the channel above the ridge-shaped multilayer stacks 210a, 210b, and 210c The upper portion 209a of the layer 209 is in contact. For example, in this embodiment, the contact plugs 229A and 229B are formed on the ridge-shaped multilayer stack 210a; the contact plugs 229C and 229D are formed on the ridge-shaped multilayer stack 210b; the contact plugs 229E and 229F are formed on the ridge On the multilayer stack 210c.

Then, another etching process is performed to remove a portion of the dielectric layer 228 and a portion of the upper portion 209a of the channel layer 209 on the top of the same ridge multilayer stack, and the portion of the upper layer 209a of the channel layer 209 on the same ridge multilayer stack Cut into multiple pads separated from each other. Furthermore, a plurality of contact plugs located above the same ridge-shaped multilayer stack are electrically isolated. For example, in this embodiment, the above etching process may divide the upper portion 209a of the channel layer 209 on the ridge-shaped multilayer stack 210a into a first pad 209a1 and a second pad 209a2, thereby separating the contact plugs 229A and 229B Electrical isolation. The above etching process can separate the upper portion 209a of the channel layer 209 on the ridge multilayer stack 210b into a third pad 209a3 and a fourth pad 209a4, thereby electrically isolating the contact plugs 229C and 229D. The above etching process may divide the upper portion 209a of the channel layer 209 on the ridge multilayer stack 210c into a fifth pad 209a5 and a sixth pad 209a6, thereby electrically isolating the contact plugs 229E and 229F.

The two contact plugs 229A and 229B located on the top of the ridge multilayer stack 210a are in electrical contact with the first pad 209a1 and the second pad 209a2, respectively. The two contact plugs 229C and 229D located on the top of the ridge multilayer stack 210b are in electrical contact with the third pad 209a3 and the fourth pad 209a4, respectively. The two contact plugs 229E and 229F located on the top of the ridge multilayer stack 210c are in sexual contact with the fifth pad 209a5 and the sixth pad 209a6, respectively. Each of the first pad 209a1 to the sixth pad 209a6 will be formed on the channel layer 209 and the memory layer through a part of the channel layer 209 (including the lower portion 209b and the tandem portion 209c) on the sidewall of the trench 204, respectively A plurality of memory cells 231 at the intersection of 206 and conductive layers 112-114 are connected in series to form a series of memory cells 232 parallel to the Z axis. Among them, the plurality of transistors 234 formed on the intersections of the channel layer 209, the memory layer 206 and the conductive layer 115 of the ridge-shaped multilayer stacks 210a, 210b and 210c are respectively in correspondence with the plurality of memory cells 231 of the corresponding memory cell series 232 The serial connection can be used as a serial selection line (SSL) switch corresponding to the memory cell serial 232, respectively. The plurality of transistors 235 formed on the intersections of the channel layer 209, the memory layer 206, and the conductive layer 111 of the ridge-shaped multilayer stacks 210a, 210b, and 210c are respectively connected in series with the plurality of memory cells 231 corresponding to the memory cell series 232 It can be used as the ground selection line (GSL) switch corresponding to the memory cell string 232, respectively. The polysilicon layer 201a can be used as a common source line at the bottom of these memory cell strings 232.

Subsequently, through a series of subsequent processes (not shown), the contact plugs 229A-229F are connected to the corresponding bit lines (not shown), respectively, to complete the preparation of the three-dimensional memory device 200 as shown in FIG. 2G .

By implanting charged ion dopants into the upper portion 209a and the lower portion 209b of the channel layer 209 through the ion doping process 230, the resistance value of the overall channel can be effectively reduced to improve the operation quality of the three-dimensional memory device 200 while reducing power Wear out.

According to the above embodiments, the present invention is to provide a three-dimensional memory element and a manufacturing method thereof. This method of manufacturing a three-dimensional memory device provides a patterned multilayer stack structure on a substrate, and sequentially forms a memory layer and a channel layer on at least one trench sidewall of the multilayer stack structure. Before the trench is filled with dielectric material, an ion doping process is performed on the channel layer, and a plurality of ion dopants are implanted into the channel layer so that the channel layer is located in the first serial portion on the sidewall of the trench The ion doping concentration is substantially less than the ion doping concentration of the channel layer adjacent to the first upper portion of the trench opening and the lower portion of the trench bottom.

Due to the doping process, the lower part of the channel layer at the bottom of the trench can have charged ion dopants, which can effectively reduce the resistance of the channel layer and improve the volume of the three-dimensional memory device because of the number of insulating layers and conductive layers in the multi-layer structure The increase causes the channel width to shrink locally, causing the channel resistance to rise sharply.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be deemed as defined by the scope of the attached patent application.

100, 200: Three-dimensional memory device 101, 201: substrate 101a: dielectric isolation layer 104, 204: trench 104a, 204a: trench sidewall 104b, 204b: trench opening 104c, 204c: trench bottom 109, 209 : Channel layers 109a, 209a: upper part 109c, 209c: tandem 109b, 209c: lower part 110: multilayer stacked structure 111-115: conductive layer 111a: top surface of conductive layer 120: protective layer 128, 228: dielectric layer 129A-129E, 229A-229F: contact plugs 109a1-109a5, 209a1-209a6: pads 110a, 110b, 110c, 210a, 210b, 210c: ridged multilayer stack 121-125: insulating layers 130, 230: ion doping Hybrid process 131, 1231: memory cells 132, 133, 232: memory cell string 134, 135, 136, 137, 234, 235: transistor 201a: polysilicon layer 106, 206: memory layer 219a, 219b: channel membrane

In order to make the above-mentioned embodiments of the present invention and other objects, features and advantages more obvious and understandable, a few preferred embodiments are described in detail in conjunction with the drawings, as follows: Figures 1A to 1F are based on A schematic cross-sectional view of a series of manufacturing structures for a three-dimensional memory device according to an embodiment of the present invention; and FIGS. 2A to 2G illustrate a three-dimensional memory device according to another embodiment of the present invention Schematic diagram of a series of process structure.

100: stereo memory element

101: substrate

101a: dielectric isolation layer

109: Channel layer

109c: Serial part

109b: Lower part

111-115: conductive layer

111a: the top surface of the conductive layer

120: protective layer

128: dielectric layer

129A-129E: Contact plug

109a1-109a5: solder pad

110a, 110b, 110c: ridged multilayer stack

121-125: Insulation

131: Memory Cell

134, 135, 136, 137: transistor

132, 133: memory cell series

Claims (10)

A three-dimensional memory device includes: a substrate; a plurality of conductive layers on the substrate; a plurality of insulating layers on the substrate, interleaved with the conductive layers to form a multi-layer stack structure (multi- layer stacks), wherein the multilayer stack structure has at least one trench, passing through the conductive layers and the insulating layers; a memory layer covering the multilayer stack structure, and extending at least onto a first side wall of the trench And a channel layer covering the memory layer, wherein the channel layer includes a first upper portion, a first tandem portion, and a lower portion, the first upper portion is adjacent to an opening of the trench; the lower portion The portion is adjacent to the bottom of the trench; the first tandem portion is located on the first side wall for connecting the first upper portion and the lower portion, and has an ion substantially smaller than the first upper portion and the lower portion Doping concentration. According to the three-dimensional memory device described in item 1 of the patent application scope, the channel layer further includes: a second upper portion adjoining the opening of the groove and isolated from the first upper portion; and a second tandem portion Located on a second side wall of the trench, one end of the second tandem portion is connected to the second upper portion, and the other end of the second tandem portion is connected to the first tandem portion through the lower portion, And the second tandem portion has an ion doping concentration that is substantially smaller than the second upper portion and the lower portion. The three-dimensional memory device as described in item 2 of the patent application scope, wherein the substrate includes a dielectric isolation layer in contact with the multilayer stack structure, and the bottom of the trench is located in the dielectric isolation layer. The three-dimensional memory device as described in item 1 of the patent application range, wherein the substrate includes a polysilicon layer in contact with the multilayer stack structure, and the bottom of the trench is located in the polysilicon layer. The three-dimensional memory device as described in item 1 of the patent scope, wherein the lower portion extends upward from the bottom of the trench, but does not substantially exceed a top surface of one of the lowermost layers of the conductive layers. The three-dimensional memory device as described in item 1 of the patent application scope further includes: a dielectric layer filling the trench and covering the channel layer; and a contact plug passing through the dielectric layer and communicating with the The first upper part is in contact. A method for manufacturing a three-dimensional memory element, comprising: forming a multi-layer stack structure on a substrate, the multi-layer stack structure including a plurality of insulating layers and a plurality of conductive layers stacked alternately; patterning the multi-layer stack structure, whereby Forming at least one trench in the multilayer stack structure, passing through the conductive layers and the insulating layers; forming a memory layer, covering the multilayer stack structure, and extending at least to a sidewall of the trench; forming a channel layer , Covering the memory layer; and before filling the trench with a dielectric material, an ion doping process is performed on the channel layer, a plurality of ion dopants are implanted into the channel layer, and the channel layer is at least separated Into an upper part, a series of rows and a lower part; wherein, the upper part is adjacent to an opening of the trench; the lower part is located at the bottom of the trench; the first serial part is located on the side wall for connection The upper portion and the lower portion; and the tandem portion has an ion doping concentration that is substantially smaller than the upper portion and the lower portion. The method for manufacturing a three-dimensional memory device as described in item 7 of the patent application scope further includes: forming a dielectric layer to fill the trench and covering the channel layer; and forming at least two contact plugs through the dielectric The electrical layer is in contact with the upper portion; and an etching process is performed to remove a portion of the dielectric layer and a portion of the channel layer on top of one of the multilayer stack structures to electrically isolate the at least two contact plugs. The method for manufacturing a three-dimensional memory device as described in item 7 of the patent application scope, wherein the substrate includes a dielectric isolation layer in contact with the multilayer stack structure, and the bottom of the trench is located in the dielectric isolation layer. The method for manufacturing a three-dimensional memory device as described in item 7 of the patent application range, wherein the substrate includes a polysilicon layer in contact with the multilayer stack structure, and the bottom of the trench is located in the polysilicon layer.

Images