TWI698985B - Three dimensional memory device and method for fabricating the same - Google Patents

Abstract

A 3D memory device includes a multi-layers stacking structure, a memory layer, a channel layer, and a switching element. The multi-layers stacking structure includes a plurality of conductive layers, a plurality of insulating layers, and an opening. The insulating layer and the conductive layer are stacked along a stacking direction in a staggered manner, and the opening passes through the conductive layer. The memory layer is disposed in the opening and at least partially overlaps with the conductive layers. The channel layer is disposed in the opening and overlaps the memory layer. The switching element includes a channel plug disposed over the multi-layers stacking structure and electrically connecting to the channel layer, a gate dielectric layer surrounding the channel plug, and a gate surrounding the gate dielectric layer.

Description

Three-dimensional memory element and manufacturing method thereof

The present disclosure relates to a memory device and its manufacturing method, and more particularly to a three dimensional (3D) memory device with high memory density and its manufacturing method.

Memory components are important data storage components in portable electronic devices such as MP3 players, digital cameras, notebook computers, smart phones, etc. With the increase of various applications and the improvement of functions, the demand for memory components also tends to be smaller in size and larger in memory capacity. In response to this demand, designers have turned to develop a three-dimensional memory device that includes multiple plane of memory cells stacked, such as vertical-channel (VC) three-dimensional NAND flash. Memory components.

A typical NAND flash memory device uses a thin film transistor with a multilayer dielectric charge trapping structure as the memory cell of the memory cell series and the series/ground selection switch, and adopts higher The drain or source voltage and the lower gate voltage (or floating) can induce band-to-band tunneling (BBT) to generate a gate and cause drain leakage current (gate Induced drain leakage current, GIDL) to erase the memory cell string. However, after the holes generated by band-to-band tunneling are injected into the gate oxide layer through the acceleration of the transverse electric field, they often cause charge accumulation, which makes it easy to make the serial/ground selection switch of the charge trapping thin film transistor. The subsequent write operation cannot be turned on normally, causing the operation to fail.

Therefore, there is a need to provide an advanced three-dimensional memory device and a manufacturing method thereof to solve the problems faced by the conventional technology.

An embodiment of this specification discloses a three-dimensional memory device. The three-dimensional memory device includes: the three-dimensional memory device includes multi-layer stacks, a memory layer channel layer, and a switching device. The multilayer stack structure includes a plurality of conductive layers, a plurality of insulating layers, and at least one opening. The insulating layer and the conductive layer are stacked alternately along a stacking direction, and the opening passes through the conductive layer. The memory layer is located in the opening and at least partially overlaps the conductive layer. The channel layer is located in the opening and overlaps the memory layer. The switching element includes: a channel plug located above the multilayer stack structure and electrically connected to the channel layer; a gate dielectric layer surrounding the channel plug; and a gate surrounding the gate dielectric layer.

Another embodiment of this specification discloses a method for fabricating a three-dimensional memory device, which includes the following steps: first, a multilayer stack structure including a plurality of conductive layers, a plurality of insulating layers and at least one opening is provided. Wherein, the insulating layer and the conductive layer are stacked alternately along a stacking direction, and the opening passes through the conductive layer. In the mouth A memory layer at least partially overlapping the conductive layer is formed. A channel layer at least partially overlapping with the memory layer is formed in the opening. A switching element is formed above the multilayer stack structure, so that the switching element includes: a channel plug electrically connected to the channel layer; a gate dielectric layer surrounding the channel plug without a dielectric charge trapping structure; and a surrounding gate dielectric The gate of the electrical layer.

According to the above-mentioned embodiments, this specification discloses a three-dimensional memory device and a manufacturing method thereof. It uses a switch element without a gate dielectric layer of a dielectric charge trapping structure as a series selection switch/ground selection switch for the series of memory cells in the three-dimensional memory element. Therefore, there is no need to erase the memory cell string in a way that the band-to-band tunneling generates a gate and causes a drain leakage current. It can avoid the use of charge trapping thin film transistors as the tandem selector switch/grounding selector switch, because holes are injected into the gate oxide layer, causing charge accumulation, causing the tandem selector switch/grounding selector switch to fail to open normally during write operations. The problem of failure.

In some embodiments of this specification, this structure can be applied to a three-dimensional memory device with a gate-surrounded structure, a three-dimensional memory device with a single-gate vertical channel (single-gate vertical channel, SGVC) structure, and a U U-shaped vertical channel (U-shaped vertical channel) structure of three-dimensional memory device, cylindrical channel (cylindrical channel) structure of memory cell series of three-dimensional memory device or semi-cylindrical channel (hemi-cylindrical channel) structure Three-dimensional memory components.

100, 200, 300: Three-dimensional memory components

101: Substrate

102: buried oxide layer

102a: The bottom of the buried oxide layer

103: O-shaped opening

103b: Side wall of O-shaped opening

103a: The bottom of the O-shaped opening

105: Dielectric cylinder

105a: The top surface of the dielectric cylinder

105b: The bottom of the dielectric column

106: Falling on the contact pad

108: groove

109: insulating material

110: Multi-layer stacked structure

110a: The top surface of the multilayer stack structure

112A: Internal connection structure

112B: Internal connection structure

114: memory layer

120: conductive layer

122: bottom gate layer

122a: the bottom of the bottom gate layer

124: Channel layer

125: Dielectric protective layer

126: gate material layer

127: Dielectric cover layer

128A, 128B: through hole

129: Gate Dielectric Layer

130: insulating layer

131: conductive film

132: channel plug

140, 145: memory cell

141, 141a, 141b: tunneling transistor switch

144: Gate surrounding memory cell series

146: U-shaped memory cell string

147A, 147B, 347: metal-oxide-semiconductor transistor switching elements

150: Patterned hard mask layer

201: source conductor layer

202: Interposer plug

241a, 241b: tunneling transistor switch

246A, 246B: Memory cell series

S1-S11: Tangent

H1: Height difference

N+: n-type dopant

BL: bit line

CS: Common source line

U1, U2: U-shaped profile

In order to have a better understanding of the above and other aspects of this specification, the following specific examples are given in conjunction with the accompanying drawings and detailed descriptions are as follows: Figure 1A is a structure of a multilayer stacked structure drawn according to an embodiment of the present invention Perspective view; Figure 1B is a cross-sectional view of the structure drawn along the tangent line S1 of Figure 1A; Figure 2A is a drawing showing the patterning process of the multilayer stack structure of Figure 1A to form a plurality of O-shaped openings After the top view of the structure; Figure 2B is a cross-sectional view of the structure drawn along the tangent line S2 shown in Figure 2A; Figure 3A is a diagram showing the formation of a memory layer and a channel layer on the structure shown in Figure 2A And a top view of the structure after a plurality of dielectric pillars; Figure 3B is a cross-sectional view of the structure drawn along the tangent line S3 of Figure 3A; Figure 4A is a diagram showing a return to the structure shown in Figure 3A The top view of the structure after the etching process; Fig. 4B is a cross-sectional view of the structure drawn along the tangent line S4 shown in Fig. 4A; Fig. 5A shows the formation of a plurality of drops on the structure shown in Fig. 4A The top view of the structure after the contact pad; FIG. 5B is a cross-sectional view of the structure along the tangent line S5 of FIG. 5A; Figure 6A is a top view of the structure after forming a dielectric protective layer, a gate material layer and a dielectric cover layer on the structure shown in Figure 5A; Figure 6B is drawn along the tangent line S6 of Figure 6A Figure 7A is a top view of the structure after forming a through hole on the structure shown in Figure 6A; Figure 7B is a cross-sectional view of the structure shown along the line S7 of Figure 7A; Fig. 8A is a top view of the structure after forming a gate dielectric layer on the structure shown in Fig. 7A; Fig. 8B is a cross-sectional view of the structure taken along the line S8 of Fig. 8A; Fig. 9A is A top view of the structure after removing a part of the dielectric protection layer in the structure of FIG. 8A; FIG. 9B is a cross-sectional view of the structure along the tangent line S9 of FIG. 9A; FIG. 10A is a diagram showing A top view of the structure after forming a plurality of channel plugs in the structure of Figure 9A; Figure 10B is a cross-sectional view of the structure drawn along the line S10 of Figure 10A; Figure 11A is shown in Figure 10A A perspective view of the structure after a plurality of grooves are formed on the structure shown; Figure 11B is a cross-sectional view of the structure taken along the line S11 of Figure 11A; Figures 12A and 12B are perspective views and cross-sections of a three-dimensional memory device according to an implementation of this specification. Figure 13 is a cross-sectional view of a three-dimensional memory device according to another embodiment of this specification; and Figure 14 is a three-dimensional memory device according to another embodiment of this specification The structure section view.

This manual provides a method for manufacturing a three-dimensional memory device, which can solve the problem that the drain leakage current of the serial/ground selection switch cannot be turned on normally due to the gate electrode. In order to make the above-mentioned embodiments and other objectives, features, and advantages of this specification more comprehensible, a memory device and its manufacturing method are specifically cited as a preferred embodiment, and will be described in detail with the accompanying drawings.

However, it must be noted that these specific implementation cases and methods are not intended to limit the present invention. The present invention can still be implemented with other features, elements, methods and parameters. The preferred embodiments are only used to illustrate the technical features of the present invention, and not to limit the scope of the present invention. Those with ordinary knowledge in this technical field will be able to make equivalent modifications and changes based on the description of the following specification without departing from the spirit of the present invention. In the different embodiments and drawings, the same elements will be represented by the same element symbols.

The method of manufacturing a three-dimensional memory device 100 includes the following steps: first, a substrate 101 is provided, and a multilayer stack structure 110 is formed on the substrate 101. Please refer to FIG. 1A and FIG. 1B. FIG. 1A is a perspective view of a multilayer stack structure 110 according to an embodiment of the present invention. FIG. 1B is a cross-sectional view of the structure along the tangent line S1 of FIG. 1A. The multi-layer stack structure 110 includes a plurality of conductive layers 120 and a plurality of insulating layers 130 alternately stacked on the substrate 101.

In some embodiments of the present invention, a bottom gate layer 122 and a buried oxide layer 102 may be further included between the substrate 101 and the multilayer stack structure 110. For example, in this embodiment, the buried oxide layer 102 is formed on the surface of the substrate 101 by a thermal oxidation process; the bottom gate layer 122 is formed on the buried oxide layer 102 by depositing conductive materials. The conductive layer 120 and the insulating layer 130 in the multi-layer stack structure 110 are stacked along the Z-axis direction (stacking direction) shown in FIG. 1B and alternately stacked above the bottom gate layer 122. In other embodiments of the present invention, the buried oxide layer 102 may also be formed on the substrate 101 by deposition.

The conductive layer 120 may be made of metal materials (for example, gold, copper, aluminum, tungsten or the above alloys), semiconductor materials (for example, doped or undoped polycrystalline or single crystal silicon/germanium) or other suitable materials. . The insulating layer 130 may be made of a dielectric material, such as silicon oxide, silicon nitride, oxynitride, silicate, or other materials. The buried oxide layer 102 may include silicon oxide. The material constituting the conductive layer 120 may be the same as or different from the material constituting the bottom gate layer 122. The buried oxide layer 102 may be made of the same or different material as the insulating layer 130.

Then, a patterning process is performed on the multilayer stack structure 110 to form a plurality of O-shaped openings 103 passing through the conductive layer 120 and the insulating layer 130. Please refer to FIGS. 2A to 2B. FIG. 2A shows a top view of the structure after performing a patterning process on the multilayer stack structure 110 of FIG. 1A to form a plurality of O-shaped openings 103; FIG. 2B is along The cross-sectional view of the structure shown by the tangent line S2 shown in FIG. 2A.

In some embodiments of this specification, the patterning process of the multilayer stack structure 110 includes forming a patterned hard mask layer 150 on the multilayer stack structure 110, and then using the patterned hard mask layer 150 as an etching mask, by An anisotropic etching process, such as a Reactive Ion Etching (RIE) process, removes a part of the multilayer stack structure 110, thereby forming the multilayer stack structure 110 along the Z axis direction A plurality of O-shaped openings 103 extending.

In this embodiment, the patterning process for forming these O-shaped openings 103 stops in the buried oxide layer 102, so that a part of the conductive layer 120, a part of the insulating layer 130, a part of the bottom gate layer 122 and a part of the The buried oxide layer 102 is exposed to the outside through the O-shaped opening 103. In other words, these O-shaped openings 103 do not pass through the bottom 102a of the buried oxide layer 102, and expose the semiconductor material of the substrate 101 to the outside. The height of the bottom 103a of the O-shaped opening 103 from the base 101 is substantially higher than the bottom surface 102a of the buried oxide layer 102. However, it is worth noting that the depth of the O-shaped opening 103 is not limited to this. For example, in another embodiment, the patterning process for forming the O-shaped opening 103 can be stopped in the bottom gate layer 122. That is, the O-shaped opening 103 does not pass through the bottom gate layer 122 and exposes the buried oxide layer 102 to the outside. The bottom 103a of the O-shaped opening 103 can be located (but not limited to this) starting from the bottom 122a of the bottom gate layer 122, and the distance upward is about one third of the thickness of the bottom gate layer 122.

The O-shaped opening 103 described in this specification refers to the top surface 110a of the multilayer stack structure 110 extending along the Z-axis direction toward the substrate 101 into the multilayer stack structure 110, thereby forming a parallel multilayer stack The O-shaped cross-sectional profile of the top surface 110a of the structure 110 is a recess structure. In some embodiments of the present specification, the O-shaped cross-sectional profile may be, for example, an ellipse, circle, oval, or rounded rectangle, while in the embodiments of the present specification, the O-shaped cross-sectional profile is an ellipse. According to the material of the conductive layer 120 and the insulating layer 130 and the better control of the etching depth in the multilayer stack structure 110, the size of the ellipse near the top surface 110a of the multilayer stack structure 110 is larger than the size near the bottom 122a of the bottom gate layer 122 This design can help balance the control capabilities of the upper and lower ends of the multilayer stack structure 110 in subsequent operations.

Thereafter, a memory layer 114 and a channel layer 124 are sequentially formed on the sidewall 103b and the bottom 103a of each O-shaped opening 103. Please refer to FIGS. 3A and 3B. FIG. 3A shows a top view of the structure after forming a memory layer 114, a channel layer 124, and a plurality of dielectric pillars 105 on the structure shown in FIG. 2A; FIG. 3B It is a cross-sectional view of the structure drawn along the tangent line S3 in FIG. 3A. In some embodiments of this specification, the step of forming the memory layer 114 and the channel layer 124 includes: using a deposition process, such as a Low Pressure Chemical Vapor Deposition (LPCVD) process, to form on the multilayer stack structure 110 The memory layer 114 is blanketed on the sidewall 103b and the bottom 103a of each O-shaped opening 103. Then, another deposition process, such as a low-pressure chemical vapor deposition process, is used to form a channel layer 124 on the memory layer 114.

In some embodiments of this specification, the memory layer 114 includes at least one composite layer of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer (ie, an ONO structure). However, the structure of the memory layer 114 is not limited to this. In some other embodiments of this specification, the composite layer of the memory layer 114 can also be selected from a silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide-nitride -oxide, ONONO) structure, a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a band gap engineering silicon-silicon oxide-nitride Silicon-silicon oxide-silicon (bandgap engineered silicon-oxide-nitride-oxide-silicon, BE-SONOS) structure, tantalum nitride-aluminum oxide-silicon (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS) structure and a metal-high-k bandgap-engineered silicon-oxide-nitride (metal-high-k bandgap-engineered silicon-oxide-nitride) -Oxide-silicon, MA BE-SONOS) structure is a group. The material constituting the channel layer 124 may include semiconductor materials (for example, polysilicon), metal silicides (for example, titanium silicide (TiSi), cobalt silicide (CoSi) or silicon germanium (SiGe)), oxide semiconductors (oxide semiconductors) (E.g. indium zinc oxide (InZnO) or indium gallium zinc oxide (InGaZnO)) or a combination of two or more of the above materials. In this embodiment, the memory layer 114 may be an ONO composite layer, and the channel layer 124 may be a polysilicon layer.

Then, using the patterned hard mask layer 150 on the top surface 110a of the multilayer stack structure 110 as a stop layer, a planarization process (such as Chemical-Mechanical Polishing (CMP)) is performed to remove the patterned hard mask layer 150 on the multilayer stack structure 110. A part of the memory layer 114 and a part of the channel layer 124 above the top surface 110a. Thereby, a plurality of memory cells 140 are formed at the plurality of intersections of each conductive layer 120, the memory layer 114 and the remaining part of the channel layer 124; and on the bottom gate layer 122, the memory layer 114 and the channel layer 124 At each intersection, at least one tunnel field-effect transistor switch 141 is formed. Among them, a plurality of memory cells 140 and tunneling transistor switches 141 located in each O-shaped opening 103 can be connected in series to form a gate-all-around (GAA) through the corresponding channel layer 124式Memory cell series 144.

The O-shaped opening 103 is filled with a dielectric material to form a dielectric column 105. In some embodiments of this specification, the formation of the dielectric column 105 may include the following steps: first, an insulating material, such as silicon oxide, is deposited on the multilayer stack structure 110 and each O-shaped opening 103 is filled. After that, using the patterned hard mask layer 150 as a stop layer, a planarization step, such as chemical mechanical polishing, is performed to remove a part of the insulating material above the top surface 110a of the multilayer stack structure 110, in each O-shaped opening 103 , Forming a dielectric column 105 having an O-shaped cross-sectional profile of the top surface 110a of the parallel multilayer stack structure 110 (as shown in FIG. 3B).

Then, a plurality of switching elements are formed on the top surface 110a of the multilayer structure 110. Perform an etch-back process to remove a portion of the dielectric material on the top of the dielectric column 105 through each O-shaped opening, so that the top surface 105a of the dielectric column 105 and the top surface 110a of the multilayer structure 110 There is a height difference (distance) H1, and a part of the channel layer 124 is exposed to the outside. Please refer to FIGS. 4A and 4B. FIG. 4A shows the top view of the structure after the etch-back process is performed on the structure shown in FIG. 3A; FIG. 4B is along the tangent line S4 shown in FIG. 4A. A cross-sectional view of the structure shown.

Then, a contact pad 106 is formed above the dielectric column 105 in each O-shaped opening 103. Please refer to Figures 5A and 5B. Figure 5A shows a top view of the structure after forming a plurality of contact pads 106 on the structure shown in Figure 4A; Figure 5B is along the tangent line of Figure 5A The cross-sectional view of the structure shown in S5. In some embodiments of this specification, the formation of the landing contact pad 106 includes the following steps: first, a deposition process, such as a low-pressure chemical vapor deposition process, is used to form a conductive material on the top surface 110a of the multilayer stack structure 110, so that The conductive material is self-aligned to fill each O-shaped opening 103 and electrically contact a portion of the channel layer 124 exposed to the outside. After that, using the patterned hard mask layer 150 as a stop layer, a planarization process (for example, a chemical mechanical polishing process) is performed to remove the conductive material on the top surface 110a of the multilayer stack structure 110. Wherein, the conductive material constituting the contact pad 106 may be a metal material (for example, gold, copper, aluminum, tungsten or the above alloy), a semiconductor material (for example, doped or undoped polycrystalline or single crystal silicon/ Germanium) or other suitable materials. In this embodiment, the landing contact pad 106 can also be adjusted. An ion implantation process is performed to drive n-type dopants (indicated by N+), such as phosphorus (P) or arsenic (As), into the landing contact pad 106.

A dielectric protection layer 125, a gate material layer 126 and a dielectric cover layer 127 are sequentially formed on the multilayer stack structure 110, covering the landing contact pad 106 and the patterned hard mask layer 150. Please refer to FIGS. 6A and 6B. FIG. 6A shows a top view of the structure after the dielectric protection layer 125, the gate material layer 126 and the dielectric cover layer 127 are formed on the structure shown in FIG. 5A; FIG. 6B is a cross-sectional view of the structure along the line S6 of FIG. 6A. In some embodiments of this specification, the material constituting the dielectric protection layer 125 may be silicon oxide; the gate material layer 126 may include polysilicon; the material constituting the dielectric cover layer 127 may be the same as the material constituting the dielectric protection layer 125 the same.

Afterwards, using the dielectric protection layer 125 as an etching stop layer, an etching process is performed to remove a part of the dielectric covering layer 127 and a part of the gate material layer 126 to form a plurality of through holes, such as through holes 128A and 128B respectively partially overlap the corresponding O-shaped opening 103. Please refer to Figures 7A and 7B. Figure 7A shows a top view of the structure after forming through holes 128A and 128B on the structure shown in Figure 6A; Figure 7B is along the tangent line S7 of Figure 7A The structural cross-sectional view shown. In some embodiments of this specification, each O-shaped opening 103 corresponds to two through holes 128A and 128B, respectively. For example, in this embodiment, the through holes 128A and 128B overlap with the two ends of the major axis of the oval cross-sectional profile of the O-shaped opening 103, respectively.

Next, a gate dielectric layer 129 is formed on the sidewall of each through hole 128A and 128B. Please refer to Figure 8A and Figure 8B, Figure 8A is shown in Figure 8A The top view of the structure after the gate dielectric layer 129 is formed on the structure shown in FIG. 7A; FIG. 8B is a cross-sectional view of the structure drawn along the line S8 of FIG. 8A. In some embodiments of this specification, the gate dielectric layer 129 is oxidized by a thermal oxidation process to oxidize a portion of the gate material layer 126 exposed to the outside through the through holes 128A and 128B to form a gate dielectric with a ring profile. Layer 129.

An etch-back process is performed again, and a part of the dielectric protection layer 125 is removed through the through holes 128A and 128B to expose a part of the falling contact pad 106. Please refer to Figures 9A and 9B. Figure 9A shows a top view of the structure after removing a part of the dielectric protection layer 125 in the structure of Figure 8A; Figure 9B is along the tangent line of Figure 9A The cross-sectional view of the structure shown in S9. In some embodiments of this specification, in order to protect the gate dielectric layer 129, before performing the etch-back process, a conductive film 131, such as a polysilicon film, may be formed on the sidewalls of the through holes 128A and 128B to cover the gate dielectric layer. 129, and expose a part of the dielectric protection layer 125 to be removed by the subsequent etch-back process through the through holes 128A and 128B.

Subsequent to a channel material, such as semiconductor material (such as polysilicon), metal silicide (such as titanium silicide, cobalt silicide or silicon germanium), oxide semiconductor (such as indium zinc oxide or indium gallium zinc oxide) or two or more of the above The combination of materials fills the through holes 128A and 128B to form a plurality of channel plugs 132. Please refer to Figures 10A and 10B, Figure 10A is a top view of the structure after forming a plurality of channel plugs 132 in the structure of Figure 9A; Figure 10B is drawn along the tangent line S10 of Figure 10A The structure section shown. In some embodiments of this specification, the formation After a plurality of channel plugs 132, n-type dopants (indicated by N+), such as phosphorus or arsenic, can be driven into the top of the channel plugs 132 by an ion implantation process.

Each channel plug 132 and the corresponding landing contact pad 106, the dielectric protection layer 125, the gate material layer 126, the gate dielectric layer 129 and the channel plug 132 can form a metal-oxide-semiconductor transistor (Metal -Oxide-Semiconductor Transistor, MOS Transistor) switching element, such as a metal-oxide-semiconductor transistor switching element 147A (metal-oxide-semiconductor transistor switching element 147B) formed in the through hole 128A (or through hole 128B) . Among them, the portion where the channel plug 132 overlaps the dielectric cover layer 127 and the contact pad 106 can be used as the metal-oxide-semiconductor transistor switching element 147A (metal-oxide-semiconductor transistor switching element 147B), respectively Source/drain; the overlapped portion of the channel plug 132, the gate dielectric layer 129 and the dielectric protection layer 125 can be used as a metal-oxide-semiconductor transistor switching element 147A (metal-oxide-semiconductor transistor switching element 147B) the channel region; the gate material layer 126 surrounding the channel plug 132 can be used as the gate of the metal-oxide-semiconductor transistor switching element 147A (metal-oxide-semiconductor transistor switching element 147B).

Then, a plurality of grooves 108 (grooves) are formed in the multilayer stack structure 110 by an etching process, so that each groove 108 corresponds to an O-shaped opening 103. Please refer to Figures 11A and 11B, Figure 11A shows a perspective view of the structure after forming a plurality of grooves 108 on the structure shown in Figure 10A; Figure 11B is taken along the line S11 of Figure 11A The structural cross-sectional view shown.

In some embodiments of the present specification, each trench 108 extends downward along the Z-axis direction from the dielectric cover layer 127 on the one hand, and passes through a portion of the dielectric cover layer 127 and a portion that overlap the corresponding O-shaped opening 103. The gate material layer 126 and a part of the dielectric protection layer 125 pass through the landing contact pad 106 and the dielectric pillar 105 in the corresponding O-shaped opening 103. On the other hand, it extends along the X-axis direction (vertical stacking direction) beyond the sidewalls 103b on both sides of the corresponding O-shaped opening 103, and passes through a portion of the memory layer 114 and a portion of the sidewalls 103b on the opposite sidewalls 103b of the O-shaped opening 103. The channel layer 124 extends into the multilayer stack structure 110 and a portion of the gate material layer 126 and the dielectric protection layer 125 that are not overlapped with the O-shaped opening 103.

In this embodiment, the depth of each trench 108 extending along the Z direction does not exceed the bottom 105b of the dielectric column 105, and a portion of the memory layer 114 and a portion located at the bottom 103a of the O-shaped opening 103 The channel layer 124 is disconnected. The portion of each trench 108 that extends laterally along the X-axis extends beyond the sidewall 103b of the O-shaped opening 103, and passes through opposite sides of the memory layer 114 and the channel layer 124, and will be located on a sidewall 103b of the O-shaped opening 103 A part of the memory layer 114 and a part of the channel layer 124 are disconnected; at the same time, a part of the gate material layer 126 overlapping with the O-shaped opening 103 and the landing contact pad 106 in the O-shaped opening 103 are disconnected, and they are respectively separated Divided into two parts. Thus, the metal-oxide-semiconductor transistor switching elements 147A and 147B that are originally electrically connected are electrically isolated from each other by the corresponding trench 108.

Since a part of the memory layer 114 and a part of the channel layer 124 on the side wall 103b of each O-shaped opening 103 are attached to the side wall 103b of the O-shaped opening 103, the memory layer 114 and a part of the channel layer 124 Have parallel multi-layer stacked junctions An O-shaped cross-sectional profile of the top surface 110a of the structure 110. When the corresponding groove 108 extends beyond the O-shaped opening 103, the groove 108 will break the O-shaped profile of the channel layer 124 of the memory layer 114, forming a U-shaped cross section of the top surface 110a of the two parallel multilayer stack structures 110 Outline U1 (as shown in Figure 11A). Moreover, the trench 108 does not cut off a part of the channel layer 124 at the bottom 103a of the O-shaped opening 103. Therefore, the channel layer 124 may have a U-shaped cross-sectional profile U2 (as shown in FIG. 11B) perpendicular to the X-axis direction (vertical stacking direction).

In some embodiments of this specification, each trench 108 can cut the gate-surrounded memory cell string 144 in the O-shaped opening 103 into two sub-memory cell strings connected by the channel layer 124. Among them, each memory cell 140 (a channel layer with an O-shaped cross-sectional profile) in the gate-surrounded memory cell string 144 is cut into two memory cells 145 with a U-shaped cross-sectional profile of the channel layer; The tunneling transistor switch 141 in the column 144 is cut into two tunneling transistor switches 141a and 141b. A plurality of memory cells 145 and a tunneling transistor switch (for example, a tunneling transistor switch 141a) located on the same side are connected in series by a part of the channel layer 124 located on the same side wall 103b of the O-shaped opening 103 to form a channel A series of sub-memory cells; and through a part of the channel layer 124 located at the bottom 103a of the O-shaped opening 103, the two sub-memory cell series are connected into a series of U-shaped memory cells 146. The number of memory cells 145 in each U-shaped memory cell string 146 is twice the number of memory cells 140 in the gate-surrounded memory cell string 144. In this embodiment, the tunneling transistor switches 141a and 141b can be used as inversion assist gates (IG) of the U-shaped memory cell series 146.

Subsequently, the trench 108 is filled with an insulating material 109. After a series of subsequent processes, a plurality of interconnection structures are formed, and each metal-oxide-semiconductor transistor switching element 147A and 147B is respectively connected to the corresponding bit line and the corresponding common source line to form such The three-dimensional memory device 100 is shown in FIGS. 12A and 12B. For example, in this embodiment, the metal-oxide-semiconductor transistor switching element 147A located at one end of each U-shaped memory cell string 146 is connected to the bit line BL through the interconnect structure 112A; The metal-oxide-semiconductor transistor switching element 147B at one end of the cell string 146 is connected to the common source line CS via the interconnect structure 112A. Among them, the metal-oxide-semiconductor transistor switching element 147A can be used as the serial selection switch of the U-shaped memory cell series 146; the metal-oxide-semiconductor transistor switching element 147B can be used as the grounding of the U-shaped memory cell series 146 switch.

Since the U-shaped memory cell series 146 of the three-dimensional memory device 100 uses the metal-oxide-semiconductor transistor switching elements 147A and 147B as the series selection switch/ground selection switch, there is no need to use a pair of Band tunneling generates gate and drain leakage current to erase the memory cell string. It can avoid the use of charge trapping thin film transistors as the tandem selector switch/grounding selector switch, because holes are injected into the gate oxide layer, causing charge accumulation, causing the tandem selector switch/grounding selector switch to fail to open normally during write operations. The problem of failure.

However, the metal-oxide-semiconductor transistor switch element used as the three-dimensional memory element of the series selection switch/ground selection switch is not limited to this. For example, please refer to Figure 13, which is another implementation according to this specification The example shows a cross-sectional view of a three-dimensional memory device 200 structure. The three-dimensional memory device 200 has a similar structure to the three-dimensional memory device 100 depicted in FIG. 12B, except that the three-dimensional memory device 200 does not have a buried oxide layer 102, and the three-dimensional memory device 200 has a multilayer stacked structure 110 underneath it. It includes a source conductor layer 201 and a plurality of via plugs 202. Wherein, the source conductor layer 201 may be a doped region located in the substrate 101 and in contact with the channel layer 124; the via plug 202 penetrates through the multilayer stack structure 110 to connect the source conductor layer 201 to the common source Polar CS.

In this embodiment, the multiple memory cells 145 and the tunneling transistor switch 241a (or the tunneling transistor switch 241b) located on the same side can be connected in series by a part of the channel layer 242 located on the same side to form one Independent memory cell series 246A (or memory cell series 246B). Among them, the metal-oxide-semiconductor transistor switching elements 147A and 147B can be used as series selection switches of the memory cell series 246A and 246B, respectively, and are respectively connected to the corresponding bit line BL via interconnection structures 212A and 212B. The tunneling transistor switches 241a and 241b can be used as the ground selection switches of the memory cell series 246A and 246B, respectively, and are respectively connected to a common source via the source conductor layer 201 and the corresponding via plug 202 and interconnection structure 212C. Polar CS.

Please refer to FIG. 14, which is a cross-sectional view of a three-dimensional memory device 300 according to another embodiment of the present specification. The structure of the three-dimensional memory device 300 is similar to that of the three-dimensional memory device 200 shown in FIG. 13, except that the three-dimensional memory device 300 does not use the groove 108 to surround each of the gate-surrounded memory cell series 144 The memory cell 140 is cut into two memory cells with a U-shaped channel outline. Memory cell; and the tunneling transistor switch 141 in the memory cell series 144 is cut into two tunneling transistor switches. Each gate-surrounded memory cell series 144 of the three-dimensional memory element 300 includes a single metal-oxide-semiconductor transistor switch element 347 used as a series selection switch, which is formed in and respectively via an interconnect structure 312A is connected to the corresponding bit line BL. The tunnel transistor switch 141 of the three-dimensional memory device 300 is used as the ground selection switch of the memory cell series 144 and is connected via the source conductor layer 201 and the corresponding via plug 202 and the interconnect structure 312B To the common source line CS.

According to the above-mentioned embodiments, this specification discloses a three-dimensional memory device and a manufacturing method thereof. It uses a switch element without a gate dielectric layer of a dielectric charge trapping structure as a series selection switch/ground selection switch for the series of memory cells in the three-dimensional memory element. Therefore, there is no need to erase the memory cell string in a manner in which the band-to-band tunneling generates a gate and causes a drain leakage current. It can avoid the use of charge trapping thin film transistors as the tandem selector switch/grounding selector switch, because holes are injected into the gate oxide layer, causing charge accumulation, causing the tandem selector switch/grounding selector switch to fail to open normally during write operations. The problem of failure.

In some embodiments of this specification, this structure can be applied to three-dimensional memory devices with gate-surrounded memory cell strings, three-dimensional memory devices including single-gate vertical channel memory cell strings, and U-shaped vertical channels. A three-dimensional memory device with a series of memory cells of a structure, a three-dimensional memory device with a series of memory cells having a cylindrical channel structure, or a three-dimensional memory device with a series of memory cells having a semi-cylindrical channel structure.

Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100: Three-dimensional memory device

101: Substrate

102: buried oxide layer

102a: The bottom of the buried oxide layer

103: O-shaped opening

103b: Side wall of O-shaped opening

103a: The bottom of the O-shaped opening

105: Dielectric cylinder

105a: The top surface of the dielectric cylinder

105b: The bottom of the dielectric column

109: insulating material

110: Multi-layer stacked structure

110a: The top surface of the multilayer stack structure

112A: internal connection

112B: Internal connection structure

114: memory layer

120: conductive layer

122: bottom gate layer

122a: the bottom of the bottom gate layer

124: Channel layer

125: Dielectric protective layer

126: gate material layer

127: Dielectric cover layer

129: Gate Dielectric Layer

130: insulating layer

132: channel plug

131: conductive film

145: Memory Cell

141a, 141b: tunneling transistor switch

147A, 147B: metal-oxide-semiconductor transistor switching element

150: Patterned hard mask layer

CS: Common source line

Claims (10)

A three-dimensional memory device includes: a multi-layer stack structure including a plurality of conductive layers, a plurality of insulating layers and at least one opening, the plurality of insulating layers and the plurality of conductive layers are stacked alternately along a stacking direction, the at least one The opening passes through the plurality of conductive layers; a memory layer is located in the at least one opening and at least partially overlaps the plurality of conductive layers; a channel layer is located in the at least one opening and at least partially overlaps the memory layer And a switching element, including: a channel plug located above the multilayer stack structure and electrically connected to the channel layer; a gate dielectric layer surrounding the channel plug; and a gate electrode surrounding the gate Polar dielectric layer. According to the three-dimensional memory device described in claim 1, wherein the channel layer has a U-shaped cross-sectional profile, and the U-shaped cross-sectional profile is perpendicular to the stacking direction. The three-dimensional memory device described in item 1 of the scope of the patent application further includes: a drop contact pad located in the at least one opening, respectively in contact with the channel plug and the channel layer, and electrically connected to the gate Sexual isolation. The three-dimensional memory device described in claim 1 further includes: a source conductor layer located under the multilayer stack structure and in contact with the channel layer; and a via plug passing through the multilayer stack structure , And in contact with the source conductor layer. In the three-dimensional memory device described in claim 1, wherein the gate dielectric layer does not have a dielectric charge trapping structure. A method for manufacturing a three-dimensional memory device includes: providing a multi-layer stack structure, the multi-layer stack structure includes a plurality of conductive layers, a plurality of insulating layers and at least one opening, the plurality of insulating layers and the plurality of conductive layers Stacked alternately in a stacking direction, the at least one opening passes through the plurality of conductive layers; a memory layer is formed in the at least one opening so that the memory layer and the plurality of conductive layers at least partially overlap; in the at least one opening Forming a channel layer so that the channel layer and the memory layer at least partially overlap; and forming a switching element above the multilayer stack structure so that the switching element includes: a channel plug in contact with the channel layer; A gate dielectric layer surrounds the channel plug, and the gate dielectric layer does not have a dielectric charge trapping structure; and a gate electrode surrounds the gate dielectric layer. According to the method of manufacturing a three-dimensional memory device described in claim 6, wherein the step of forming the switching device includes: filling the at least one opening with a dielectric material to form a dielectric column; forming a drop A contact pad is located above the dielectric column and is in contact with the channel layer; a dielectric protection layer is formed to cover the landing contact pad and the multilayer stack structure; and a gate material layer is formed to cover the dielectric Protective layer; forming a through hole through the gate material layer; forming a gate dielectric layer on a sidewall of the through hole; removing a part of the dielectric protection layer through the through hole to expose a part The falling contact pad; and filling the through hole with a channel material to form the channel plug. The method for manufacturing a three-dimensional memory device as described in claim 7, wherein before removing a part of the dielectric protection layer, it further includes forming a conductive film on the sidewall of the through hole to cover the gate Dielectric layer. The method for fabricating a three-dimensional memory device as described in claim 7 further comprises: forming a groove extending along a direction perpendicular to the stacking direction and exceeding the at least one opening to pass through the memory layer And the channel layer extend into a part of the multilayer stack structure; and pass through a part of the gate material layer, a part of the dielectric protection layer, and the at least one opening aligned with the at least one opening along the stacking direction A contact pad and a part of the dielectric columnar body are dropped so that the channel layer has a U-shaped cross-sectional profile perpendicular to the stacking direction; and the trench is filled with an insulating material. The method for fabricating a three-dimensional memory device as described in item 9 of the scope of patent application further includes forming a via plug, passing through the multilayer stack structure, and contacting the channel layer.

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