TWI696264B - Memory device and method for fabricating the same - Google Patents

Abstract

A 3D memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a doped semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.

Description

Memory element and its manufacturing method

This disclosure is about a memory element and its manufacturing method. In particular, it relates to a three-dimensional memory device including multiple planes of memory cells.

As the critical dimensions of integrated circuit components shrink to the limit of common memory cell technologies, engineering designers are continuously looking for techniques to stack multiple memory cell hierarchies to achieve greater storage capacity and more Less cost per bit. Charge-trapping memory technology using silicon-oxide-nitride-oxide-silicon (SONOS) structure has been applied to construct memory devices with vertical channel structures, such as Three-dimensional NAND flash memory. The vertical channel structure includes an ONO charge trapping layer passing through the conductive strip stack structure, and a channel layer covering the ONO charge trapping layer. The memory cells (memory cells) are located on the intersection of each conductive strip and the vertical channel structure, and are connected in series by the channel layer to form a series of memory cells.

In a typical vertical channel structure, the channel layer is generally composed of deposited semiconductor materials, such as epitaxial polysilicon; it is easy to generate grain boundaries (Grain Boundaries, GBs). Due to the influence of the grain boundary in the channel layer, the threshold voltages of the series selection switch, the ground selection switch and each memory cell in the memory cell series may vary. In particular, when the grain boundary is generated in the non-gate-control region of the channel layer between the ground selection switch and the memory cell string, it will greatly reduce the channel current and improve the memory cell The critical voltage seriously affects the stability of memory cell operations (such as write and erase verification operations).

Therefore, there is a need to provide an advanced memory device and its manufacturing method to solve the problems faced by the conventional technology.

An embodiment of the present specification discloses a memory device. The memory device includes: a conductive strip stack structure, a memory layer, a channel layer, and a doped semiconductor pad. The conductive strip stack structure includes multiple conductive strips and multiple insulating layers stacked alternately with the conductive strips. The conductive strip stack structure further has at least one channel opening passing through the conductive strips and the insulating layer, exposing a part of the conductive strips and the insulating layer to the outside. The memory layer is located in the channel opening and covers the portion of the conductive strip exposed to the outside through the channel opening. The channel layer is located in the channel opening and covers the memory layer. The doped semiconductor pad extends upward from the bottom of the channel opening beyond the upper surface of the bottom conductive strip in the conductive strip, and contacts the channel layer and is electrically isolated from the conductive strip. The channel layer includes a first portion having a first doping concentration, and a second portion above the first portion and having a second doping concentration.

An embodiment of the present specification discloses a method for manufacturing a memory element. The method for manufacturing a memory element includes the following steps: forming a conductive strip stack structure having at least one channel opening, wherein the conductive strip stack structure includes a plurality of conductive A strip and a plurality of insulating layers stacked alternately with the conductive strip. The channel opening passes through these conductive strips and the insulating layer, exposing a part of the conductive strips and the insulating layer. A semiconductor pad is formed, which extends upward from the bottom of the channel opening beyond the upper surface of one of the conductive strips in the conductive strip and is electrically isolated from the conductive strip. The base dopant is implanted in the semiconductor bonding pad. A memory layer is formed in the channel opening and covers the portion of the conductive strip exposed to the outside through the channel opening. A channel layer is formed in the channel opening, covers the memory layer, and contacts the semiconductor pad. And driving a portion of the base dopant into the channel layer so that the channel layer includes a first portion with a first doping concentration and a second portion above the first portion and having a second doping concentration.

According to the above-mentioned embodiments, the embodiments of the present specification provide a memory device and a manufacturing method thereof. It is to form a semiconductor pad at the bottom of the channel opening used to form the vertical memory cell string in the memory device, so that the semiconductor bonding pad contacts the vertical memory cell string channel layer formed later on the side wall of the channel opening. Before the channel layer is formed, the base dopant is implanted into the semiconductor pad using an ion implantation process, and a portion of the base dopant in the semiconductor pad is driven into the vertical channel layer by heat treatment in the subsequent process to reduce the channel The channel resistance in the layer further provides a more stable threshold voltage control of the vertical memory cell string, which solves the problem of the unstable operation of the memory cell string operation caused by the conventional technology in which the grain boundary is generated in the non-gate control area of the channel layer.

This specification provides a memory device and a manufacturing method thereof to solve the problem of the variation of the critical voltage of the memory cell due to the generation of grain boundaries in the vertical channel layer in the conventional technology. In order to make the above-mentioned embodiments of the specification and other objects, features and advantages more obvious and understandable, a plurality of preferred embodiments will be cited below in conjunction with the accompanying drawings for detailed description.

However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, components, methods, and parameters. The proposed preferred embodiments are only used to illustrate the technical features of the present invention, and are not intended to limit the patent application scope of the present invention. Those with ordinary knowledge in this technical field will be able to make equivalent modifications and changes based on the description of the following description without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be denoted by the same element symbols.

FIGS. 1A to 1G are schematic cross-sectional views of a manufacturing process structure of a memory device 10 having a vertical channel structure according to an embodiment of the present specification. The manufacturing method of the memory device 10 includes the following steps: First, at least one conductive strip stack structure 11 is formed on the substrate 101. The formation of the conductive strip stack structure 11 includes providing a plurality of conductive layers 103 stacked on top of each other and separated by a plurality of insulating layers 102 (as shown in FIG. 1A). In some embodiments of the present specification, the material constituting the conductive layer 103 may be a doped or undoped semiconductor, for example, including silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC)) , Metals (may include tungsten (W) and platinum (Pt)) and conductive compounds (may include titanium nitride (TiN), tantalum nitride (TaN)) and other materials. The material constituting the insulating layer 102 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or other suitable dielectric materials.

After that, a patterning process, such as an etching process, is used to form a plurality of channel openings 104, pass through the insulating layer 102 and the conductive layer 103, and part of the substrate 101 is outside. A plurality of conductive strip stack structures 11 (as shown in FIG. 1B) are formed on the substrate 101 by the insulating layer 102 and the conductive layer 103. In some embodiments of the present specification, the channel opening 104 may be a trench or a through hole. In this embodiment, the channel opening 104 may be a trench that passes through the conductive layer 103 and the insulating layer 102 to expose part of the side walls of the conductive strip layer 103 and the insulating layer 102, and exposes the insulating layer 102 and the conductive layer 103 is divided into at least two conductive strip stack structures 11.

Each conductive strip stack structure 11 includes a plurality of conductive strips 103A, 103B, 103C, 103D, and 103E stacked alternately with the insulating layer 102. The conductive strip stacking structure 11 is located in the middle level of the plurality of conductive strips 103B, 103C, and 103D, which can be used as word lines (WLs) of the memory element 10; at least one conductive strip in the lower level 103A, can be used as a reference (eg, ground) selection line (GSLs) of the memory device 10; at least one conductive strip 103E in the upper hierarchy can be used as a serial selection line (SSLs) of the memory device 10 .

Next, a memory layer 105 is formed in the channel opening 104, so that the memory layer 105 covers the insulating layer 102 and the conductive strips 103A, 103B, 103C, 103D, and 103E through the channel opening 104 and exposed to the outer side wall and the channel opening The bottom 104a of 104 is in contact (as shown in FIG. 1C). The memory layer 105 may include a multilayer dielectric charge trapping structure. For example, in some embodiments of the present specification, the memory layer 105 may include a multi-layer data storage structure known in flash memory technology, such as silicon oxide-silicon nitride-silicon known in flash memory technology. Oxide-nitride-oxide (ONO) structure, silicon oxide-silicon nitride-silicon oxide-silicon nitride-silicon oxide (oxide-nitride-oxide-nitride-oxide, ONONO) structure, one silicon- Silicon oxide-silicon nitride-silicon oxide-silicon (silicon-oxide-nitride-oxide-silicon, SONOS) structure, energy gap engineering silicon-silicon oxide-silicon nitride-silicon oxide-silicon (bandgap engineered silicon -oxide-nitride-oxide-silicon (BE-SONOS) structure, tantalum nitride-alumina-silicon nitride-silicon oxide-silicon (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon, TANOS) structure and Metal high-k dielectric bandgap engineering silicon-silicon oxide-silicon nitride-silicon oxide-silicon (metal-high-k bandgap-engineered silicon-oxide-nitride-oxide-silicon, MA BE-SONOS).

After that, a part of the memory layer 105 is removed to expose the bottom 104a of the channel opening 104, and a semiconductor pad 106 is formed. The bottom 104a of the channel opening 104 extends upward beyond the upper surface 103A1 of the bottom conductive strip 103A In order to electrically isolate the semiconductor pad 106 from the conductive strips 103A, 103B, 103C, 103D, 103E, and 103F through the remaining memory layer 105 (as shown in FIG. 1D). In some embodiments of the present specification, the semiconductor pad 106 may be a semiconductor structure formed at the bottom 104a of the channel opening 104 by a deposition process, for example, a self-aligned selective epitaxial growth technique. The material constituting the semiconductor pad 106 may be silicon, germanium, silicon germanium, gallium arsenide, silicon carbide, or other suitable semiconductor materials. In this embodiment, the semiconductor pad 106 may be a polysilicon epitaxial structure. The top 106a of the semiconductor pad 106 is located between the upper surface 103A1 of the bottom conductive strip 103A and the lower surface 103B1 of the second highest conductive strip 103B in the bottom hierarchy. There is no other conductive strip between the upper surface 103A1 of the bottom conductive strip 103A and the lower surface 103B1 of the conductive strip 103B. However, in another embodiment of the present specification, the top 106a of the semiconductor pad 106 may extend upward beyond other conductive strips (not shown).

Then, an ion implantation process is performed on the semiconductor pad 106 to implant a plurality of base dopants 107 with a predetermined doping concentration into the semiconductor pad 106 (as shown in FIG. 1E). In some embodiments of the present specification, the base dopant 107 may be a p-type dopant, such as boron (B), or may be an n-type dopant, such as phosphorus (P) or arsenic (As). In this embodiment, the base dopant 107 may be an n-type dopant.

Next, a channel layer 108 is formed in the channel opening 104 to cover the memory layer 105 and the top 106 a of the semiconductor pad 106 so that the channel layer 108 is in contact with the semiconductor pad 106. A plurality of charge trapping thin film transistor switches are formed at the intersections where the conductive stripes 103A, 103B, 103C, 103D, and 103E overlap the memory layer 105, the channel layer 108, and the semiconductor pad 106, respectively , And through the channel layer 108 connected in series to form a memory cell string 109 (as shown in FIG. 1F).

For example, in this embodiment, the charge trapping thin film transistor switch 109A is formed at the intersection of the conductive strip 103A and the memory layer 105 and the semiconductor pad 106, and is electrically connected to the substrate 101 via the semiconductor pad 106 , Can be used as a ground selection switch of the memory cell string 109; a plurality of charge trapping thin film transistor switches 109B formed on the intersections of the conductive stripes 103B, 103C, and 103D overlapping the memory layer 105 and the channel layer 108, 109C and 109D can be used as a plurality of memory cells in the memory cell string 109; a plurality of charge trapping thin film transistor switches 109E formed on the intersection of the conductive strip 103E and the memory layer 105 and the channel layer 108 can be used as The series selection switch of the memory cell series 109.

The material constituting the channel layer 108 may be the same as or different from the material constituting the semiconductor pad 106. In some embodiments of the present specification, the material constituting the channel layer 108 may include semiconductor materials, such as silicon, germanium, silicon germanium, gallium arsenide (GaAs), silicon carbide, or other suitable semiconductor materials. In this embodiment, the channel layer 108 includes polysilicon.

After that, the channel opening 104 is filled with the dielectric material 110, and after the dielectric material 110 is planarized, a part of the dielectric material 110 is etched back to form a plurality of recesses aligned with the channel opening 104 (not (Shown), and filled with a conductive material to form a contact pad 111 connecting the bit line (not shown) and the channel layer 108. Subsequently, a series of subsequent processes (not shown) are performed to form the memory device 10 as shown in FIG. 1G.

In some embodiments of the present specification, since the subsequent process includes a plurality of thermal processes, a portion of the base dopant 107B can be driven into the channel layer 108 from the doped semiconductor pad 106 to diffuse into the channel layer 108 The dopant concentration of a portion of the base dopant 107B is substantially smaller than the dopant concentration of the remaining portion of the base dopant 107A remaining in the semiconductor pad 106. Among them, a portion of the base dopant 107B diffused into the channel layer 108 can be divided into a first portion 107B1 having a first dopant concentration above the top 106a of the semiconductor pad 106, and having a first dopant concentration above, and having The second portion 107B2 of the second dopant concentration; the first dopant concentration is greater than the second dopant concentration; and the first dopant concentration has a top 106a from the semiconductor pad 106, along the direction away from the bottom 104a of the channel opening 104, upward A gradually decreasing concentration gradient; the second doping concentration has a concentration gradient that gradually decreases upward from the first portion 107B1 along the direction away from the bottom 104a of the channel opening 104.

In this embodiment, there is no obvious boundary between the first portion 107B1 and the second portion 107B2 of the base dopant 107B diffused into the channel layer 108. In other words, the dopant concentration of a portion of the base dopant 107B that diffuses into the channel layer 108 has a concentration gradient that decreases upward from the top 106a of the semiconductor pad 106 along the direction away from the bottom 104a of the channel opening 104. Wherein, the extension height of a portion of the base dopant 107B in the channel layer 108 (that is, the height of the second portion 107B2) does not extend upward beyond the lower surface 103B1 of the conductive strip 103B.

By driving a part of the base dopant 107B into the channel layer 108, the grain boundary barrier and channel resistance in the channel layer 108 can be reduced, and the memory cell string can be provided under the same operating voltage The higher channel current of 109 makes the charge trapping thin film transistor switches 109A, 109B, 109C, 109D, and 109E in the memory cell string 109 have a more stable threshold voltage, which solves the conventional technology because the grain boundaries are generated vertically The non-gate control region of the channel layer 108 causes the operation of the memory cell string 109 to be unstable.

FIGS. 2A to 2G are schematic cross-sectional views of the manufacturing process structure of the memory device 20 having a vertical channel structure according to another embodiment of the present specification. The manufacturing method of the memory element 20 includes the following steps: First, at least one sacrificial strip stack structure 21 is formed on the substrate 201. The formation of the sacrificial strip stack structure 21 includes providing a plurality of sacrificial layers 213 stacked on each other and separated by a plurality of insulating layers 202 (as shown in FIG. 2A). In some embodiments of the present specification, the material constituting the sacrificial layer 213 may be a dielectric material different from the insulating layer 202. For example, in this embodiment, the material constituting the insulating layer 202 may be silicon dioxide; the material constituting the sacrificial layer 213 may be silicon nitride.

After that, a patterning process, such as an etching process, is used to form a plurality of channel openings 204, pass through the insulating layer 202 and the sacrificial layer 213, and expose a portion of the substrate 201 outside. Thereby, a plurality of sacrificial strip stack structures 21 (as shown in FIG. 2B) are formed on the substrate 201. In some embodiments of the present specification, the channel opening 204 may be a trench or a through hole. In this embodiment, the channel opening 204 may be a through hole, passing through the conductive layer 213 and the sacrificial layer 213, exposing a part of the sidewalls of the sacrificial layer 213 and the insulating layer 202, and exposing the sacrificial layer 213 and the insulating layer 202 At least two sacrificial strip stack structures 21 are divided. Each of the sacrificial strip stacking structures 21 includes a plurality of sacrificial strips 213A, 213B, 213C, 213D, and 213E that are alternately stacked with the insulating layer 202 and isolated from each other.

Next, a semiconductor pad 206 is formed, extending upward from the bottom 204a of the channel opening 204 beyond the upper surface 213A1 of the bottommost sacrificial strip 213A (as shown in FIG. 2C). In some embodiments of the present specification, the semiconductor pad 206 may be formed on the bottom 204a of the channel opening 204 by a deposition process, for example, a self-aligned selective epitaxial growth technique. The material constituting the semiconductor pad 206 may be silicon, polysilicon, germanium, silicon germanium, gallium arsenide, silicon carbide, or other suitable semiconductor materials. In this embodiment, the semiconductor pad 206 may be a polysilicon structure. The top 206a of the semiconductor pad 206 is located between the upper surface 213A1 of the underlying sacrificial strip 213A and the lower surface 213B1 of the sacrificial strip 213B of the next highest height.

Then, an ion implantation process is performed on the semiconductor pad 206, so as to implant a plurality of base dopants 207 with a predetermined doping concentration into the semiconductor pad 206 (as shown in FIG. 2C). In some embodiments of the present specification, the base dopant 207 may be a p-type dopant, such as boron, or may be an n-type dopant, such as phosphorus or arsenic. In this embodiment, the base dopant 207 may be an n-type dopant, and the predetermined doping concentration has a concentration gradient that decreases from the top 206a of the semiconductor pad 206 toward the bottom 204a of the channel opening 204.

Next, a memory layer 205 is formed in each channel opening 204, so that the memory layer 205 covers the insulating layer 202 and the sacrificial strips 213B, 213C, 213D, and 213E through the channel opening 204 and exposed to the outer side wall. After that, a portion of the memory layer 205 is removed to expose the top 206a of the semiconductor pad 206, and a channel layer 208 is formed in each channel opening 204 to cover the memory layer 205 and the top 206a of the semiconductor pad 206 To make the channel layer 208 contact with the semiconductor pad 206 (as shown in FIG. 2D).

In some embodiments of the present specification, the memory layer 205 may include a silicon oxide-silicon nitride-silicon oxide structure, a silicon oxide-silicon nitride-silicon oxide-nitride known in flash memory technology Silicon-silicon oxide structure, a silicon-silicon oxide-silicon nitride-silicon oxide-silicon structure, energy gap engineering silicon-silicon oxide-silicon nitride-silicon oxide-silicon structure, tantalum nitride-oxidation Aluminum-silicon nitride-silicon oxide-silicon structure and metal high dielectric constant energy gap engineering silicon-silicon oxide-silicon nitride-silicon oxide-silicon. The channel layer 208 may include semiconductor materials such as silicon, polysilicon, germanium, silicon germanium, gallium arsenide, silicon carbide, and graphene, or other conductive materials such as metal silicides and metals. In this embodiment, the memory layer 205 may include a silicon oxide-silicon nitride-silicon oxide structure known in flash memory technology; the channel layer 208 may be a polysilicon film.

The dielectric material 210 is then used to fill the channel opening 204, and after the dielectric material 210 is planarized, a portion of the dielectric material 210 is etched back to form a plurality of recesses (not shown) aligned with the channel opening 204 Shown), and filled with a conductive material to form a contact pad 211 (as shown in FIG. 2E) connecting the bit line (not shown) and the channel layer 208.

Then, the sacrificial strips 213A, 213B, 213C, 213D, and 213E in the sacrificial strip stacking structure 21 are selectively removed, thereby forming a gap 212 between the insulating layers 202, and part of the side walls of the memory layer 205 and the semiconductor pad 206 206b is exposed. A dielectric liner 214 is formed in the gap 212 to cover at least the side wall 206b (as shown in FIG. 2F) of the semiconductor pad 206 exposed to the outside through the gap 212.

In some embodiments of the present specification, a trench 215 penetrating the sacrificial strips 213A, 213B, 213C, 213D, and 213E and the insulating layer 202 may be formed in the sacrificial strip stack structure 21, and then through a selective etching process, through the trench Groove 215 to remove these sacrificial strips 213A, 213B, 213C, 213D, and 213E. For example, in the present embodiment, an etching chemistry having a relatively easy etching of silicon nitride, such as phosphoric acid (H ₃ PO ₄ ), is selected to remove the sacrificial strips 213A, 213B, 213C, 213D, and 213E. In some embodiments of the present specification, the dielectric liner 214 is formed by performing a thermal oxidation process on the sidewall 206b of the semiconductor pad 206.

Then, a conductive material is used to fill the void 212, thereby forming a plurality of conductive strips 203A, 203B, 203C, and 203D between the insulating layers 202, and converting the original sacrificial strip stack structure 21 into a plurality of conductive strip stacks Structure 22 (as shown in Figure 2G). Among them, a plurality of conductive stripes 203B, 203C, and 203D located in a hierarchy between each conductive strip stack structure 22 can be used as a character line of the memory element 20; at least one conductive strip 203A located in the lower hierarchy , Can be used as a reference (eg, ground) selection line of the memory element 20; at least one conductive strip 203E in the upper hierarchy can be used as a serial selection line of the memory element 20. Furthermore, a plurality of charge trapping thin film transistor switches are formed at intersections where the conductive stripes 203A, 203B, 203C, 203D, and 203E overlap the memory layer 205, the channel layer 208, the dielectric liner 214, and the semiconductor pad 206, The channel layer 208 is connected in series to form a series of memory cells 209.

For example, in this embodiment, the thin film transistor switch 209A is formed at the intersection of the conductive strip 203A, the dielectric liner 214, and the semiconductor pad 206, and is electrically connected to the substrate 201 via the semiconductor pad 206, and can be used to As a ground selection switch for the memory cell string 209; a plurality of thin film transistor switches 209B, 209C, and 209D formed on the intersections of the conductive strips 203B, 203C, and 203D overlapping the memory layer 205 and the channel layer 208 can be used as A plurality of memory cells of the memory cell string 209; a plurality of thin film transistor switches 209E formed on the intersection of the conductive strip 203E and the memory layer 205 and the channel layer 208 can be used as the string selection of the memory cell string 209 switch.

Subsequently, a spacer 216 and a source line 217 are formed in the trench 215. After that, a series of post-processes (not shown) are performed to form the memory device 20 as shown in FIG. 2G. In some embodiments of the present specification, since the subsequent process includes a plurality of thermal processes, a portion of the substrate dopant 207B can be driven into the channel layer 208 from the semiconductor pad 206 to diffuse into a portion of the substrate in the channel layer 208 The dopant concentration of the dopant 207B is substantially smaller than the dopant concentration of the remaining base dopant 207A remaining in the semiconductor pad 206. A part of the base dopant 207B diffused into the channel layer 208 can be divided into at least two parts, for example, a first part 207B1 having a first dopant concentration above the top 206a of the semiconductor bonding pad 206 and above the first part , And has a second portion 207B2 with a second dopant concentration. The first dopant concentration is greater than the second dopant concentration; and the first dopant concentration has a concentration gradient that gradually decreases upward from the top 206a of the semiconductor pad 206 along the direction away from the bottom 204a of the channel opening 204; the second dopant The impurity concentration has a concentration gradient that gradually decreases upward from the first portion 207B1 along the direction away from the bottom 204a of the channel opening 204.

In this embodiment, there is no obvious boundary between the first portion 207B1 and the second portion 207B2 of a portion of the base dopant 207B diffused into the channel layer 208. In other words, the concentration of a portion of the base dopant 207B diffused into the channel layer 208 has a concentration gradient that decreases upward from the top 206a of the semiconductor pad 206 along the direction away from the bottom 204a of the channel opening 204. And the extension height of a portion of the base dopant 207B (that is, the height of the second portion 207B2) diffused into the channel layer 208 does not extend upward beyond the lower surface 203B1 of the conductive strip 203B.

By driving a part of the base dopant 207B into the channel layer 208, the energy barrier and the channel resistance of the grain boundary in the channel layer 208 can be reduced, and under the same operating voltage, a higher channel of the memory cell string 209 can be provided Current, which in turn enables the charge trapping thin film transistor switches 209A, 209B, 209C, 209D, and 209E in the memory cell string 209 to have a more stable threshold voltage, which solves the problem of the conventional technology that the grain boundary is generated in the vertical channel layer 208. The gate control area causes the unstable operation of the memory cell string 109.

According to the above-mentioned embodiments, the embodiments of the present specification provide a memory device and a manufacturing method thereof. It is to form a semiconductor pad at the bottom of the channel opening used to form the vertical memory cell string in the memory device, so that the semiconductor bonding pad contacts the vertical memory cell string channel layer formed later on the side wall of the channel opening. Before the channel layer is formed, the base dopant is implanted into the semiconductor pad using an ion implantation process, and a portion of the base dopant in the semiconductor pad is driven into the vertical channel layer by heat treatment in the subsequent process to reduce the channel The channel resistance in the layer further provides a more stable threshold voltage control of the vertical memory cell string, which solves the problem of the unstable operation of the memory cell string operation caused by the conventional technology in which the grain boundary is generated in the non-gate control area of the channel layer.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in this technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be deemed as defined by the appended patent application scope.

10, 20: memory components 101, 201: substrate 11, 22: conductive strip stack structure 102, 202: insulating layer 103, 203: conductive layer 103A, 103B, 103C, 103D, 103E: conductive strip 103A1: the upper surface of the bottom conductive strip 103B1, 203B1: the lower surface of the next highest conductive strip 104, 204: channel opening 104a, 204a: the bottom of the channel opening 105, 205: memory layer 106, 206: Semiconductor pad 106a, 206a: the top of the semiconductor pad 107, 207: base doping 107A, 207A: the remaining part of the base adulterant 107B, 207B: part of the base dopant diffused into the channel layer 107B1, 207B1: Part One 107B2, 207B2: Part Two 108, 208: channel layer 109, 209: memory cell series 109A, 109B, 109C, 109D, 109E: charge trapping thin film transistor switch 110, 210: dielectric materials 111, 211: contact pad 203A, 203B, 203C, 203D, 203E: conductive strip 213A1: the upper surface of the bottom sacrificial strip 213B1: the lower surface of the next highest sacrificial strip 206b: sidewall of semiconductor pad 209A, 209B, 209C, 209D, 209E: charge trapping thin film transistor switch 212: gap 213: Sacrificial layer 213A, 213B, 213C, 213D, 213E: Sacrificial strip 214: Dielectric lining 215: Groove 216: Wall 217: source line

In order to have a better understanding of the above and other aspects of this specification, the following specific examples are given, together with the attached drawings and the scope of patent application, as detailed below: FIGS. 1A to 1G are schematic cross-sectional views of a manufacturing process structure of a memory device having a vertical channel structure according to an embodiment of this specification; FIGS. 2A to 2G are schematic cross-sectional views of a manufacturing process structure of a memory device having a vertical channel structure according to another embodiment of this specification.

no.

10: Memory components

101: substrate

11: conductive strip stack structure

102: insulating layer

103: conductive layer

103A1: the upper surface of the bottom conductive strip

103A, 103B, 103C, 103D, 103E: conductive strip

103B1: the lower surface of the next highest conductive strip

104: channel opening

104a: bottom of the channel opening

105: memory layer

106: semiconductor pad

106a: top of semiconductor pad

107: basal adulterant

107A: The remaining part of the base adulterant

107B: A portion of the base dopant diffused into the channel layer

107B1: Part One

107B2: Part Two

108: channel layer

109: Memory cell series

109A, 109B, 109C, 109D, 109E: charge trapping thin film transistor switch

110: Dielectric material

111: contact pad

Claims (10)

A memory element includes: A conductive strip stack structure, including a plurality of conductive strips and a plurality of insulating layers, stacked alternately with the plurality of conductive strips; the conductive strip stack structure also has at least one channel opening through the plurality of conductive strips and The plurality of insulating layers; A memory layer located in the at least one channel opening and covering the portion of the plurality of conductive strips exposed to the outside through the at least one channel opening; A channel layer located in the at least one channel opening and covering the memory layer; and A doped semiconductor pad extending upward from a bottom of the at least one channel opening beyond an upper surface of a bottom conductive strip of the plurality of conductive strips and in contact with the channel layer and with the plurality of Conductive strips are electrically isolated; The channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration above the first portion. The memory device as described in item 1 of the patent application range, wherein the second doping concentration is less than the first doping concentration. The memory device according to item 1 of the patent application scope, wherein the first portion is located above a top of the doped semiconductor pad; the first doping concentration is greater than the second doping concentration, and the first A doping concentration has a gradient that gradually decreases upward from a top of the doped semiconductor pad away from the bottom of the at least one channel opening. The memory device of claim 3, wherein the second doping concentration has a gradient that gradually decreases upward from the bottom of the first portion away from the bottom of the at least one channel opening. The memory device as described in item 4 of the patent application range, wherein the top of the doped semiconductor pad is located on the upper surface of the bottom conductive strip and the primary high bottom conductive strip among the plurality of conductive strips Between a lower surface of the belt, and between the upper surface and the lower surface, there is no one of the plurality of conductive strips. The memory device as recited in item 5 of the patent application range, wherein the second portion does not extend beyond the lower surface. The memory device as described in item 1 of the patent application range, wherein the memory layer includes a multilayer dielectric charge trapping structure. A method for manufacturing a memory element includes: Forming a conductive strip stack structure having at least one channel opening, wherein the conductive strip stack structure includes a plurality of conductive strips and a plurality of insulating layers, stacked alternately with the plurality of conductive strips; the at least one channel opening passes through The plurality of conductive strips and the plurality of insulating layers; Forming a semiconductor pad, extending upward from a bottom of the at least one channel opening beyond an upper surface of a bottom conductive strip of the plurality of conductive strips, and electrically isolated from the plurality of conductive strips; Implanting a base dopant in the semiconductor pad; Forming a memory layer in the at least one channel opening, and covering a portion of the plurality of conductive strips exposed to the outside through the at least one channel opening; Forming a channel layer in the at least one channel opening, covering the memory layer, and contacting the semiconductor pad; and Driving a portion of the base dopant into the channel layer, such that the channel layer includes a first portion having a first doping concentration, and a first portion above the first portion and having a second doping concentration Two parts. The method for manufacturing a memory element as described in item 8 of the patent application scope, wherein the step of forming the conductive strip stack structure having the at least one channel opening includes: Forming a plurality of sacrificial material layers staggered with the plurality of insulating layers; Forming the at least one channel opening through the plurality of sacrificial material layers; Forming the semiconductor pad on the bottom of the at least one channel opening; Forming the memory layer in the at least one channel opening and covering the exposed portion of the plurality of sacrificial strips through the at least one channel opening; Forming the channel layer in the at least one channel opening, covering the memory layer, and contacting the semiconductor pad; Selectively removing the plurality of sacrificial layers to form a plurality of gaps between the plurality of insulating layers, exposing a portion of the memory layer and a sidewall of the semiconductor pad to the outside; Forming at least one dielectric liner in the plurality of voids, covering at least the sidewall of the semiconductor pad; and Filling the plurality of voids with a conductive material, thereby forming the plurality of conductive strips between the plurality of insulating layers. The method for manufacturing a memory element as described in item 8 of the patent application scope, wherein after forming the conductive strip stack structure having at least one channel opening, the method further includes: Forming the memory layer in the at least one channel opening, wherein the memory layer is in contact with the bottom of the at least one channel opening; Removing a portion of the memory layer to expose the bottom of the at least one channel opening to the outside; Forming the semiconductor pad; and The channel layer is formed to cover the memory layer and a top of the semiconductor pad.

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