TWI762270B - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device is provided. The memory device includes a substrate, a stacked structure, a channel layer, and a charge storage structure. The stacked structure is located on the substrate and includes a plurality of insulating layers and a plurality of conductive layers stacked alternately, and the stacked structure has holes. The channel layer is located in the hole and includes a first part and a second part. The number of grain boundaries in the second part is lower than the number of grain boundaries in the first part. The charge storage structure is located between the first part and the plurality of conductive layers, and the charge storage structure and the second part sandwich the first part therebetween.

Description

Memory device and method of manufacturing the same

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly, to a memory device and a method for fabricating the same.

The flash memory has the advantage that the stored data will not disappear even after the power is turned off, so it has become a memory element widely used in many electronic devices. Although the three-dimensional NAND flash memory developed with the evolution of the process can improve the integration of memory devices, there are also many related challenges.

The present invention provides a memory device and a manufacturing method thereof, which can improve the quality of the channel layer and reduce the variation of read current.

An embodiment of the present invention provides a memory device, comprising: a substrate; a stack structure, located on the substrate, including alternately stacked insulating layers and a plurality of conductive layers, the stack structure has holes; a channel layer is located on the substrate a hole including a first portion; and a second portion, the second portion having a lower number of grain boundaries than the first portion; and a charge storage structure located between the first portion and the plurality of conductors between layers, and the charge storage structure and the second portion sandwich the first portion.

An embodiment of the present invention provides a method for manufacturing a memory device, including: forming a stack structure on a substrate, the stack structure including alternately stacked insulating layers and a plurality of conductive layers; forming holes in the stack structure; the stack structure sidewalls in the hole form a charge storage structure; a channel layer is formed in the hole, including the sidewalls of the charge storage structure in the hole forming a first portion; and all the holes in the hole The sidewall of the first portion forms a second portion, and the number of grain boundaries of the second portion is lower than that of the first portion.

Another embodiment of the present invention provides a method for manufacturing a memory device, including: forming a stack structure on a substrate, the stack structure including alternately stacked first material layers and a plurality of second material layers; forming a hole in the hole; forming a channel layer in the hole, including a sidewall of the stack structure in the hole forming a first portion; and forming a second portion in the sidewall of the first portion in the hole, The number of grain boundaries of the second part is lower than the number of grain boundaries of the first part; a filling layer is formed in the hole to cover the sidewall of the second part; the plurality of second material layers are replaced with a plurality of a plurality of conductor layers; and forming a charge storage structure between the plurality of conductor layers and the plurality of first material layers.

Based on the above, in various embodiments of the present invention, the channel layer includes a first part and a second part. The low grain boundary density of the second part can reduce the variation of the read current.

10, 100, 200: base

12: Dielectric layer

14, 106, 206: holes

16: Amorphous silicon layer

16a, 16b: polysilicon layer

17: Tempering process

18: Grain Boundary

20: Epitaxial silicon layer

22: channel layer

C: intersection

102, 202: the first material layer

104, 204: Second material layer

108: Channel Layer

110: Fill Layer

112: Ditch

114: Horizontal opening

116, 216, 220: Silicon oxide layer

118, 218: Silicon nitride layer

120, 120a: high dielectric constant dielectric layer

122, 222, 222a: charge storage structures

124, 124a: conductor layer

C: intersection

P1, 108a, 208a: Part 1

P2, 108b, 208b: Part II

SK, SK’: Stacked structure

T1, T2, T3: Thickness

1A to 1D are schematic cross-sectional views of intermediate stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

2A to 2I are schematic cross-sectional views of intermediate stages of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention.

3A to 3D are schematic cross-sectional views of intermediate stages of a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

1A to 1D are schematic cross-sectional views of intermediate stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A , a substrate 10 is provided. The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. A dielectric layer 12 having openings 14 has been formed on the substrate 10 . Dielectric layer 12 may be a single layer, a composite layer, or a stacked layer. Substrate 10 and dielectric layer 12 may include other layers or elements. An amorphous silicon layer 16 is formed on the sidewalls of the dielectric layer 12 in the opening 14 . The amorphous silicon layer 16 may be deposited by chemical vapor deposition. The amorphous silicon layer 16 may be doped or not doped. The dopant can be P-type such as boron, or N-type such as phosphorus or arsenic.

Referring to FIG. 1B, a tempering process 17 is performed on the amorphous silicon layer 16 to form a polysilicon layer 16a. The polysilicon layer 16a has a plurality of grain boundaries 18 therein. There are a plurality of intersections C between the grain boundaries 18 . The thickness T1 of the polysilicon layer 16a is, for example, 10 nm to 20 nm.

Referring to FIG. 1B and FIG. 1C , if the thickness T1 of the polysilicon layer 16 a is thick, and there are many grain boundaries 18 and intersections C, it will be unfavorable for the current to travel. Implementation of the present invention For example, an etching process, such as anisotropic etching, may be selectively performed to reduce the thickness T1 of the polysilicon layer 16a to form the polysilicon layer 16b having a thickness T2. The thickness T2 of the polysilicon layer 16b is, for example, 1 nm to 5 nm. The density of the grain boundaries 18 in the polysilicon layer 16b decreases due to the thinning of the thickness. The intersection point C between the grain boundary 18 and the grain boundary 18 also decreases or disappears accordingly.

Referring to FIG. 1D , an epitaxial process is performed to form an epitaxial silicon layer 20 on the sidewalls of the polysilicon layer 16 b in the opening 14 . The epitaxial silicon layer 20 may not fill the opening 14, or may fill the remaining space of the opening 14 (not shown). The formation method of the epitaxial silicon layer 20 is, for example, a thermal wire chemical vapor deposition method. In some embodiments, deposition is performed using methane and argon at a temperature of 100 to 550 degrees Celsius and a pressure of 1 x 10" ² to 1 Torr. The epitaxial silicon layer 20 and the polysilicon layer 16b can jointly serve as the channel layer 22 . The polysilicon layer 16b serves as the first part P1 of the channel layer 22 ; the epitaxial silicon layer 20 serves as the second part P2 of the channel layer 22 . In some embodiments, the thickness T3 of the second portion P2 of the channel layer 22 is 75% to 95% of the total thickness (T2+T3) of the channel layer 22 . Compared with the polysilicon layer 16b, the grain boundary density of the epitaxial silicon layer 20 is lower, so the grain boundary density of the second portion P2 of the channel layer 22 is lower than that of the first portion P1. When the channel layer 22 is applied to the memory element, the variation of the read current can be reduced. Although the channel layer 22 is described as including the polysilicon layer 16b as the first part P1 and the epitaxial silicon layer 20 as the second part P2 as an example, the invention is not limited thereto. In other embodiments, other suitable types of polycrystalline layers and epitaxial layers may also be used as the first portion P1 and the second portion P2 of the channel layer 22 , respectively.

The above-mentioned process of forming the channel layer can be applied to the process of the memory device, and the following is an example.

2A to 2I are a three-dimensional diagram according to an embodiment of the present invention A schematic cross-sectional view of an intermediate stage of a manufacturing method for a memory device.

Referring to FIG. 2A , a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. The substrate 100 may further include an element layer (not shown) on the semiconductor substrate and a metal interconnect structure (not shown) on the element layer. The element layer may include active elements or passive elements. The active elements are, for example, transistors, diodes, and the like. Passive elements are, for example, capacitors, inductors, and the like. The metal interconnect structure may include a dielectric layer (not shown), plugs 101 and wires (not shown), and the like. The plug 101 can be electrically connected to the source line. The material of the plug 101 includes tungsten.

Referring to FIG. 2A , a stack structure SK is formed on the substrate 100 . The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The stacked structure SK includes a plurality of first material layers 102 and a plurality of second material layers 104 stacked alternately. The first material layer 102 may be an insulating layer, such as silicon oxide. The second material layer 104 may be an insulating layer such as silicon nitride. In this embodiment, the bottommost layer and the topmost layer of the stacked structure SK are both the first material layer 102, but the present invention is not limited thereto. In addition, in this embodiment, four layers of the first material layer 102 and three layers of the second material layer 104 are used for description, however, the present invention is not limited thereto.

Next, referring to FIG. 2B , a patterning process is performed to remove part of the stack structure SK in the memory array region to form one or more holes 106 passing through the stack structure SK. In one embodiment, the holes 106 may have substantially vertical sidewalls. In another embodiment. The holes 106 may have slightly sloping sidewalls (not shown).

Referring to FIG. 2C , a channel layer 108 is formed on the sidewall of the hole 106 . The channel layer 108 can be formed by using the method for forming the channel layer 22 in the above-mentioned embodiments. That is, the channel layer 108 may include the first portion 108a and the second portion 108b. The first portion 108a is connected to the plug 101, while the second portion 108b covers the first portion 108a. The first portion 108a is, for example, a polysilicon layer; the second portion 108b is, for example, an epitaxial silicon layer. The polysilicon layer and the epitaxial silicon layer can be formed by the methods for forming the polysilicon layer 16b and the epitaxial silicon layer 20 described in the above embodiments, respectively. The channel layer 108 is, for example, a conformal layer that does not fill the holes 106 .

Referring to FIG. 2D , the filling layer 110 is filled in the hole 106 . The material of the filling layer 110 is, for example, silicon oxide.

2E to 2I illustrate replacing the second material layer 104 with a conductor layer 124a, and forming a charge storage structure 122a between the conductor layer 124a and the first material layer 102, which will be described in detail below.

Referring to FIG. 2E , lithography and etching processes are performed to form slits 112 in the stacked structure SK. The trenches 112 expose the plurality of first material layers 102 and the plurality of second material layers 104 of the stacked structure SK.

Referring to FIG. 2F , an etchant is injected/passed through the trench 112 to remove the plurality of second material layers 104 of the stacked structure SK to form a plurality of horizontal openings 114 to expose the plurality of first material layers 102 of the stacked structure SK with the channel layer 108.

Referring to FIGS. 2F and 2G , the charge storage structures 122 are formed in the trenches 112 and the horizontal openings 114 . The charge storage structure 122 includes, for example, a silicon oxide layer 116 , a silicon nitride layer 118 and a high-k dielectric layer 120 . The high-k dielectric layer 120 refers to a dielectric layer with a dielectric constant greater than 4, such as Al ₂ O ₃ , HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO ₂ or a combination thereof. The silicon oxide layer 116 , the silicon nitride layer 118 and the high-k dielectric layer 120 are, for example, conformal layers, which can be formed by chemical vapor deposition or atomic layer deposition.

Referring to FIG. 2H , a conductor layer 124 is formed in the trenches 112 and the horizontal openings 114 to cover the charge storage structure 122 . The conductor layer 124 is, for example, tungsten, titanium or tantalum, The method of forming is chemical vapor deposition, for example.

2I, the conductor layer 124 of the trench 112 and the high-k dielectric layer 120 of the charge storage structure 122 are removed, leaving the conductor layer 124a and the charge storage structure 122a in the horizontal opening 114. The charge storage structure 122a includes a silicon oxide layer 116, a silicon nitride layer 118, and a high-k dielectric layer 120a.

After that, subsequent processes can be performed to complete the fabrication of the three-dimensional memory device.

3A to 3D are schematic cross-sectional views of intermediate stages of a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

Referring to FIG. 3A , a substrate 200 is provided. The substrate 200 may be a semiconductor substrate, such as a silicon-containing substrate. In one embodiment, doped regions may be formed in the substrate 200 according to design requirements. A device layer (not shown) and a metal interconnect structure (not shown) may be formed on the substrate 200 . The element layer may include active elements or passive elements. The active elements are, for example, transistors, diodes, and the like. Passive elements are, for example, capacitors, inductors, and the like. The metal interconnect structure may include dielectric layers, plugs and wires, and the like.

Referring to FIG. 3A , a stack structure SK' is formed on the substrate 200 . The stacked structure SK' includes a plurality of first material layers 202 and a plurality of second material layers 204 which are alternately stacked. The first material layer 202 may be an insulating layer, such as silicon oxide. The second material layer 204 may be a polysilicon layer. In this embodiment, the bottommost layer and the topmost layer of the stacked structure SK' are both the first material layer 202, but the present invention is not limited thereto. In addition, in this embodiment, four layers of the first material layer 202 and three layers of the second material layer 204 are used for description, however, the present invention is not limited thereto.

Next, referring to FIG. 3B , a patterning process is performed to remove part of the stack structure SK to form one or more holes 206 passing through the stack structure SK'. in an implementation For example, the holes 206 may have substantially vertical sidewalls. In another embodiment. The holes 206 may have slightly sloping sidewalls (not shown).

Referring to FIG. 3C , charge storage structures 222 are formed on the sidewalls of the holes 206 . The charge storage structure 222 includes, for example, a silicon oxide layer 216 , a silicon nitride layer 218 and a silicon oxide layer 220 . The silicon oxide layers 216 and 220 and the silicon nitride layer 218 are, for example, conformal layers, which can be formed by thermal oxidation or chemical vapor deposition.

Referring to FIG. 3D , a channel layer 208 is formed on the sidewalls of the charge storage structure 222 of the hole 206 . The channel layer 208 can be formed by using the method for forming the channel layer 22 in the above embodiments. That is, the channel layer 208 may include a first portion (eg, a polysilicon layer) 208a and a second portion (eg, an epitaxial silicon layer) 208b. The second portion 208b fills the hole 206, but not limited thereto. The polysilicon layer and the epitaxial silicon layer can be formed by the methods for forming the polysilicon layer 16b and the epitaxial silicon layer 20 described in the above embodiments, respectively, and details are not described herein again.

After that, subsequent processes can be performed to complete the fabrication of the three-dimensional memory device.

In various embodiments of the present invention, the channel layer includes a polysilicon layer and an epitaxial silicon layer. The low grain boundary density of the epitaxial silicon layer can reduce the variation of the read current. In addition, the thickness of the polysilicon layer can be reduced to reduce the number of grain boundaries and grain boundary intersections, thereby further reducing the variation of the read current.

10: Base

12: Dielectric layer

14: Hole

16b: polysilicon layer

18: Grain Boundary

20: Epitaxial silicon layer

22: channel layer

T3: Thickness

Claims (14)

A memory element, comprising: a substrate; a stack structure, located on the substrate, comprising a plurality of insulating layers and a plurality of conductor layers stacked alternately, the stacked structure has holes; a channel layer is located in the holes, comprising: a first portion; and a second portion, the second portion having a lower grain boundary number than the first portion and extending through the plurality of insulating layers and the plurality of conductor layers of the stacked structure; and a charge storage structure, located between the first portion and the plurality of conductor layers, and sandwiching the first portion between the charge storage structure and the second portion. The memory device of claim 1, wherein the first portion includes polysilicon and the second portion includes epitaxial silicon. The memory element of claim 2, wherein the thickness of the second portion is 75% to 95% of the total thickness of the channel layer. The memory device of claim 1, wherein the charge storage structure is further located between the plurality of insulating layers and the plurality of conductor layers of the stacked structure. The memory device of claim 4, further comprising a filling layer filled in the hole and covering the sidewall of the second portion. The memory element of claim 1, wherein the second portion fills the hole. A method for manufacturing a memory element, comprising: forming a stack structure on a substrate, the stack structure comprising a plurality of insulating layers and a plurality of conductive layers stacked alternately; forming holes in the stack structure; the stack structure sidewalls form a charge storage structure; and forming a channel layer in the hole, comprising: forming a first portion in the sidewall of the charge storage structure in the hole; and the first portion in the hole The sidewalls of the second portion form a second portion, the second portion having a lower grain boundary number than the first portion and extending through the plurality of insulating layers and the plurality of conductor layers of the stacked structure. The method for manufacturing a memory device according to claim 7, further comprising removing a part of the first part so as to reduce the thickness of the first part. The method for manufacturing a memory device according to claim 7, wherein the first part includes polysilicon, and the second part includes epitaxial silicon. The method of manufacturing a memory element according to claim 9, wherein the thickness of the second portion is 75% to 95% of the total thickness of the channel layer. A method for manufacturing a memory device, comprising: forming a stack structure on a substrate, the stack structure comprising a plurality of first material layers and a plurality of second material layers alternately stacked; forming a hole in the stack; forming a channel layer in the hole, including a sidewall of the stack in the hole forming a first portion; and forming a sidewall of the first portion in the hole forming a second part, the number of grain boundaries of the second part is lower than the number of grain boundaries of the first part; forming a filling layer in the hole to cover the sidewall of the second part; The two material layers are replaced by a plurality of conductor layers; and a charge storage structure is formed between the plurality of conductor layers and the plurality of first material layers. The method for manufacturing a memory device as claimed in claim 11, further comprising removing a part of the first part to make the thickness of the first part thinner. The method of manufacturing a memory device according to claim 11, wherein the first part includes polysilicon, and the second part includes epitaxial silicon. The method of manufacturing a memory element according to claim 13, wherein the thickness of the second portion is 75% to 95% of the total thickness of the channel layer.

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