CN105990365B - Memory element and its manufacturing method - Google Patents
Memory element and its manufacturing method Download PDFInfo
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- CN105990365B CN105990365B CN201510086829.2A CN201510086829A CN105990365B CN 105990365 B CN105990365 B CN 105990365B CN 201510086829 A CN201510086829 A CN 201510086829A CN 105990365 B CN105990365 B CN 105990365B
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Abstract
The present invention provides a kind of memory element and its manufacturing methods.The memory element includes substrate, the first doped region, multiple composite constructions, multiple wordline and electric charge storage layer.First doped region is located at substrate surface.Multiple composite constructions are located on the first doped region.Each composite construction includes two semiconductor fin structures and dielectric layer.Each semiconductor fin structure includes the second doped region, positioned at the top of each semiconductor fin structure；And matrix area, between the second doped region and the first doped region.Dielectric layer is between semiconductor fin structure.Multiple wordline are located in substrate.Each wordline covers the partial sidewall and atop part of each composite construction.Electric charge storage layer is between composite construction and wordline.
Description
Technical field
The invention relates to a kind of semiconductor element and its manufacturing methods, and in particular to a kind of memory element and
Its manufacturing method.
Background technique
Non-volatility memorizer (non-volatile memory) is due to that can carry out the deposit of multiple data, read, erase
Deng operation, and with the advantages of when power supply supply discontinuity, stored data will not disappear.Therefore, non-volatility memorizer
Have become prerequisite memory element in many electronic products, normal operating when maintaining electric equipment products to be switched on.
As the size of semiconductor element is increasingly reduced, the short-channel effect (short of conventional flat formula memory element
Channel effect) it is increasingly serious.This phenomenon will lead to second effect in memory element (2nd bit effect) and
The deterioration of programming interference (program disturbance).Therefore, it in order to improve above-mentioned phenomenon, develops in recent years rectilinear
Memory element (vertical memory device), so that identical passage length can also be maintained while size reduction,
To avoid short-channel effect and improve second effect and programming interference.
However, double-grid structure be easy to cause above-mentioned second effect in existing rectilinear memory element.Therefore,
How to improve the second effect of rectilinear memory element, and maintain original operation efficiency, is the project of current desired research.
Summary of the invention
The present invention provides a kind of memory element and its manufacturing method, can improve the second effect of rectilinear memory element,
And maintain original operation efficiency.
The present invention provides a kind of memory element comprising substrate, the first doped region, multiple composite constructions, multiple wordline with
And electric charge storage layer.Above-mentioned first doped region is located at substrate surface.Above-mentioned multiple composite constructions are located on the first doped region.It is each
Composite construction includes two semiconductor fin structures and dielectric layer.Each semiconductor fin structure includes the second doped region, position
In the top of each semiconductor fin structure；And matrix area, between the second doped region and the first doped region.Above-mentioned dielectric
Layer is between semiconductor fin structure.Above-mentioned multiple wordline are located in substrate.Each wordline covers the portion of each composite construction
Divide side wall and atop part.Above-mentioned electric charge storage layer is between composite construction and wordline.
In one embodiment of this invention, wherein above-mentioned electric charge storage layer is located at the side of each semiconductor fin structure.
In one embodiment of this invention, above-mentioned first doped region electrically more extends to each semiconductor fin structure.
In one embodiment of this invention, memory element further includes multiple first contact holes and multiple second contact holes.
Above-mentioned multiple first contact holes are located in the first part of substrate.Every one first contact hole is electrically connected corresponding second doping
Area.Above-mentioned multiple second contact holes are located on the second part of substrate.Every one second contact hole is electrically connected the first doped region.
In one embodiment of this invention, there is channel and third contact hole in the first part of above-mentioned substrate.Ditch
Road extends along second direction and exposes part of matrix area.Third contact hole is located in channel, and it is naked to be electrically connected channel institute
The part of matrix area of dew.
The present invention provides a kind of manufacturing method of memory element comprising following steps.Substrate is provided.In being formed in substrate
Multiple composite constructions.Each composite construction includes two semiconductor fin structures and dielectric layer.Above-mentioned dielectric layer is located at semiconductor
Between fin structure.Each semiconductor fin structure includes the second doped region and matrix area.First is formed in substrate surface to mix
Miscellaneous area.Above-mentioned first doped region connects each semiconductor fin structure.In forming multiple wordline in substrate.Each wordline covering is every
The partial sidewall and atop part of one composite construction.Electric charge storage layer is formed between composite construction and wordline.
In one embodiment of this invention, wherein the method for forming above-mentioned composite construction includes the following steps.In substrate
Form semiconductor fin structure.Dielectric layer is formed on the substrate.Part of dielectric layer is removed, to form composite construction.
In one embodiment of this invention, wherein the method for removing the above-mentioned dielectric layer in part includes the following steps.Form figure
The mask layer of case, covering part dielectric layer and part semiconductor fin structure.Remove the mask layer covering not being patterned
Dielectric layer.
In one embodiment of this invention, wherein the method for forming above-mentioned semiconductor fin structure includes the following steps.?
Doped layer is formed in substrate.Doped layer and substrate are patterned, to form semiconductor fin structure.
In one embodiment of this invention, the manufacturing method of memory element further includes more in being formed in the first part of substrate
A first contact hole.Every one first contact hole is electrically connected the second corresponding doped region.It is formed on the second part of substrate
Multiple second contact holes.Every one second contact hole is electrically connected the first doped region.
Based on above-mentioned, memory element provided by the invention includes composite construction.Also, in composite construction, dielectric layer position
Between two semiconductor fin structures, so that the electric charge storage layer of covering composite construction is located at each semiconductor fin structure
Side.In this way, which the second effect of rectilinear memory element can be greatly improved, and maintain original operation efficiency.Furthermore
Each semiconductor fin structure can be electrically connected by the first doped region, make connection between the inside of rectilinear memory element more
It is easy, and then simplifies the processing step of rectilinear memory element.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and cooperate appended attached drawing
It is described in detail below.
Detailed description of the invention
Fig. 1 is the upper schematic diagram according to memory element depicted in the first embodiment of the present invention.
Fig. 2 be according to depicted in the first embodiment of the present invention along the diagrammatic cross-section of the A-A ' line of Fig. 1.
Fig. 3 is the diagrammatic cross-section according to memory element depicted in another embodiment of the present invention.
Fig. 4 is the upper schematic diagram according to memory element depicted in the second embodiment of the present invention.
Fig. 5 A to Fig. 5 I is respectively the diagrammatic cross-section of the manufacturing method of the memory element of the B-B ' line along Fig. 1.
Fig. 6 be according to depicted in the first embodiment of the present invention along the diagrammatic cross-section of the C-C ' line of Fig. 1.
Fig. 7 be according to depicted in another embodiment of the present invention along the diagrammatic cross-section of the C-C ' line of Fig. 1.
Fig. 8 A to Fig. 8 B is the manufacturer according to the partial component of memory element depicted in another embodiment of the present invention
The diagrammatic cross-section of method.
Fig. 9 A to Fig. 9 B is the manufacturer according to the partial component of memory element depicted in one more embodiment of the present invention
The diagrammatic cross-section of method.
Figure 10 is the existing second effect schematic diagram with the memory element of an example of the invention.
Figure 11 is breakdown voltage (the punch through for reading the different positions of memory element of an example of the invention
Voltage, Vpt) schematic diagram.
Figure 12 is the curent change schematic diagram of the bit line of the memory element of an example of the invention
Figure 13 is channeling potential (channel potential) schematic diagram of the memory element of an example of the invention
Figure 14 be apply different voltages to an example of the invention memory element curent change schematic diagram
Figure 15 is the schematic diagram according to a kind of memory array structure depicted in the first embodiment of the present invention.
Figure 16 is the schematic diagram according to another memory array structure depicted in the first embodiment of the present invention.
Figure 17 is the schematic diagram according to a kind of memory array structure depicted in the second embodiment of the present invention.
Figure 18 is the schematic diagram according to another memory array structure depicted in the second embodiment of the present invention.
Figure 19 A to Figure 19 B is that (RR) operation is inversely read according to the memory element of the memory array structure of Figure 15
Schematic diagram.
Figure 20 A to Figure 20 B is to carry out channel hot electron injection according to the memory element of the memory array structure of Figure 15
(CHEI) schematic diagram operated.
Figure 21 A to Figure 21 B is to wear to cause then to energy band according to the memory element progress energy band of the memory array structure of Figure 15
Hot hole injects the schematic diagram of (BTBT HH) operation.
Figure 22 A to Figure 22 B is the signal that reverse read operation is carried out according to the memory element of the memory array structure of Figure 16
Figure.
Figure 23 A to Figure 23 B is to carry out channel hot electron implant operation according to the memory element of the memory array structure of Figure 16
Schematic diagram.
Figure 24 A to Figure 24 B is to wear to cause then to energy band according to the memory element progress energy band of the memory array structure of Figure 16
Hot hole implant operation schematic diagram.
Figure 25 A to Figure 25 B is the memory element operated according to FN electron injection depicted in the first embodiment of the present invention
Schematic diagram.
Figure 26 A to Figure 26 B is the memory element according to the hole FN implant operation depicted in the first embodiment of the present invention
Schematic diagram.
[symbol description]
10: substrate
10a, 54a: matrix area
11,12a, 13,56a: doped region
12,52,56: doped layer
14,22a, 22c: oxide layer
14a: patterned oxide layer
16,22b: nitration case
16a: patterned nitration case
18: advanced patterned thin film layer
18a: patterned advanced patterned thin film layer
19: hard mask layer
19a: patterned hard mask layer
20,70: mask layer
21: dielectric layer
22: electric charge storage layer
24: wordline
26,30: dielectric layer
28: isolation structure
32,34,36: contact hole
32a, 34a: contact hole
40,40a, 40b, 40c, 40d, 41,42,44: semiconductor fin structure
50,60: stack layer
54: base layer
62,62a, 64,64a: barrier layer
80,80a, 80b, 81: composite construction
100,101,200: memory element
150,160: memory cell string
B1, B2: block
BdL: matrix line
BL1~BLn: bit line
BLT1~BLTn: bitline transistor
D1, D2: direction
Id1、Id2: electric current
L1, L2: spacing
M1, M2: storage unit
MBL: main bit line
P1, P2: part
R1, R2: area
S1、S2、Vd、Vg、Vs、VT、Vb, V ', V ": voltage
SL: source electrode line
T, T1, T2, T3: channel
WL1~WL2m: wordline
Specific embodiment
Fig. 1 is the upper schematic diagram according to memory element depicted in the first embodiment of the present invention.Fig. 2 is according to this hair
The diagrammatic cross-section of the depicted A-A ' line along Fig. 1 of bright first embodiment.
Referring to Fig. 1 and Fig. 2, memory element 100 includes substrate 10, doped region 11, multiple composite constructions 80, multiple
Wordline 24 and electric charge storage layer 22.In Fig. 1, from the point of view of first direction D1, substrate 10 includes first part P1 and second
Divide P2.First part P1 is, for example, the array area of memory element 100, and second part P2 is, for example, the neighboring area of array.With
From the point of view of two direction D2, substrate 10 includes multiple first block B1 and multiple second block B2.First block B1 and the second block B2
It alternates.Every one first block B1 includes two a first area R1 and second area R2.Second area R2 is located at the first block R1
Between.Above-mentioned first direction D1 is different from second direction D2.In an exemplary embodiment, above-mentioned first direction D1 and second party
It is substantially perpendicular to D2.
Substrate 10 is, for example, semiconductor base, semiconducting compound substrate or silicon-on-insulator (silicon on
Insulator, SOI) substrate.Substrate 10 may include ion implanted regions, such as be formed by with p-type or N-type ion injection
Regions and source/drain.Substrate 10 may include single layer structure or multilayered structure.Substrate 10 is, for example, including shallow trench isolation
(shallow trench isolation, STI).In one embodiment, substrate 10 is, for example, silicon base or doped polycrystalline
Silicon.
Doped region 11 is located at the surface of substrate 10.Doped region 11 can be the first conductive type, and the first conductive type is, for example, N-type.
The admixture of doped region 11 is, for example, phosphorus or arsenic.The thickness of doped region 11 is, for example, 20-200 nanometers.
Multiple composite constructions 80 are located on doped region 11.D1 extends each composite construction 80 along a first direction.It is each multiple
Closing structure 80 includes two semiconductor fin structures 40 and dielectric layer 21.In one embodiment, each semiconductor fin structure
40 include doped region 12a and matrix area 10a.In another embodiment, part doped region 11 extends to each composite construction 80
Lower part.In other words, each semiconductor fin structure 40 may include doped region 12a, matrix area 10a and part doped region
11.Doped region 12a is located at the top of each semiconductor fin structure 40.Matrix area 10a be located at doped region 12a and doped region 11 it
Between.Source electrode/matrix/drain electrode of the 11/ matrix area 10a/ doped region 12a of doped region for example as memory element 100.Doped region
12a can be the first conductive type；Matrix area 10a can be the second conductive type.11/ matrix area 10a/ doped region 12a of doped region is, for example, N
+/P/N+ doped region or P+/N/P+ doped region.Also, doped region 11 can be identical or not identical with the doping concentration of doped region 12a；
Matrix area 10a can be doped or undoped.In one embodiment, the doping concentration of matrix area 10a is, for example, to be less than doped region
The doping concentration of 11 and doped region 12a.In another embodiment, the thickness of matrix area 10a is, for example, and is greater than doped region 11 and mixes
The thickness of miscellaneous area 12a.The thickness of matrix area 10a is, for example, 30-500 nanometers.The thickness of doped region 12a is, for example, that 20-200 receives
Rice.In each composite construction 80, dielectric layer 21 is, for example, to be located between two semiconductor fin structures 40.Dielectric layer 21 is for example
It is electrically to completely cut off above-mentioned two semiconductor fin structure 40.The material of dielectric layer 21 is, for example, oxide, nitride, nitrogen
Oxide or combinations thereof.In one embodiment, the width of semiconductor fin structure 40 is, for example, 30-60 nanometers；Dielectric layer 21
Width is, for example, 5-40 nanometers.
Referring once again to Fig. 1 and Fig. 2, multiple wordline 24 extend along second direction D2, and are located at the firstth area of substrate 10
On R1.Each wordline 24 covers the partial sidewall and atop part of each composite construction 80.The material of wordline 24 is, for example, that N+ mixes
Miscellaneous polysilicon, P+ DOPOS doped polycrystalline silicon, metal material (such as metal silicide, ruthenium, molybdenum or tungsten) or combinations thereof.
Electric charge storage layer 22 is between composite construction 80 and wordline 24.Electric charge storage layer 22 may include multiple portions, example
It is located at least in the side of each semiconductor fin structure 40 respectively in this way.In one embodiment, each portion of electric charge storage layer 22
Divide partial sidewall and the surface at top and doped region 11 of the semiconductor fin structure 40 in conformal covering composite construction 80, and
Dielectric layer 21 is not covered, as shown in Figure 2.In another embodiment, a part of conformal covering composite junction of electric charge storage layer 22
The partial sidewall of semiconductor fin structure 40 in structure 80 and top and the surface of doped region 11, another part cover dielectric layer
21, and it is connected to each other to homogenous material layer, as shown in Figure 6.Electric charge storage layer 22 is, for example, floating grid (floating
Gate), electric charge capture layer (charge trapping layer) or nanocrystal (nano-crystal).In one embodiment,
Electric charge storage layer 22 is, for example, by oxide layer 22a/ nitration case 22b/ oxide layer 22c (Oxide-Nitride-Oxide, ONO) institute
The composite layer of composition, this composite layer can be three layers or more.The material of electric charge storage layer 22 include silica, silicon nitride or its
Combination.Electric charge storage layer 22 not only there is charge to store function, it may have electrically by doped region 12a, doped region 11 and wordline 24
The effect of isolation.
Each semiconductor fin structure 40 is, for example, between electric charge storage layer 22 and dielectric layer 21.Of the invention
In one embodiment, when element operation, in doped region 12a (for example as drain electrode), close to 22 side of electric charge storage layer
Carrier can be influenced by wordline 24 (for example as grid) bias and is flowed into the electric charge storage layer 22 of one side；And it adulterates
Close to the electric charge carrier of 21 side of dielectric layer in area 12a (for example as drain electrode), Ze Hui auto-dope area 12a (e.g. makees
For drain electrode) it penetrates to doped region 11 (for example as source electrode).In this way, can avoid two positions of same storage unit each other
It interacts, and then improves the second effect of memory element.
Referring once again to Fig. 1, memory element 100 further includes multiple first contact holes 34 and multiple second contact holes 32.
First contact hole 34 is located on the first part P1 of substrate 10；Second contact hole 32 is located on the second part P2 of substrate 10.?
In one embodiment, the second contact hole 32 and the first contact hole 34 are, for example, the second area R2 for being located at substrate 10.Every 1 first connects
Touching window 34 is electrically connected the doped region 12a in corresponding semiconductor fin structure 40.Every one second contact hole 32 is electrically connected
Doped region 11.The material of second contact hole 32 and the first contact hole 34 is, for example, aluminium, copper or its alloy.
It is noted that each semiconductor fin structure 40 as included by composite construction 80 is located at doped region 11
On, therefore, when source electrode of the doped region 11 for example as memory element, but the source electrode in each semiconductor fin structure 40 that
This is electrically connected.In this way, which the connection between the inside of rectilinear memory element is more easy, rectilinear storage is significantly simplified
The framework of relativeness and stacked structure between element.
Fig. 3 is the diagrammatic cross-section according to memory element depicted in another embodiment of the present invention.
Referring to figure 3., the composite construction 81 in memory element 101 is similar to the composite construction 80 in memory element 100,
Difference is that each semiconductor fin structure 41 further includes barrier layer 64a and barrier layer 62a.Barrier layer 62a is located at matrix area
Between 10a and doped region 11；Barrier layer 64a is between matrix area 10a and doped region 12a.In one embodiment, barrier layer
The material of 62a and barrier layer 64a includes oxide, nitride, nitrogen oxides or combinations thereof.Barrier layer 62a and barrier layer 64a can
To be identical or different material.In this embodiment, barrier layer 62a and barrier layer 64a is located at doped region 11 and doping
Between area 12a, to play the part of the role for stopping dopant diffusion in doped region 11 and doped region 12a.Therefore, barrier layer 62a and resistance
The thickness of barrier 64a should be able to stop doped region 11, in matrix area 10a and doped region 12a admixture diffusion, and can make
Electric charge carrier (such as electronics or hole) is easy tunneling.
Fig. 4 is the upper schematic diagram according to memory element depicted in the second embodiment of the present invention.It is worth noting that,
The memory element 100 of memory element 200 and Fig. 1 of Fig. 4 the difference is that further including that third connects in the first part P1 of substrate 10
Touch window 36.
Referring to figure 4., memory element 200 is similar to memory element 100, and difference is to further include third contact hole 36.
Composite construction 80, wordline 24, the second contact hole 32 and the first contact hole 34 are no longer subject to as described in memory element 100 in this
It repeats.
Third contact hole 36 is located among channel T3.Channel T3 is located at the first part P1 of substrate 10.In one embodiment,
Channel T3 is, for example, the second block B2 for being located at substrate 10.Channel T3 is, for example, to extend along second direction D2.Also, channel T3
Expose the matrix area 10a (not being painted) in corresponding semiconductor fin structure 40.That is, in the first block B1,
Matrix area 10a is between doped region 12a and doped region 11；In the second block B2, matrix area 10a is located on doped region 11,
And channel T3 exposes matrix area 10a.
Third contact hole 36 is located in channel T3.Third contact hole 36 is located in the second block B2, and along second direction
D2 extends.The material of third contact hole 36 is, for example, aluminium, copper or its alloy.In this embodiment, third contact hole 36 electrically connects
Meet the exposed matrix area 10a of channel T3.
Significantly, since third contact hole 36 is electrically connected the matrix area 10a of semiconductor fin structure 40.Also
It is to say, the matrix area 10a of multiple semiconductor fin structures 40 can be electrically connected to each other by third contact hole 36.Therefore, when
Matrix area 10a for example as memory element matrix when, can be applied by being subsequently formed the conducting wire above third contact hole 36
Power-up is depressed into matrix, to control the current potential of matrix.In this way, the current potential of matrix can clearly be learnt, avoid the current potential of matrix by
The coupling effect of other biass and be floating (floating) state.
Fig. 5 A to Fig. 5 I is respectively the diagrammatic cross-section of the manufacturing method of the memory element of the B-B ' line along Fig. 1.Following
Embodiment in, component identical with the memory element 100 of Fig. 1 is with identical symbology.Also, the material of identical components,
Relativeness with adjacent member is not repeated here as described in memory element 100 in this.
Referring to Fig. 1 and Fig. 5 A, substrate 10 is provided.Then, doped layer 12 is formed on the substrate 10.Doped layer 12
It can be the first conductive type, the first conductive type is, for example, N-type.The method for forming doped layer 12 is, for example, to carry out ion note to substrate 10
Enter technique, admixture is flowed into the surface of substrate 10.The admixture of doped layer 12 is, for example, phosphorus or arsenic, and the dosage of doping is, for example,
1×1013/cm2To 1 × 1014/cm2。
B referring to figure 5. forms hard mask layer 19 on doped layer 12.Hard mask layer 19 can be single-layer or multi-layer.Hard mask
Layer 19 material include silica, silicon nitride, advanced patterned film (advanced patterning film, APF) or its
Combination.In one embodiment, hard mask layer 19 may include oxide layer 14, nitration case 16 and advanced patterned thin film layer 18.Shape
Method at hard mask layer 19 is, for example, that oxide layer 14, nitration case are sequentially formed on doped layer 12 using chemical vapour deposition technique
16 and advanced patterned thin film layer 18.In another embodiment, hard mask layer 19 may include any the two in above-mentioned three layers.
Then, patterned mask layer 20 is formed on hard mask layer 19.The material of mask layer 20 is, for example, photoresist.
C referring to figure 5. is mask with patterned mask layer 20, is carried out to hard mask layer 19, doped layer 12 and substrate 10
Etching technics, to form multiple patterned hard mask layer 19a, multiple doped region 12a, multiple matrix area 10a and multiple channels
T.Etching technics is, for example, anisotropic etching, such as dry etching method.Dry etching method can be plasma etching, reactivity
Ion etching etc..In one embodiment, patterned hard mask layer 19a may include patterned oxide layer 14a, patterned nitrogen
Change layer 16a and patterned advanced patterned thin film layer 18a.Also, the doping below each patterned hard mask layer 19a
Area 12a and matrix area 10a forms semiconductor fin structure 40.
The depth of channel T is, for example, between 1500 angstroms to 6000 angstroms.In one embodiment, the side wall of channel T is for example
It is that admixture is flowed into matrix area when preventing the subsequent bottom to channel T from carrying out ion implantation technology with its plane perpendicular
In 10a.Also, two base angles of channel T are, for example, right angle, chamfering or fillet.In one embodiment, two base angles of channel T
E.g. chamfering or fillet, so that the admixture of the bottom channel T is easy diffusion when subsequent progress ion implantation technology.However, this
Invention is not limited thereto.
Then, C and Fig. 5 D referring to figure 5., remove patterned mask layer 20 and patterned advanced patterned thin film layer
18a.Meanwhile exposing multiple channel T1.Remove patterned mask layer 20 and patterned advanced patterned thin film layer 18a's
Method is, for example, to carry out dry or wet to strip/etching technics.
Later, using patterned nitration case 16a as mask, ion implantation technology is carried out to substrate 10, admixture is injected into ditch
In the substrate 10 of the road bottom T1, to form doped region 11.Doped region 11 can be the first conductive type, and the first conductive type is, for example, N-type.
The admixture of doped region 11 is, for example, phosphorus or arsenic, and the dosage of doping is, for example, 1 × 1013/cm2To 1 × 1014/cm2.In an embodiment
In, (block) ion implanting can be stopped to form doped region 11 due to being located at the patterned nitration case 16a above doped region 12a
When inject doped region 12a simultaneously, therefore the doping concentration of doped region 11 Yu doped region 12a can be adjusted separately.
It is worth noting that, in one embodiment, since the base angle of above-mentioned channel T1 is chamfering or fillet, thus making
The dopant diffusion range that doped region 11 must be injected is wider, and then diffuses in the substrate 10 of the bottom matrix area 10a, in matrix area
Doped region 11 is formed in the substrate 10 of 10a and the bottom channel T1.In another embodiment, can carry out ion implantation technology it
Afterwards, then to substrate 10 hot tempering process is carried out, so that the dopant diffusion of injection is into the substrate 10 of the bottom matrix area 10a.Again
In one embodiment, doped region 11 be may extend into the substrate 10 of second part P2.
E referring to figure 5. forms dielectric layer 21 between semiconductor fin structure 40.The forming method of dielectric layer 21 is for example
It is to form dielectric materials layer on the substrate 10 using thermal oxidation method or chemical vapour deposition technique.Then, may optionally utilize
Dielectric materials layer is ground to by mechanical lapping (CMP) technique to be flushed with patterned nitration case 16a.
Later, patterned nitration case 16a, patterned oxide layer 14a and part of dielectric layer 21 are removed.Remove patterning
Nitration case 16a method including the use of hot phosphoric acid solution.The method of dielectric layer 21 is removed including the use of buffer oxide etching agent
(buffered oxide etchant, BOE).Alternatively, also can use comprehensive etching (blanket etching) technique one
And remove above-mentioned three.However, invention is not limited thereto.In one embodiment, above-mentioned steps can also be omitted.
F and 5G referring to figure 5. forms patterned mask layer 70 on the substrate 10.Patterned mask layer 70 covers often
Dielectric layer 21 and part semiconductor fin structure 40 between a pair of of semiconductor fin structure 40, expose adjacent two pairs of semiconductors
Dielectric layer 21 between fin structure 40.In one embodiment, the spacing L1 of patterned mask layer 70 is, for example, semiconductor fin
Twice of the spacing L2 of shape structure 40, but it is not limited to this.In another embodiment, optionally patterned cover is being formed
Before mold layer 70, prior to forming hard mask layer (not being painted) in substrate 10.
Then, remove the dielectric layer 21 that the mask layer 70 that is not patterned covers, with formed multiple composite constructions 80 and
Multiple channel T2.Each composite construction 80 includes two semiconductor fin structures 40 and dielectric layer 21.Also, above-mentioned dielectric layer 21
Between two semiconductor fin structures 40.Each channel T2 is between two neighboring composite construction 80.It removes later
Patterned mask layer 70.
H referring to figure 5., in formation electric charge storage layer 22 in substrate 10.Electric charge storage layer 22 along composite construction 80 top
The surface in face and side and doped region 11 is conformally formed.The forming method of electric charge storage layer 22 is, for example, chemical vapor deposition
Method or thermal oxidation method etc..
Referring to Fig. 1 and Fig. 5 I, wordline 24 is formed on electric charge storage layer 22.Each wordline 24 is along second party
Extend to D2, covers the partial sidewall and atop part of each composite construction 80.That is, above-mentioned electric charge storage layer 22 is located at again
It closes between structure 80 and wordline 24.
Fig. 6 be according to depicted in the first embodiment of the present invention along the diagrammatic cross-section of the C-C ' line of Fig. 1.Fig. 7 be according to
The diagrammatic cross-section of the depicted C-C ' line along Fig. 1 of another embodiment of the present invention.
Fig. 6 is please referred to, after forming wordline 24, in formation dielectric layer 26 in substrate 10.Then, photoetching and etching are utilized
Technique removes part of dielectric layer 26 and Partial charge storage layer 22, to form multiple connect in the substrate 10 of second part P2
Contact hole 34a.Meanwhile multiple contact hole 32a are formed in the substrate of first part P1 10.The bottom surface of each contact hole 34a is exposed
Doped region 11 out.The bottom surface of each contact hole 32a exposes the doped region 12a of semiconductor fin structure 40.
Later, the first contact hole 34 and the second contact hole 32 are respectively formed in contact hole 34a and contact hole 32a.It is each
First contact hole 34 is electrically connected the doped region 12a in corresponding semiconductor fin structure 40.Every one second contact hole, 32 electricity
Property connecting doped area 11.The forming method of first contact hole 34 and the second contact hole 32 is, for example, first to form conductor on the substrate 10
Material layer.Conductor material layer is, for example, aluminium, copper or its alloy.The forming method of conductor material layer can be physical vapour deposition (PVD)
Method, e.g. sputtering method.And then with chemical mechanical milling method or be etched back to method remove contact hole 34a and contact hole 32a with
Outer conductor material layer.
Fig. 7 is please referred to, it in another embodiment, can be in the second part of substrate 10 before forming above-mentioned dielectric layer 26
Multiple isolation structures 28 are formed in P2.The e.g. shallow trench isolation regions of isolation structure 28 (shallow trench isolation,
STI).Then, doped region 13 is formed in the substrate 10 between isolation structure 28.Doped region 13 is located at 11 top of doped region, and
Doped region 13 and doped region 11 are electrically connected.In one embodiment, doped region 11, doped region 12a and doped region 13 are all first
Conductivity type, e.g. N-type.The admixture of doped region 13 is, for example, phosphorus or arsenic, and the dosage of doping is, for example, 1 × 1013/cm2To 1 ×
1014/cm2.Thereafter, dielectric layer 30 is formed above the substrate 10 of second part P2.Then, it re-forms dielectric layer 26, first connect
Touch window 34 and the second contact hole 32.
It is worth noting that, in this embodiment, since the bottom surface of every one second contact hole 32 is contacted with doped region 13, and
Doped region 13 is located at 11 top of doped region, therefore every one second contact hole 32 can pass through doped region 13 and be electrically connected doped region 11.And
And doped region 11 connects each semiconductor fin structure 40.Therefore, every one second contact hole 32 can pass through doped region 13 and doping
Area 11 is electrically connected each semiconductor fin structure 40.
In one embodiment of this invention, subsequent technique may include above the second contact hole 32 and the first contact hole 34
Conducting wire is formed, so that doped region 11 and doped region 12a are electrically connected to external component by conducting wire.However, the present invention not with
This is limited.
Fig. 8 A to Fig. 8 B is the manufacturer according to the partial component of memory element depicted in another embodiment of the present invention
The diagrammatic cross-section of method.Fig. 9 A to Fig. 9 B is the partial component according to memory element depicted in one more embodiment of the present invention
The diagrammatic cross-section of manufacturing method.
In another embodiment of the present invention, above-mentioned semiconductor fin structure 40 semiconductor fin structure as shown in Figure 8 B
42.Fig. 8 A is please referred to, the forming method of semiconductor fin structure 42 e.g. forms stack layer 50 on the substrate 10.Stack layer 50
It from bottom to top include doped layer 52, base layer 54 and doped layer 56.Above-mentioned doped layer 52, base layer 54 and doped layer 56 can be distinguished
It is formed using chemical vapour deposition technique or epitaxy.
Later, Fig. 8 B is please referred to, photoetching and etching technics, patterning base layer 54 and doped layer 56 are carried out, to form half
Conductor fin structure 42.Each semiconductor fin structure 42 includes matrix area 54a and doped region 56a.Above-mentioned doped layer 52 again can
Referred to as doped region.52/ matrix area 54a/ doped region 56a of doped layer (doped region) is for example as source electrode/matrix/drain electrode.It is worth
One is mentioned that, since above-mentioned doped layer 52 does not carry out patterned step, when pretending as source electrode, and each semiconductor fin structure
42 source electrode can be electrically connected to each other.
In one more embodiment of the present invention, above-mentioned semiconductor fin structure 40 semiconductor fin structure as shown in Figure 9 B
44.Fig. 9 A is please referred to, the forming method of semiconductor fin structure 44 is, for example, first to form stack layer 60 on the substrate 10.Stack layer
60 from bottom to top include doped layer 52, barrier layer 62, base layer 54, barrier layer 64 and doped layer 56.Form barrier layer 62 and resistance
The method of barrier 64 is, for example, chemical vapour deposition technique.
Later, Fig. 9 B is please referred to, patterning doped layer 56, barrier layer 64, base layer 54 and barrier layer 62 are multiple to be formed
Semiconductor fin structure 44.Semiconductor fin structure 44 further includes patterned barrier layer compared to semiconductor fin structure 42
62a and patterned barrier layer 64a.
Figure 10 is the existing second effect schematic diagram with the memory element of an example of the invention.
Please refer to Figure 10, the longitudinal axis be deputy threshold voltage variations amount (delta threshold voltage, dVt),
Horizontal axis is primary threshold voltage variations amount.Since the electric charge storage layer in memory element of the invention is located at semiconductor fin-shaped
The side of structure, and two adjacent semiconductor fin structures are separated by dielectric layer.Therefore, in operation, semiconductor
Electric charge carrier in fin structure close to dielectric layer side can penetrate (penetrate) to source electrode from drain electrode, avoid same deposit
Two positions of storage unit influence each other.Via Figure 10 it is found that the second effect of memory element of the invention is existing
60%, greatly improve the second effect of memory element.
Figure 11 is the breakdown voltage schematic diagram for reading the different positions of memory element of an example of the invention.Figure 12 is this hair
The curent change schematic diagram of the bit line of the memory element of a bright example.Figure 13 is the logical of the memory element of an example of the invention
Road current potential schematic diagram.
The memory element of an example of the invention is led by taking composite construction shown in Fig. 2 as an example including left and right two and half
Body fin structure.In this example, different voltages can be applied respectively and (apply drain voltage V in drain electrode in source electrode and drain electroded, and
Apply source voltage V in source electrodes=0V), with read the left side semiconductor fin structure it is upper, the next, and observe it to not
Select the electric current and the channel (matrix in such as Fig. 2 of bit line (the doped region 12a of the semiconductor fin structure on the right in such as Fig. 2)
Area 10a) voltage influence.
Please refer to Figure 11, Figure 12 and Figure 13, the longitudinal axis of Figure 11 be breakdown voltage (punch through voltage,
Vpt)；Horizontal axis is passage length (Lg).Two curves respectively indicate in figure: when read semiconductor fin structure upper respectively and
When the next, influence of the different passage lengths to reach throught voltage.Figure 12 and Figure 13 is then respectively indicated when reading upper, non-selected position
The influence of the curent change and down channel current potential of line (for floating (floating) or ground connection (grounding) state).
Via Figure 11 and Figure 12 it is found that when non-selected bit line is floating state, breakdown voltage when reading upper is relatively read
Breakdown potential when the next is forced down.This result is attributed to when reading upper, is applied to the common drain line (doped region in such as Fig. 2
11) drain voltage VdSo that channel (the doped region in such as Fig. 2 below non-selected bit line (the doped region 12a in such as Fig. 2)
10a) current potential rises, and forms an equivalent grid bias, causes the channeling potential for selecting bit line to improve, and then form breakdown current,
As shown in figure 13.In contrast, when non-selected bit line is ground state (as 0V), the spy of reach throught voltage can be greatly improved
Property, as shown in FIG. 12 and 13.
Figure 14 be apply different voltages to an example of the invention memory element curent change schematic diagram.
Referring to Fig. 2 and Figure 14, in this example, drain voltage Vd；Select the source voltage S1=0 of bit line；
The source voltage S2 of non-selected bit line is respectively floating state (F), 0V, 1V, 2V.Solid line 1 to solid line 4 in Figure 14 respectively indicates
Drain leakage I when source voltage S2 is respectively floating state, 2V, 1V, 0Vd1.Dotted line 5,6,7 is respectively to work as source voltage S2
When=0V, S2=1V and S2=2V, the leakage current I of source voltage S2d2。
By the result of Figure 14, it can be seen that, the source voltage S2 of non-selected bit line is higher, can inhibit the programming of non-selected bit line
Interference, but the leakage current that will lead to the source voltage S1 of selection bit line improves.The source voltage S2 of lower non-selected bit line can
Inhibit the leakage current of the source voltage S1 of above-mentioned selection bit line, but the programming of non-selected bit line can be caused to interfere.Therefore, it is intended to program
When the next, preferred embodiment is to make the source voltage S2 of non-selected bit line between 1V between 2V.
Figure 15 is the schematic diagram according to a kind of memory array structure depicted in the first embodiment of the present invention.Figure 16 be according to
According to the schematic diagram of another memory array structure depicted in the first embodiment of the present invention.
Figure 15 is please referred to, Figure 15 is painted multiple memory cell strings (cell strings) 150.Above-mentioned multiple memory cell strings
150 via source electrode line SL, a plurality of wordline WL1~WL2m(wherein m is the integer greater than 1) and multiple bit lines BL1~BLn(wherein n
For the integer greater than 1) concatenation, to be arranged in a storage array (memory array) in column direction and line direction.Source electrode line
SL is, for example, the source electrode for concatenating each storage unit in storage array.Wordline WL1、WL2...WL2mIt e.g. concatenates respectively multiple
The grid of storage unit.Bit line BL1、BL2...BLnThe drain electrode of multiple storage units is e.g. concatenated respectively.In one embodiment,
Bit line BL1、BL2It can be respectively coupled to bitline transistor BLT1And BLT2；Bit line BL3、BL4It can be respectively coupled to bitline transistor
BLT3And BLT4。
Each memory cell string 150 may include 32 storage unit M1 or more.It in one embodiment, can be through
As applying different size of voltage to source electrode corresponding to storage unit M1, drain electrode and grid respectively, to be read out
(read), (program) or the operation of (erase) of erasing are programmed.For example, e.g. first to bit line BL1Bit line crystal
Pipe BLT1Apply a critical voltage VTMake bitline transistor BLT1Conducting, and via bit line BL1Apply drain voltage Vd, via source electrode
Line SL applies source voltage VsAnd via wordline WLiApply grid voltage VgTo storage unit M1.
Referring to Fig. 1 and Figure 15, in one embodiment of this invention, two drain electrodes in each composite construction 80 can
Share identical main bit line MBL (the bit line BL in such as Figure 151).In this way, when applying a voltage to bit line BL1When, via bit line
Transistor BLT1Or BLT2One of drain electrode of same composite construction 80 can be only selected, at this point, non-selected drain voltage is floating
Set state.
In contrast, referring to Fig. 1 and Figure 16, in this memory array structure, in each composite construction 80 two
A drain electrode is connected to different main bit line MBL (the bit line BL in such as Figure 161、BL3).In this way, when applying a voltage to bit line
BL1When, via bitline transistor BLT1Or BLT2The drain electrode of different composite structure 80 may be selected.That is, same composite construction
Two drain electrodes in 80 can be selected simultaneously, and can be respectively provided with different voltage.For example, when applying a voltage to bit line
BL1And BL3When, it can be respectively via bitline transistor BLT1And BLT3Two of same composite construction 80 are selected to drain.
Figure 17 is the schematic diagram according to a kind of memory array structure depicted in the second embodiment of the present invention.Figure 18 be according to
According to the schematic diagram of another memory array structure depicted in the second embodiment of the present invention.
Multiple memory cell strings 160 are painted referring to Fig. 4 and Figure 17, Figure 17.Each memory cell string 160 may include
32 storage unit M2 or more.Above-mentioned multiple memory cell strings 160 are via matrix line BdL, multiple bit lines BL1~
BLn(wherein n is greater than 1 integer), source electrode line SL and a plurality of wordline WL1~WL2m(wherein m is the integer greater than 1) concatenation,
To be arranged in a storage array in column direction and line direction.It is worth noting that, compared to the first embodiment, the present embodiment
Matrix line BdL can concatenate the matrix of each storage unit in storage array.That is, in addition to applying drain voltage Vd, source electrode
Voltage VsAnd grid voltage VgExcept, the present embodiment more can apply matrix voltage V via matrix line BdLbTo storage unit, with
Control the current potential of matrix.In addition, in the present embodiment, two drain electrodes of each composite construction 80 can share identical main bit line
MBL。
Two drain electrodes connection referring to Fig. 4 and Figure 18, in this memory array structure, in each composite construction 80
To different main bit line MBL (the bit line BL in such as Figure 182、BL4).In this way, when applying a voltage to bit line BL2When, via position
Line transistor BLT1Or BLT2It can select the drain electrode of different composite structure 80.That is, two in same composite construction 80 leak
Pole can be selected simultaneously, and can be respectively provided with different voltage.
On the other hand, said memory cells M1, M2 can be read out by various methods, program or erase.Citing comes
It says, the method for reading storage unit M1, M2 is, for example, reverse reading (RR).Alternatively, storage unit M1, M2 can pass through channel thermoelectric
Son injects (CHEI) or the energy band mode for causing hot hole injection (BTBT HH) tunneling to energy band to program.In addition, storage unit
M1, M2 can carry out the operation of erasing of storage unit by modes such as BTBT HH, FN electron injection or the hole FN injections.Table 1 arranges
Three kinds of operating conditions that storage unit is read out out, program and is erased, however, the present invention is not limited thereto.
Table 1
Hereafter two kinds of memory array structures shown in Figure 15, Figure 16 will be directed to respectively using exemplary embodiment, in embodiment
State reverse reading, channel hot electron injection, the energy band operation for causing hot hole to inject tunneling to energy band.Also, in hereinafter by act
Example illustrates the operating method of the injection of the hole FN and FN electron injection.It should be understood that the scope of the present invention be not limited to it is cited
Operating method and operation voltage.
Figure 19 A to Figure 19 B is the signal that reverse read operation is carried out according to the memory element of the memory array structure of Figure 15
Figure.It is upper and the next that Figure 19 A, 19B respectively indicate reading.
Referring to Figure 15, Figure 19 A and Figure 19 B, the drain electrode of semiconductor fin structure 40a is, for example, and bit line BL1's
Bitline transistor BLT1Connection；Semiconductor fin structure 40b be, for example, and bit line BL1Bitline transistor BLT2Connection；Semiconductor
The drain electrode of fin structure 40c be, for example, and bit line BL3Bitline transistor BLT3Connection；Semiconductor fin structure 40d be, for example, with
Bit line BL3Bitline transistor BLT4Connection.Source electrode line SL, bit line BL1、BL2、BL3、BL4And bitline transistor BLT1、BLT2、
BLT3、BLT4Operation voltage it is as shown in table 2.
Table 2
| BL1 | BL3 | BL2 | BL4 | BLT1 | BLT2 | BLT3 | BLT4 | SL | |
| It is upper | 0V | 0V | 0V | 0V | 9V | 0V | 9V | 0V | 1.6V |
| It is the next | 1.6V | 1.6V | 1.6V | 1.6V | 9V | 0V | 9V | 0V | 0V |
Referring to table 2, Figure 19 A, Figure 19 B, reading upper operating condition is, for example, that will read bias to be applied to source
Extremely (source voltage Vs=1.6V) and gate terminal (grid voltage Vg=7V), and selected semiconductor fin structure 40a,
The drain electrode end of 40c is biased (drain voltage Vd=0V), to sense the charge in drain side junction.At this point, non-selected
The drain voltage V of semiconductor fin structure 40b, 40ddFor floating state (F).In contrast, as shown in Figure 19 B, it reads the next
Operating condition be, for example, by read bias be applied to drain electrode end (drain voltage Vd=1.6V), to sense on source side injection
Charge.In addition, the matrix voltage V of aforesaid operations conditionbFor floating state, but invention is not limited thereto.For example, when
When the structure of memory element is as shown in Figure 4, matrix voltage VbIt is also possible to 0V.
Figure 20 A to Figure 20 B is to carry out channel hot electron implant operation according to the memory element of the memory array structure of Figure 15
Schematic diagram.It is upper and the next that Figure 20 A, 20B respectively indicate programming.Source electrode line SL, bit line BL1、BL2、BL3、BL4And bit line
Transistor BLT1、BLT2、BLT3、BLT4Operation voltage it is as shown in table 3.
Table 3
| BL1 | BL3 | BL2 | BL4 | BLT1 | BLT2 | BLT3 | BLT4 | SL | |
| It is upper | 4V | 0V | 0V | 4V | 9V | 0V | 9V | 0V | 0V |
| It is the next | 0V | 4V | 4V | 0V | 9V | 0V | 9V | 0V | 4V |
Referring to table 3, Figure 20 A and Figure 20 B, programming upper operating condition is, for example, to apply grid voltage Vg=
12V applies source voltage V so that channel conductives=0V and matrix voltage Vb=0V/F, and apply intermediate level respectively
Drain voltage Vd=4V and 0V is to selected semiconductor fin structure 40a, 40c, to form the electric field from source electrode to drain electrode.Not
The drain voltage V of semiconductor fin structure 40b, 40d of selectiondFor floating state (F).When the bias between source electrode and drain electrode is suitable
When big, in that will generate excessive thermoelectron on channel, the thermoelectron meeting injector grid of part is to be programmed.Conversely, as schemed
Shown in 20B, programming the next operating condition is then the source voltage V for applying intermediate levels=4V, and apply drain voltage respectively
Vd=0V and 4V forms the electric field from drain electrode to source electrode to selected semiconductor fin structure 40a, 40c.It is worth mentioning
It is, when programming upper, drain voltage Vd=4V and 0V respectively indicate programming and it is unprogrammed (inhibit)；When programming the next,
Drain voltage Vd=0V and 4V respectively indicate programming and it is unprogrammed.
Figure 21 A to Figure 21 B is to wear to cause then to energy band according to the memory element progress energy band of the memory array structure of Figure 15
The schematic diagram of hot hole implant operation.Figure 21 A, 21B respectively indicate erase it is upper and the next.Source electrode line SL, bit line BL1、BL2、
BL3、BL4And bitline transistor BLT1、BLT2、BLT3、BLT4Operation voltage it is as shown in table 4.
Table 4
| BL1 | BL3 | BL2 | BL4 | BLT1 | BLT2 | BLT3 | BLT4 | SL | |
| It is upper | 5V | 0V | 0V | 5V | 9V | 0V | 9V | 0V | 0V |
| It is the next | 0V | 5V | 5V | 0V | 9V | 0V | 9V | 0V | 5V |
Referring to table 4, Figure 21 A and Figure 21 B, upper operating condition of erasing is, for example, to apply grid voltage Vg=-
8V, while applying source voltage Vs=0V and matrix voltage Vb=0V/F, and apply drain voltage V respectivelyd=5V and 0V is to selected
Semiconductor fin structure 40a, 40c selected.Under these bias conditions, pass through energy band caused hot hole injection tunneling to energy band
It is upper to erase that charged carriers are injected into electric charge storage layer.Conversely, 1B referring to figure 2., erases the next operating condition then
To apply source voltage Vs=5V, and apply drain voltage V respectivelyd=0V and 5V to selected semiconductor fin structure 40a,
40c。
Significantly, since it is above-mentioned it is reverse read, channel hot electron injection and energy band is tunneling to energy band causes heat
The operation of hole injection is all memory array structure as shown in figure 15, i.e., two drain electrodes in each composite construction 80 can be shared
Identical main bit line MBL.That is, aforesaid operations can betide half simultaneously in two adjacent composite constructions 80a, 80b
Conductor fin structure 40a, 40c or semiconductor fin structure 40b, 40d.In other words, list is only had in each composite construction
One storage unit is operated.It influences each other in this way, can avoid neighbouring storage unit, and then improves memory element
Second effect.
Figure 22 A to Figure 22 B is the signal that reverse read operation is carried out according to the memory element of the memory array structure of Figure 16
Figure.It is upper and the next that Figure 22 A, 22B respectively indicate reading.
Referring to Figure 16, Figure 22 A and Figure 22 B, the drain electrode of semiconductor fin structure 40a is, for example, and bit line BL1's
Bitline transistor BLT1Connection；Semiconductor fin structure 40c be, for example, and bit line BL1Bitline transistor BLT2Connection；Semiconductor
The drain electrode of fin structure 40b be, for example, and bit line BL3Bitline transistor BLT3Connection；Semiconductor fin structure 40d be, for example, with
Bit line BL3Bitline transistor BLT4Connection.Source electrode line SL, bit line BL1、BL2、BL3、BL4And bitline transistor BLT1、BLT2、
BLT3、BLT4Operation voltage it is as shown in Table 2 above.
Referring to table 2, Figure 22 A, Figure 22 B, reading upper operating condition is, for example, that will read bias to be applied to source
Extremely (source voltage Vs=1.6V) and gate terminal (grid voltage Vg=7V), and selected semiconductor fin structure 40a,
The drain electrode end of 40b is biased (drain voltage Vd=0V), to sense the charge in drain side junction.At this point, non-selected
The drain electrode of semiconductor fin structure 40c, 40d is floating state (F).When reading the next, as shown in Figure 22 B, operating condition example
Bias will be read in this way is applied to drain electrode end (drain voltage Vd=1.6V), to sense the charge on source side injection.It is worth
It is noted that will appear substantial carrier-free in the matrix of source electrode exhausts side (depletion when reading upper
Edge) (as shown in the dotted line in Figure 22 A)；It is then above-mentioned depletion region occur in the matrix close to drain electrode when reading the next.
Figure 23 A to Figure 23 B is to carry out channel hot electron implant operation according to the memory element of the memory array structure of Figure 16
Schematic diagram.It is upper and the next that Figure 23 A, 23B respectively indicate programming.Source electrode line SL, bit line BL1、BL2、BL3、BL4And bit line
Transistor BLT1、BLT2、BLT3、BLT4Operation voltage it is as shown in table 5.
Table 5
| BL1 | BL3 | BL2 | BL4 | BLT1 | BLT2 | BLT3 | BLT4 | SL | |
| It is upper | 4V | 0V | 0V | 4V | 9V | 0V | 9V | 0V | 0V |
| It is the next | 0V | V’ | V’ | 0V | 9V | 0V | 9V | 0V | 4V |
Referring to table 5 and Figure 23 A, programming upper operating condition is, for example, to apply grid voltage Vg=12V so that
Channel conductive, while applying source voltage Vs=0V and matrix voltage Vb=0V/F, and apply the drain voltage of intermediate level respectively
Vd=4V and 0V is to selected semiconductor fin structure 40a, 40b, to form the electric field from source electrode to drain electrode.Non-selected half
The drain electrode of conductor fin structure 40c, 40d are floating state (F).When the bias between source electrode and drain electrode is quite big, on channel
Excessive thermoelectron will be generated, the thermoelectron meeting injector grid of part is to be programmed.
When programming is the next, as shown in fig. 23b, operating condition is then the source voltage V for applying intermediate levels=4V, and
Apply drain voltage V respectivelyd=0V and Vd=V ' is formed to selected semiconductor fin structure 40a, 40b from drain electrode to source
The electric field of pole.It is worth noting that, above-mentioned V ' (unprogrammed bias) can be independent bias, can unrestricted choice V ' pressure difference.
However, as V ' it is excessively high when, another drain electrode (such as drain electrode of semiconductor fin structure 40a) in same composite construction 80a can be made
Generate leakage current；In contrast, it will cause programmings to interfere when V ' is too low.In one embodiment, V ' is, for example, between 1V to 2V
Between.In addition, when programming upper, drain voltage Vd=4V and 0V respectively indicate programming and it is unprogrammed；When programming the next, leakage
Pole tension Vd=0V and V ' respectively indicate programming and it is unprogrammed.
Figure 24 A to Figure 24 B is to wear to cause then to energy band according to the memory element progress energy band of the memory array structure of Figure 16
Hot hole implant operation schematic diagram.Figure 24 A, 24B respectively indicate erase it is upper and the next.Source electrode line SL, bit line BL1、BL2、
BL3、BL4And bitline transistor BLT1、BLT2、BLT3、BLT4Operation voltage it is as shown in table 6.
Table 6
| BL1 | BL3 | BL2 | BL4 | BLT1 | BLT2 | BLT3 | BLT4 | SL | |
| It is upper | 5V | 0V | 0V | 5V | 9V | 0V | 9V | 0V | 0V |
| It is the next | 0V | V” | V” | 0V | 9V | 0V | 9V | 0V | 5V |
Referring to table 6, Figure 24 A and Figure 24 B, upper operating condition of erasing is, for example, to apply grid voltage Vg=-
8V, while applying source voltage Vs=0V and matrix voltage Vb=0V/F, and apply drain voltage V respectivelyd=5V and 0V is to selected
Semiconductor fin structure 40a, 40b selected.Under these bias conditions, pass through energy band caused hot hole injection tunneling to energy band
It is upper to erase that charged carriers are injected into electric charge storage layer.Conversely, 4B referring to figure 2., erases the next operating condition then
To apply source voltage Vs=5V, and apply drain voltage V respectivelyd=0V and Vd=V " extremely selected semiconductor fin structure
40a,40b.It is worth noting that, above-mentioned V " (unprogrammed bias) can be independent bias.In one embodiment, V " is, for example, to be situated between
In 0V between 5V.In another embodiment, V " is, for example, 2.5V.
Significantly, since it is above-mentioned it is reverse read, channel hot electron injection and energy band is tunneling to energy band causes heat
The operation of hole injection is all memory array structure as shown in figure 16, i.e., two drain electrodes in each composite construction 80 are connected to
Different main bit line MBL.Therefore, two storage units in same composite construction can be operated simultaneously.Due to of the invention
There is dielectric layer between two storage units, thus can avoid neighbouring storage unit and interfere with each other, and then improve storage
The second effect of element.
Figure 25 A to Figure 25 B is the memory element operated according to FN electron injection depicted in the first embodiment of the present invention
Schematic diagram.Figure 26 A to Figure 26 B is the memory element according to the hole FN implant operation depicted in the first embodiment of the present invention
Schematic diagram.
5A referring to figure 2., the operation erased in a manner of+FN electron injection are, for example, to make electronics from semiconductor fin-shaped knot
Structure 40a, 40b, 40c, 40d are injected among the electric charge storage layer of side.Its operating condition is, for example, to apply grid voltage Vg=
10V, while applying drain voltage Vd=-10V, source voltage Vs=-10V, matrix voltage Vb=-10V or floating, in source electrode
Biggish electric field is formed between drain electrode and grid, so that the electronics in matrix and drain electrode can enter electricity by FN tunneling effect
Lotus storage layer, and then data of erasing.5B referring to figure 2., in contrast, the operation example erased in a manner of-FN electron injection
Such as electronics is made to be injected into electric charge storage layer from grid.Its operating condition is, for example, to apply grid voltage Vg=-10V applies simultaneously
Drain voltage Vd=10V, source voltage Vs=10V, matrix voltage Vb=10V or floating makes electronics be injected into charge storage from grid
Deposit layer.
6A referring to figure 2., the operation erased with the hole+FN injection mode are, for example, that hole is made to be injected into electricity from grid
Lotus storage layer.Its operating condition is, for example, to apply grid voltage Vg=10V, while applying drain voltage Vd=-10V, source voltage
Vs=-10V, matrix voltage Vb=-10V or floating, to form biggish electric field between source electrode and drain electrode and grid, so that grid
Hole in extremely can enter electric charge storage layer, and then data of erasing by FN tunneling effect.6B referring to figure 2., in contrast,
It is, for example, that hole is made to be injected into electric charge storage layer from matrix and drain electrode with the operation that the injection of the hole-FN is erased.It is operated
Condition is, for example, to apply grid voltage Vg=-10V, while applying drain voltage Vd=10V, source voltage Vs=10V, matrix electricity
Press Vb=10V or floating, so that the hole in matrix and drain electrode can enter charge storage region by FN tunneling effect, in turn
It erases data.
In addition, the injection of the above-mentioned hole FN and the operation of FN electron injection in addition to can be used for erasing memory data it
Outside, before carrying out above-mentioned programming or the operation erased to storage unit, as the start voltage (threshold of storage unit
Voltage, Vt) because process variation or other factors are not reached and are taken, it can be adjusted using the method for the hole FN or electron injection
Start voltage, to meet required target value.In one embodiment, start voltage can be promoted by the method for FN electron injection.
In another embodiment, start voltage can be reduced by the method that the hole FN is injected.
In conclusion memory element provided by the invention includes composite construction.In composite construction, dielectric layer is located at two
Between semiconductor fin structure, so that the electric charge storage layer of covering composite construction is located at the side of each semiconductor fin structure.
In this way, which two storage units that can avoid in same composite construction interfere with each other in operation, rectilinear deposit is greatly improved
The second effect of element is stored up, and maintains original operation efficiency.Furthermore the source electrode in each semiconductor fin structure is electric each other
Property connection, keep the connection between the inside of rectilinear memory element more easy, and then the technique of the rectilinear memory element of simplification
Step.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle those of ordinary skill, without departing from the spirit and scope of the present invention, when the change and modification that can make part, thus it is of the invention
Protection scope is subject to view as defined in claim.
Claims (10)
1. a kind of memory element characterized by comprising
One substrate；
One first doped region is located at the substrate surface；
Multiple composite constructions are located on first doped region, and each composite construction includes:
Two semiconductor fin structures, each semiconductor fin structure include one second doped region, are located at each semiconductor fin-shaped
The top of structure；And a matrix area, between second doped region and first doped region；And
One dielectric layer, between those semiconductor fin structures；
Multiple wordline are located in the substrate, and each wordline covers the partial sidewall and atop part of each composite construction；And
One electric charge storage layer, between those composite constructions and those wordline.
2. memory element according to claim 1, wherein the electric charge storage layer is located at the one of each semiconductor fin structure
Side.
3. memory element according to claim 1, wherein first doped region more extends to each semiconductor fin structure.
4. memory element according to claim 1, which is characterized in that further include:
Multiple first contact holes, in a first part of the substrate, every one first contact hole is electrically connected corresponding be somebody's turn to do
Second doped region；And
Multiple second contact holes, on a second part of the substrate, every one second contact hole is electrically connected first doping
Area.
5. memory element according to claim 1, in which:
In a first part of the substrate have a channel, the channel extends along a second direction and expose partially those
Matrix area；And
One third contact hole is located in the channel, which is electrically connected those matrixes of the exposed part of the channel
Area.
6. a kind of manufacturing method of memory element characterized by comprising
One substrate is provided；
Multiple composite constructions are formed, in the substrate, each composite construction includes two semiconductor fin structures and a dielectric layer,
The dielectric layer is located between those semiconductor fin structures, wherein each semiconductor fin structure include one second doped region and
One matrix area；
One first doped region is formed, in the substrate surface, which connects each semiconductor fin structure；
Multiple wordline are formed, in the substrate, each wordline covers the partial sidewall and atop part of each composite construction；And
An electric charge storage layer is formed, between those composite constructions and those wordline.
7. the manufacturing method of memory element according to claim 6, wherein the method for forming those composite constructions includes:
Those semiconductor fin structures are formed on this substrate；
Those dielectric layers are formed on this substrate；And
Those dielectric layers of part are removed, to form those composite constructions.
8. the manufacturing method of memory element according to claim 7, wherein the method for removing those dielectric layers of part includes:
Form a patterned mask layer, those dielectric layers of covering part and those semiconductor fin structures of part；And
Remove those dielectric layers not covered by the patterned mask layer.
9. the manufacturing method of memory element according to claim 7, wherein the method for forming those semiconductor fin structures
Include:
A doped layer is formed on this substrate；And
The doped layer and the substrate are patterned, to form those semiconductor fin structures.
10. the manufacturing method of memory element according to claim 6, which is characterized in that further include:
Multiple first contact holes are formed, in a first part of the substrate, every one first contact hole is electrically connected corresponding
Second doped region；And
Multiple second contact holes are formed, on a second part of the substrate, every one second contact hole is electrically connected this and first mixes
Miscellaneous area.
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