TWI590253B - Non-volatile memory - Google Patents

Description

Non-volatile memory

This invention relates to a semiconductor component, and more particularly to a non-volatile memory.

Non-volatile memory has been widely used in personal computers and electronic devices because it has the advantages of allowing data to be stored, read, erased, etc., and the stored data does not disappear after power-off.

A typical non-volatile memory is designed to have a stacked gate-Gate structure including a tunneling oxide layer, a floating gate, and a gate dielectric layer sequentially disposed on the substrate. And control gate (Control Gate). When programming or erasing the flash memory device, apply appropriate voltages to the source region, the drain region, and the control gate to inject electrons into the polysilicon floating gate or to remove electrons from the polysilicon. Pull out in the floating gate.

In the operation of non-volatile memory, the larger the Gate-Coupling Ratio (GCR) between the floating gate and the control gate, the lower the operating voltage required for its operation will be. Flash memory operation speed and efficiency will be greatly Upgrade. The method for increasing the gate coupling ratio includes increasing the overlap area between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the floating The dielectric constant (Dielectric Constant; k) of the dielectric layer between the gate and the control gate.

However, as integrated circuits are moving toward miniaturized components with higher degree of accumulation, it is necessary to reduce the memory cell size of non-volatile memory to increase its accumulation. Wherein, reducing the size of the memory cell can be achieved by reducing the gate length of the memory cell and the spacing of the bit lines. However, the smaller the gate length shortens the channel length under the tunneling oxide layer, which is likely to cause abnormal electrical penetration between the drain and the source, which will seriously affect the memory cell. Electrical performance. Moreover, when the memory cells are programmed and erased, the electrons repeatedly traverse the tunnel oxide layer, which will wear out the tunnel oxide layer, resulting in a decrease in the reliability of the memory device.

The present invention provides a non-volatile memory and a method of fabricating the same that can operate at a low operating voltage, thereby increasing the reliability of the semiconductor component.

The present invention provides a non-volatile memory and a method of manufacturing the same, which can improve the degree of integration of components.

The present invention provides a non-volatile memory having a first memory unit disposed on a substrate having a deep well region. The first memory unit includes: a stacked structure, a first floating gate and a second floating gate, a first tunneling dielectric layer and a second tunneling dielectric layer, a first erase dielectric layer and a second Wiping off dielectric layer, first auxiliary gate dielectric layer and The second auxiliary gate dielectric layer, the first doped region and the second doped region, the first control gate and the second control gate, and the inter-gate dielectric layer. The stacked structure includes a gate dielectric layer, a gate, and an insulating layer sequentially disposed on the substrate. The first floating gate and the second floating gate are respectively disposed on sidewalls of the two sides of the stacked structure, and the tops of the first floating gate and the second floating gate respectively have corner portions. The first tunneling dielectric layer and the second tunneling dielectric layer are respectively disposed between the first floating gate and the substrate and between the second floating gate and the substrate. The first erase dielectric layer and the second erase dielectric layer are respectively disposed between the gate and the first floating gate and between the gate and the second floating gate, and the first erase dielectric layer and The second erase dielectric layer respectively includes a first portion and a second portion on the first portion, wherein the second portion has a thickness less than or equal to the first portion, and the corner portion is adjacent to the second portion. The first doped region and the second doped region are respectively disposed in the substrate, wherein the first floating gate, the stacked structure and the second floating gate are connected to the first doped region and the second doped region On the base. The first control gate and the second control gate are respectively disposed on the first floating gate and the second floating gate. The inter-gate dielectric layer is disposed between the first control gate and the first floating gate and between the second control gate and the second floating gate.

In an embodiment of the invention, the non-volatile memory has a first bit line and a second bit line. The first bit line is electrically connected to the second bit line in parallel with the second bit line, wherein the first doped region is electrically connected to the first bit line, and the second doped region is electrically connected to the second bit line.

In an embodiment of the invention, the non-volatile memory further includes a second memory unit in the row direction, and the second memory unit is disposed on the substrate, the second memory The structure of the unit is the same as that of the first memory unit, sharing the second doped region.

In an embodiment of the invention, the non-volatile memory has a first bit line and a second bit line. The first bit line and the second bit line are disposed on the substrate in parallel, wherein the second doping region shared by the first memory unit and the second memory unit is electrically connected to the first bit line, and the first memory unit is A doped region and a third doped region of the second memory cell are electrically connected to the second bit line, respectively.

In an embodiment of the invention, the first memory unit and the second memory unit share the first control gate or the second control gate, and the first control gate or the second control gate fills the first memory unit. An opening between the second memory unit.

In an embodiment of the invention, the non-volatile memory further includes a third memory unit in the column direction, the third memory unit is disposed on the substrate, and the structure of the third memory unit is the same as the structure of the first memory unit. The third memory unit and the first memory unit are serially connected by the first doping region, sharing the gate, the first control gate and the second control gate, and the first control gate and the second control gate are filled Between the first memory unit and the third memory unit.

In an embodiment of the invention, the non-volatile memory has a first bit line, a second bit line, and a third bit line. The first bit line, the second bit line and the third bit line are disposed in parallel on the substrate, wherein the first doping region connected in series with the first memory unit and the third memory unit is electrically connected to the second bit The second doped region of the first memory unit is electrically connected to the first bit line, and the third doped region of the third memory cell is electrically connected to the third bit line.

In an embodiment of the invention, the first tunneling dielectric layer is further disposed on The first control gate is disposed between the first control gate and the first doped region; and the second tunneling dielectric layer is disposed between the second control gate and the second doped region.

In an embodiment of the invention, the height of the first portion of the first erase dielectric layer and the second erase dielectric layer is 0.8 times to less than the height of the first floating gate and the second floating gate 1 times.

In an embodiment of the invention, the material of the first portion of the first erase dielectric layer and the second erase dielectric layer comprises hafnium oxide/tantalum nitride, hafnium oxide/tantalum nitride/yttria or hafnium oxide. .

In an embodiment of the invention, the material of the insulating layer comprises yttrium oxide.

In an embodiment of the invention, the material of the inter-gate dielectric layer comprises yttrium oxide/tantalum nitride/yttria or tantalum nitride/yttria or other high dielectric constant material (k>4).

In an embodiment of the invention, the material of the first tunneling dielectric layer and the second tunneling dielectric layer comprises yttrium oxide, and the thickness of the first tunneling dielectric layer and the second tunneling dielectric layer is between Between 60 and 200 angstroms.

In an embodiment of the invention, the material of the gate dielectric layer comprises hafnium oxide, and the thickness of the gate dielectric layer is less than or equal to the thickness of the first tunneling dielectric layer and the second tunneling dielectric layer.

In an embodiment of the invention, the material of the second portion of the first erase dielectric layer and the second erase dielectric layer comprises ruthenium oxide, and the thickness of the second portion is between 100 angstroms and 180 angstroms.

In an embodiment of the invention, the angle of the corner portion is less than or equal to 90 degree.

In an embodiment of the invention, the angle of the corner portion is less than or equal to 90 degrees. The threshold voltage of the first memory cell after stylization is between Vcc and 0: the threshold voltage after the erase of the first memory cell is less than zero.

In the non-volatile memory of the present invention, the two memory cells adjacent in the X direction (row direction) have the same structure and share the first doped region or the second doped region. The two memory cells adjacent in the Y direction (column direction) have the same structure, sharing the first doped region or the second doped region, the gate (word line), and the control gate. Therefore, the degree of integration of components can be improved.

In the non-volatile memory of the present invention, the thickness of the gate dielectric layer under the gate is relatively thin, and when the memory unit is operated, a smaller voltage can be used to open/close the channel region under the gate, that is, the operation can be reduced. Voltage.

In the non-volatile memory of the present invention, the control gate covers the floating gate, which can increase the area sandwiched between the control gate and the floating gate, and improve the coupling ratio of the memory element.

In the non-volatile memory of the present invention, since the height of the first portion of the erase dielectric layer is 0.8 times to less than 1 times the height of the floating gate, the floating gate is provided with a corner portion, and the corner portion is When the angle is less than or equal to 90 degrees, the electric field is concentrated by the corner portion, the erase voltage can be reduced, and the electrons can be efficiently pulled out from the floating gate to increase the speed of erasing the data.

The non-volatile memory of the present invention, due to the first floating gate, stacked There is no gap between the structure and the second floating gate, so the accumulation of memory cells can be improved. Moreover, the first floating gate and the second floating gate can store the electric charge, so that the two-bit data can be stored in a single memory unit, and the storage capacity can be improved.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Base

102‧‧‧Isolation structure

104‧‧‧Active Area

120‧‧‧Stack structure

122‧‧‧gate dielectric layer

124‧‧‧ gate

126‧‧‧Insulation

128, DW‧‧‧Shenjing District

118a, 118b‧‧‧wipe the dielectric layer

130a, 130b‧‧‧ part one

132a, 132b‧‧‧ part two

140a, 140b, FGa, FGb‧‧‧ floating Gate

141‧‧‧ Corner

142a, 142b‧‧‧ tunneling dielectric layer

146, 148‧‧‧ doped area

150a, 150b‧‧‧ control gate

152‧‧‧Interruptor dielectric layer

162‧‧‧ plug

164‧‧‧ openings

BL0~BL3‧‧‧ bit line

CG0~CG5‧‧‧Control gate line

M, M11~M33‧‧‧ memory unit

WL0~WL2‧‧‧ character line

1A is a top view of a non-volatile memory in accordance with an embodiment of the present invention.

FIG. 1B is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention.

FIG. 1C is a schematic circuit diagram of a non-volatile memory according to an embodiment of the invention.

2A and 2B are schematic diagrams showing an example of a program operation of a memory unit.

2C and 2D are schematic views showing an example of erasing a memory cell.

2E and 2F are schematic diagrams showing an example of a reading operation on a memory cell.

FIG. 3A illustrates a non-volatile memory according to an embodiment of the invention. Upper view.

FIG. 3B is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention.

FIG. 3C is a schematic circuit diagram of a non-volatile memory according to an embodiment of the invention.

4A and 4B are schematic diagrams showing an example of a program operation of a memory unit.

4C and 4D are schematic views showing an example of an erase operation of a memory cell.

4E and 4F are schematic diagrams showing an example of a reading operation on a memory cell.

1A is a top view of a non-volatile memory in accordance with an embodiment of the present invention. FIG. 1B is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention. FIG. 1B is a cross-sectional view taken along line AA' of FIG. 1A. FIG. 1C is a schematic circuit diagram of a non-volatile memory according to an embodiment of the invention.

1A, 1B, and 1C, the non-volatile memory includes a plurality of memory cells M11 to M33, word lines WL0 to WL2, bit lines BL0 to BL3, and control gate lines CG0 to CG5. The memory cells M11 to M33 are arranged in a row/column array.

The non-volatile memory is disposed on the substrate 100. In the substrate 100, for example An isolation structure 102 is provided to define the active area 104. The isolation structure 102 is, for example, a shallow trench isolation structure. There is a deep well region 128 in the substrate 100. The deep well region 128 is, for example, a doped region containing an N-type or P-type dopant, depending on the design of the terminal element.

As shown in FIG. 1A, the memory cell M includes a stacked structure 120, an erase dielectric layer 118a (118b), a floating gate 140a (140b), a tunneling dielectric layer 142a (142b), a doped region 146, and doping. A region 148, a control gate 150a (150b), and a gate dielectric layer 152.

The stacked structure 120 sequentially passes through the gate dielectric layer 122, the gate 124, and the insulating layer 126 from the substrate 100. The gate dielectric layer 122 is disposed between the gate 124 and the substrate 100, for example. The material of the gate dielectric layer 122 is, for example, hafnium oxide. The thickness of the gate dielectric layer 122 is, for example, less than or equal to the thickness of the tunnel dielectric layer 142.

The gate 124 is disposed between the gate dielectric layer 122 and the insulating layer 126, for example. The gate 124 extends, for example, in the Y direction. The material of the gate 124 is, for example, a conductor material such as doped polysilicon. The insulating layer 126 is provided, for example, on the gate 124. The material of the insulating layer 126 is, for example, cerium oxide.

The erase dielectric layer 118a (118b) is disposed, for example, between the floating gate 140a (140b) and the gate 124. The erase dielectric layer 118a (118b) includes a first portion 130a (130b) and a second portion 132a (132b) on the first portion 130a (130b). The thickness of the second portion 132a (132b) is less than or equal to the first portion 130a (130b). The material of the first portion 130a (130b) of the erase dielectric layer 118a (118b) is, for example, hafnium oxide/tantalum nitride/yttria or tantalum nitride/yttria or hafnium oxide. The material of the second portion 132a (132b) of the erase dielectric layer 118a (118b) is, for example, ruthenium oxide. The thickness of the second portion 132a (132b) of the erase dielectric layer 118a (118b) is, for example, between 100 angstroms and 180 angstroms.

The floating gate 140a and the floating gate 140b are, for example, sidewalls disposed on both sides of the stacked structure 120, and the tops of the floating gate 140a and the floating gate 140b respectively have corner portions 141. The height of the first portion 130a (130b) of the erase dielectric layer 118a (118b) is 0.8 times to less than 1 times the height of the floating gate 140a (140b). This corner portion 141 is adjacent to the second portion 132a (132b) of the erase dielectric layer 118a (118b). The angle of the corner portion 141 is less than or equal to 90 degrees. The material of the floating gate 140a and the floating gate 140b is, for example, a conductor material such as doped polysilicon. The floating gate 140a and the floating gate 140b may each be composed of one or more conductor layers.

The tunneling dielectric layer 142a is disposed between the floating gate 140a and the substrate 100, for example, and the tunneling dielectric layer 142b is disposed between the floating gate 140b and the substrate 100, for example. The tunneling dielectric layer 142a is disposed, for example, between the control gate 150a and the doping region 146; the tunneling dielectric layer 142b is disposed, for example, between the control gate 150b and the doping region 148. The material of the tunneling dielectric layer 142a and the tunneling dielectric layer 142b is, for example, hafnium oxide. The thickness of the tunneling dielectric layer 142a and the tunneling dielectric layer 142b is between 60 angstroms and 200 angstroms.

The doped region 146 is, for example, disposed in the substrate 100 beside the floating gate 140a. The doped region 148 is, for example, disposed in the substrate 100 beside the floating gate 140b. The floating gate 140a, the stacked structure 120 and the floating gate 140b are connected to the substrate 100 disposed between the doping region 146 and the doping region 148. The doped region 146 and the doped region 148 are, for example, doped regions containing N-type or P-type dopants, depending on the design of the device.

The control gate 150a is, for example, disposed on the floating gate 140a; the control gate The pole 150b is, for example, disposed on the floating gate 140b. The control gate 150a and the control gate 150b extend, for example, in the Y direction (column direction). The material of the control gate 150a and the control gate 150b is, for example, a conductor material such as doped polysilicon. The inter-gate dielectric layer 152 is disposed, for example, between the control gate 150a and the floating gate 140a and between the control gate 150b and the floating gate 140b. The material of the inter-gate dielectric layer 152 is, for example, tantalum oxide/tantalum nitride/yttria or tantalum nitride/yttria or other high dielectric constant material (k>4).

An interlayer insulating layer (not shown) is disposed on the substrate 100, for example, and covers the memory unit M. The material of the interlayer insulating layer is, for example, cerium oxide, phosphoric glass, borophosphon glass or other suitable dielectric material. The plurality of plugs 162 are, for example, disposed in the interlayer insulating layer. The material of the plug 162 is, for example, a conductor material such as aluminum or tungsten. The plurality of bit lines BL0 BLBL3 are disposed on the interlayer insulating layer, for example, and the bit lines BL0 BLBL3 are electrically connected to the doping regions 146 or the doping regions 148 of the memory cells M by the plugs 162, respectively. The material of the bit lines BL0 to BL3 is, for example, a conductor material such as aluminum, tungsten or copper. As shown in FIG. 1C, the memory cells M11 to M33 have a structure as shown in FIGS. 1A and 1B. In the following description, the memory unit M in FIG. 1B is divided into a left bit and a right bit.

In the X direction (row direction), a plurality of memory cells M are connected in series by doped regions (doped regions 146 or doped regions 148). For example, the structure of the memory cell M11 is the same as that of the memory cell M12, sharing a doped region (doped region 146 or doped region 148); the structure of the memory cell M12 is the same as that of the memory cell M13, sharing a blend The impurity region (doped region 146 or doped region 148);...; the memory cell M31 has the same structure as the memory cell M32, sharing a doped region (doped region 146 or doped The impurity cell 148) has the same structure as the memory cell M33 and shares a doped region (doped region 146 or doped region 148).

In the Y direction (column direction), a plurality of memory cells M are connected in series by doped regions (doped regions 146 or doped regions 148), and the common gate 124, the control gate 150a, and the control gate 150b are shared. . The control gate 150a and the control gate 150b fill between the memory unit M (for example, the memory unit M11, the memory unit M21, and the memory unit M31). For example, the structure of the memory cell M11 is the same as that of the memory cell M21, sharing a doped region (doped region 146 or doped region 148). The structure of the memory cell M21 is the same as the structure of the memory cell M31. a region (doped region 146 or doped region 148);...; memory cell M13 has the same structure as memory cell M23, sharing a doped region (doped region 146 or doped region 148), memory cell M23 The structure shares the same doping region (doped region 146 or doped region 148) as the memory cell M33.

The bit lines BL0 to BL3 are respectively disposed on the substrate, and the bit lines BL0 to BL3 are arranged in parallel in the row direction. A memory cell row is disposed in two adjacent bit lines, and the doped regions included in the memory cell row are respectively connected to two adjacent bit lines corresponding thereto (doped regions 146). Or doped region 148). For example, the memory unit M11, the memory unit M12, and the memory unit M13 are connected in series to form a memory cell row. The first and third doped regions are electrically connected to the bit line BL0, starting from the memory unit M11. The four doped regions are electrically connected to the bit line BL1. The memory unit M21, the memory unit M22, and the memory unit M23 are connected in series to form a memory cell row, and the first and third doped regions are electrically connected to the bit line BL2, and the second and fourth doped regions are electrically connected. Connect to the 3rd bit line BL1. The memory unit M31, the memory unit M32, and the memory unit M33 are connected in series to form a memory cell row, the first and third doped regions are electrically connected to the bit line BL2, and the second and fourth doped regions are electrically connected to the third row. Strip bit line BL3.

Moreover, in the row direction, for example, the doped regions shared by the memory cells M11 and the memory cells M12 connected in series are electrically connected to the bit line BL1, and the doped regions not shared by the memory cell M11 and the memory cell M12 are respectively electrically connected. Connected to bit line BL0. In the column direction, for example, the doped regions shared by the memory cells M11 and the memory cells M21 connected in series are electrically connected to the bit line BL1, and the other doped region of the memory cell M11 is electrically connected to the bit line BL0. The other doped region of the memory cell M21 is electrically connected to the bit line BL2.

The word lines WL0 to WL2 are respectively disposed on the substrate, and the word lines WL0 to WL2 are arranged in parallel in the column direction, and are respectively connected to the gates 124 of the memory cells of the same column. For example, the word line WL0 is connected to the gate 124 of the memory cells M11 to M31. The word line WL1 is connected to the gate 124 of the memory cells M12 to M32. The word line WL2 is connected to the gate 124 of the memory cells M13 to M33.

The control gate lines CG0 CG CG5 are respectively disposed on the substrate, and the control gate lines CG0 CG CG5 are arranged in parallel in the column direction, and respectively connected to the control gate 150a or the control gate 150b of the memory cell of the same column. In the present embodiment, the control gate lines CG0, CG2, CG4 are connected to the control gates 150a of the memory cells of the same column. The control gate lines CG1, CG3, CG5 are connected to the control gates 150b of the memory cells of the same column.

In the above non-volatile memory, the two memory cells M adjacent in the X direction (row direction) have the same structure, sharing the first doping region 146 or the second doping region 148. The two memory cells M adjacent in the Y direction (column direction) have the same structure, sharing the first doping region 146 or the second doping region 148, the gate (word line) 124, and the control gate 150a (150b). Therefore, the degree of integration of components can be improved. In the above non-volatile memory, the thickness of the gate dielectric layer 122 is relatively thin. When the memory cell is operated, a smaller voltage can be used to open/close the channel region under the gate 124, that is, the operating voltage can be lowered. The control gate 150a (150b) covers the floating gate 140a (140b), and can increase the area sandwiched between the control gate 150a (150b) and the floating gate 140a (140b), thereby improving the memory component. Coupling rate. The height of the first portion 130a (130b) of the erase dielectric layer 118a (118b) is 0.8 times to less than 1 times the height of the floating gate 140a (140b). The floating gate 140a (140b) is provided with a corner portion 141, and the angle of the corner portion 141 is less than or equal to 90 degrees, and the electric field is concentrated by the corner portion 141, thereby reducing the erasing voltage and efficiently discharging electrons from the floating gate The pole 140a (140b) is pulled out to increase the speed of erasing the data. Moreover, the corner portion 141 is adjacent to the second portion 132a (132b) of the erase dielectric layer 118a (118b), and the thin portion of the second portion 132a (132b) of the erase dielectric layer 118a (118b) can also be improved. In addition to the rate.

In the non-volatile memory of the present invention, since there is no gap between the floating gate 140a, the stacked structure 120 and the floating gate 140b, the degree of accumulation of the memory cells can be improved. Moreover, the charge can be stored in both the floating gate 140a and the floating gate 140b, so that the data of the two bits can be stored in a single memory unit, and the storage capacity can be improved.

Next, the operation mode of the non-volatile memory of the present invention will be described, including operation modes such as stylization, erasing, and data reading. Figure 2A and Figure 2B show the memory list A schematic diagram of an instance of a stylized operation. 2C and 2D are schematic views showing an example of erasing a memory cell. 2E and 2F are schematic diagrams showing an example of a reading operation on a memory cell.

Referring to FIG. 2A, when the floating gate FGa (left bit) of the selected memory cell M22 is programmed, a voltage Vcc is applied to the deep well region DW, and the voltage Vcc is, for example, a power supply voltage. A voltage of 0 volts is applied to the substrate sub. A voltage Vwlp is applied to the gate (word line WL1) of the selected memory cell M22 to form a channel in the substrate under the gate, and the voltage Vwlp is, for example, 0.6 to 1.2 volts. The gate of the unselected memory cell (word lines WL0, WL2) applies a voltage of 0 volts. Applying a voltage Vblp to the doped region (bit line BL1) of the selected memory cell M22; applying a voltage Vbli to the doped region (bit line BL2); applying a voltage Vcgp to the control gate (control gate line CG2); The pole (control gate line CG3) applies a voltage Vcc. The voltage Vblp is, for example, 3 to 7 volts; the voltage Vbli is, for example, 0.3 to 0.8 volts; and the voltage Vcgp is, for example, 5 to 9 volts. Under such a bias voltage, electrons are moved from the drain (bit line BL2) to the source (bit line BL1), and the floating gate FGa of the selected memory cell M22 is injected in the mode of source-side hot electron injection. (left bit). Since the gate of the unselected memory cell (word lines WL0, WL2) is applied with a voltage of 0 volts, the channel region cannot be formed, and electrons cannot be injected into the floating gate of the unselected memory cell, so the unselected memory cells are not programmed. .

Referring to FIG. 2B, when the floating gate FGb (right bit) of the selected memory cell M22 is programmed, a voltage Vcc is applied to the deep well region DW, and the voltage Vcc is, for example, a power supply voltage. A voltage of 0 volts is applied to the substrate sub. Applying a voltage Vwlp to the gate (word line WL1) of the selected memory cell M22 for the substrate under the gate The channel is formed in the middle, and the voltage Vwlp is, for example, 0.6 to 1.2 volts. The gate of the unselected memory cell (word lines WL0, WL2) applies a voltage of 0 volts. Applying a voltage Vblp to the doped region (bit line BL2) of the selected memory cell M22; applying a voltage Vbli to the doped region (bit line BL1); applying a voltage Vcgp to the control gate (control gate line CG3); The pole (control gate line CG2) applies a voltage Vcc. The voltage Vblp is, for example, 3 to 7 volts; the voltage Vbli is, for example, 0.3 to 0.8 volts; the voltage Vcgp is, for example, 5 to 9 volts; and the voltage Vegp is, for example, 3 to 7 volts. Under such a bias voltage, electrons are moved from the drain (bit line BL1) to the source (bit line BL2), and the floating gate FGb of the selected memory cell M22 is injected in the source-side hot electron injection mode. (right bit). Since the gate of the unselected memory cell (word lines WL0, WL2) is applied with a voltage of 0 volts, the channel region cannot be formed, and electrons cannot be injected into the floating gate of the unselected memory cell, so the unselected memory cells are not programmed. .

Referring to FIG. 2C, when the floating gate FGa (left bit) of the selected memory cell M22 is erased, a voltage Vcge is applied to the control gate (control gate line CG2) of the selected memory cell M22; The control gate of the memory unit M22 (control gate line CG3) applies a voltage of 0 volts. Applying a voltage of 2 times Vcc to the gate (word line WL1) of the selected memory cell M22; applying a voltage of 0 volt to the gate of the unselected memory cell (word lines WL0, WL2); in the doped region (bit) The voltage of Vcc is applied to the line BL1), the doped region (bit line BL2), the deep well region DW, and the substrate sub. The voltage Vcge is, for example, -8 to 0 volts. The voltage Vcc is, for example, a power supply voltage. Using the voltage difference between the control gate (control gate line CG2) and the gate (word line WL1), the FN tunneling effect is induced, and the floating gate FGa (left bit) stored in the memory unit is electronically pulled out and shift except.

Referring to FIG. 2D, when the floating gate FGb (right bit) of the selected memory cell M22 is erased, a voltage Vcge is applied to the control gate (control gate line CG3) of the selected memory cell M22; The control gate of the memory unit M22 (control gate line CG2) applies a voltage of 0 volts; the gate of the selected memory cell M22 (word line WL1) applies a voltage of 2 times Vcc; the gate of the unselected memory cell ( The word lines WL0, WL2) apply a voltage of 0 volts; a voltage of Vcc is applied to the doped region (bit line BL1), the doped region (bit line BL2), the deep well region DW, and the substrate sub. The voltage Vcge is, for example, -8 to 0 volts. The voltage Vcc is, for example, a power supply voltage. Using the voltage difference between the control gate (control gate line CG3) and the gate (word line WL1), the FN tunneling effect is induced, and the floating gate FGb (right bit) stored in the memory unit is electronically pulled out and Remove.

Referring to FIG. 2E, during the read operation, a voltage Vcc is applied to the deep well region DW, and a voltage of 0 volts is applied to the substrate sub; a voltage Vcc is applied to the gate of the selected memory cell M22 (the word line WL1); The control gate of the unit M22 (control gate line CG2) applies a voltage of 0 volts, applies a voltage Vcc to the control gate (control gate line CG3), and applies to the doped region (bit line BL2) of the selected memory cell M22. Voltage Vcc; the doped region (bit line BL1) applies a voltage of 0 volts. Among them, the voltage Vcc is, for example, a power supply voltage. In the case of the above bias voltage, the digital information stored in the floating gate FGa (left bit) of the memory unit can be determined by detecting the channel current of the memory unit.

Please refer to FIG. 2F, when the read operation is performed, the power is applied to the deep well DW. Pressing Vcc, applying a voltage of 0 volts to the substrate sub; applying a voltage Vcc to the gate of the selected memory cell M22 (word line WL1); applying 0 volts to the control gate of the selected memory cell M22 (control gate line CG3) Voltage, a voltage Vcc is applied to the control gate (control gate line CG2); a voltage Vcc is applied to the doped region (bit line BL1) of the selected memory cell M22; and a voltage of 0 volt is applied to the doped region (bit line BL2) . Among them, the voltage Vcc is, for example, a power supply voltage. In the case of the above bias voltage, the digital information stored in the floating gate FGb (right bit) of the memory unit can be determined by detecting the channel current of the memory unit.

In the method for operating a non-volatile memory of the present invention, when a stylizing operation is performed, a low voltage is applied to the gate, so that a channel can be formed in the substrate under the gate, and a source-side hot electron injection mode is adopted. Write electrons to the floating gate. When the erase operation is performed, the gate is used to erase the data, and the electrons are removed through the erase dielectric layer, thereby reducing the number of times the electrons pass through the tunnel dielectric layer, thereby improving reliability. In addition, the height of the first portion of the erase dielectric layer is 0.8 times to less than 1 times the height of the floating gate, and the floating gate is provided with a corner portion, and the angle of the corner portion is less than or equal to 90 degrees. The corner portion concentrates the electric field and efficiently pulls electrons out of the floating gate, increasing the speed at which data is erased. The threshold voltage of the memory unit of the present invention is between Vcc and 0: the threshold voltage after the memory cell is erased is less than zero.

3A is a top view of a non-volatile memory in accordance with another embodiment of the present invention. FIG. 3B is a schematic cross-sectional view of a non-volatile memory according to another embodiment of the invention. 3B is a cross-sectional view taken along line AA' of FIG. 3A. FIG. 3C is a non-swing according to an embodiment of the invention. A schematic diagram of the circuit of the memory. In FIGS. 3A to 3C, the same components as those in FIGS. 1A to 1C are denoted by the same reference numerals, and detailed description thereof will be omitted.

Referring to FIGS. 3A, 3B, and 3C, the non-volatile memory includes a plurality of memory cells M11 to M33, word lines WL0 to WL2, bit lines BL0 to BL3, and control gate lines CG0 to CG3. The memory cells M11 to M33 are arranged in a row/column array.

The non-volatile memory is disposed on the substrate 100. An isolation structure 102 is provided, for example, in the substrate 100 to define the active region 104. The isolation structure 102 is, for example, a shallow trench isolation structure.

As shown in FIG. 3A, the memory unit M includes a stacked structure 120, an auxiliary gate dielectric layer 130a (130b), an erase dielectric layer 118a (118b), a floating gate 140a (140b), and a tunneling dielectric layer 142a ( 142b), doped region 146, doped region 148, control gate 150a (150b), and inter-gate dielectric layer 152.

The stacked structure 120 sequentially passes through the gate dielectric layer 122, the gate 124, and the insulating layer 126 from the substrate 100.

The erase dielectric layer 118a (118b) is disposed, for example, between the floating gate 140a (140b) and the gate 124. The erase dielectric layer 118a (118b) includes a first portion 130a (130b) and a second portion 132a (132b) on the first portion 130a (130b). The thickness of the second portion 132a (132b) is less than or equal to the first portion 130a (130b). The material of the first portion 130a (130b) of the erase dielectric layer 118a (118b) is, for example, hafnium oxide/tantalum nitride/yttria or tantalum nitride/yttria or hafnium oxide. The material of the second portion 132a (132b) of the erase dielectric layer 118a (118b) is, for example, ruthenium oxide. The thickness of the second portion 132a (132b) of the erase dielectric layer 118a (118b) is, for example, between 100 angstroms and 180 angstroms.

The floating gate 140a and the floating gate 140b are, for example, sidewalls disposed on both sides of the stacked structure 120, and the tops of the floating gate 140a and the floating gate 140b respectively have corner portions 141. The height of the first portion 130a (130b) of the erase dielectric layer 118a (118b) is 0.8 times to less than 1 times the height of the floating gate 140a (140b). This corner portion 141 is adjacent to the second portion 132a (132b) of the erase dielectric layer 118a (118b). The angle of the corner portion 141 is less than or equal to 90 degrees. The tunneling dielectric layer 142a is disposed between the floating gate 140a and the substrate 100, for example, and the tunneling dielectric layer 142b is disposed between the floating gate 140b and the substrate 100, for example. The tunneling dielectric layer 142a is disposed, for example, between the control gate 150a and the doping region 146. The tunneling dielectric layer 142b is disposed between the control gate 150b and the doping region 148, for example.

The doped region 146 is, for example, disposed in the substrate 100 beside the floating gate 140a. The doped region 148 is, for example, disposed in the substrate 100 beside the floating gate 140b. The floating gate 140a, the stacked structure 120 and the floating gate 140b are connected to the substrate 100 disposed between the doping region 146 and the doping region 148. The doped region 146 and the doped region 148 are, for example, doped regions containing N-type or P-type dopants, depending on the design of the device.

The control gate 150a and the control gate 150b are respectively disposed on the floating gate 140a and the floating gate 140b of the adjacent two memory cells. The control gate 150a and the control gate 150b extend, for example, in the Y direction (column direction). The adjacent two memory cells share the control gate 150a or the control gate 150b, and the control gate 150a and the control gate 150b respectively fill the openings between the adjacent two memory cells.

The inter-gate dielectric layer 152 is disposed, for example, between the control gate 150a and the floating gate 140a and between the control gate 150b and the floating gate 140b.

An interlayer insulating layer (not shown) is disposed on the substrate 100, for example, and covers the memory unit M. The plurality of plugs 162 are, for example, disposed in the interlayer insulating layer. The plurality of bit lines BL0 BLBL3 are disposed on the interlayer insulating layer, for example, and the bit lines BL0 BLBL3 are electrically connected to the doping regions 146 or the doping regions 148 of the memory cells M by the plugs 162, respectively. Referring to FIG. 3A, the opening 164 for forming the plug 162 extends through the interlayer insulating layer, the control gate 150a, and the control gate 150b until the doped region 146 and the doped region 148 are exposed. An insulating layer 166 is formed between the plug 162 and the control gate 150a and between the plug 162 and the control gate 150b. The material of the bit lines BL0 to BL3 is, for example, a conductor material such as aluminum, tungsten or copper.

As shown in FIG. 3C, the memory cells M11 to M33 have a structure as shown in FIGS. 3A and 3B. In the following description, the memory unit M in FIG. 1B is divided into a left bit a and a right bit b.

In the X direction (row direction), a plurality of memory cells M are connected in series by doped regions (doped regions 146 or doped regions 148), and adjacent memory cells M share control gates. For example, the memory cell M11 has the same structure as the memory cell M12, shares a doped region (doped region 146 or doped region 148), and shares a control gate (control gate 150a or control gate 150b). The memory cell M12 has the same structure as the memory cell M13, shares a doped region (doped region 146 or doped region 148), and shares a control gate (control gate 150a or control gate 150b); The memory cell M31 has the same structure as the memory cell M32, shares a doped region (doped region 146 or doped region 148), and shares a control gate (control gate 150a or control gate 150b). ); structure of memory unit M32 and structure of memory unit M33 Similarly, a doped region (doped region 146 or doped region 148) is shared and shares a control gate (control gate 150a or control gate 150b).

In the Y direction (column direction), a plurality of memory cells M are connected in series by doped regions (doped regions 146 or doped regions 148), and the common gate 124, the control gate 150a, and the control gate 150b are shared. . The control gate 150a and the control gate 150b fill between the memory unit M (for example, the memory unit M11, the memory unit M21, and the memory unit M31). For example, the structure of the memory cell M11 is the same as that of the memory cell M21, sharing a doped region (doped region 146 or doped region 148). The structure of the memory cell M21 is the same as the structure of the memory cell M31. a region (doped region 146 or doped region 148);...; memory cell M13 has the same structure as memory cell M23, sharing a doped region (doped region 146 or doped region 148), memory cell M23 The structure shares the same doping region (doped region 146 or doped region 148) as the memory cell M33.

The bit lines BL0 to BL3 are respectively disposed on the substrate, and the bit lines BL0 to BL3 are arranged in parallel in the row direction. A memory cell row is disposed in two adjacent bit lines, and the doped regions included in the memory cell row are respectively connected to two adjacent bit lines corresponding thereto (doped regions 146). Or doped region 148). For example, the memory unit M11, the memory unit M12, and the memory unit M13 are connected in series to form a memory cell row. The first and third doped regions are electrically connected to the bit line BL0, starting from the memory unit M11. The four doped regions are electrically connected to the bit line BL1. The memory unit M21, the memory unit M22, and the memory unit M23 are connected in series to form a memory cell row, and the first and third doped regions are electrically connected to the bit line BL2, and the second and fourth doped regions are electrically connected. Connect to the 3rd bit line BL1. The memory unit M31, the memory unit M32, and the memory unit M33 are connected in series to form a memory cell row, the first and third doped regions are electrically connected to the bit line BL2, and the second and fourth doped regions are electrically connected to the third row. Strip bit line BL3.

Moreover, in the row direction, for example, the doped regions shared by the memory cells M11 and the memory cells M12 connected in series are electrically connected to the bit line BL1, and the doped regions not shared by the memory cell M11 and the memory cell M12 are respectively electrically connected. Connected to bit line BL0. In the column direction, for example, the doped regions shared by the memory cells M11 and the memory cells M21 connected in series are electrically connected to the bit line BL1, and the other doped region of the memory cell M11 is electrically connected to the bit line BL0. The other doped region of the memory cell M21 is electrically connected to the bit line BL2.

The word lines WL0 to WL2 are respectively disposed on the substrate, and the word lines WL0 to WL2 are arranged in parallel in the column direction, and are respectively connected to the gates 124 of the memory cells of the same column. For example, the word line WL0 is connected to the gate 124 of the memory cells M11 to M31. The word line WL1 is connected to the gate 124 of the memory cells M12 to M32. The word line WL2 is connected to the gate 124 of the memory cells M13 to M33.

The control gate lines CG0 to CG3 are respectively disposed on the substrate, and the control gate lines CG0 to CG3 are arranged in parallel in the column direction to respectively connect the control gates 150a (150b) of the memory cells of the adjacent two columns. In this embodiment, the control gate line CG0 is connected to the control gate 150a (150b) on the left side of the memory cells M11, M21, M31; the control gate line CG1 is connected to the control gate 150a on the right side of the memory cells M11, M21, M31. (150b) and the control gate 150a (150b) on the left side of the memory cells M12, M22, M32; the control gate line CG2 is connected to the memory cells M12, M22, M32 Control gate 150a (150b) on the right side and control gate 150a (150b) on the left side of memory cells M13, M23, M33; control gate line CG3 is connected to control gate 150a (150b) on the right side of memory cells M13, M23, M33 ).

In the above non-volatile memory, the two memory cells M adjacent in the X direction (row direction) have the same structure, and the doped region 146 or the doped region 148 and the control gate 150a (150b) are shared. The two memory cells M adjacent in the Y direction (column direction) have the same structure, and share the doped region 146 or the doped region 148, the gate (word line) 124, and the control gate 150a (150b). Therefore, the degree of integration of components can be improved.

In the above non-volatile memory, the thickness of the gate dielectric layer 122 is relatively thin. When the memory cell is operated, a smaller voltage can be used to open/close the channel region under the gate 124, that is, the operating voltage can be lowered. The control gate 150a (150b) covers the floating gate 140a (140b), and can increase the area sandwiched between the control gate 150a (150b) and the floating gate 140a (140b), thereby improving the memory component. Coupling rate. The height of the first portion 130a (130b) of the erase dielectric layer 118a (118b) is 0.8 times to less than 1 times the height of the floating gate 140a (140b). Since the floating gate 140a (140b) is provided with the corner portion 141, and the angle of the corner portion 141 is less than or equal to 90 degrees, the electric field is concentrated by the corner portion 141, and the erasing voltage can be reduced to efficiently dissipate electrons from the floating portion. The gate 140a (140b) is pulled out to increase the speed at which the data is erased. Moreover, the corner portion 141 is adjacent to the second portion 132a (132b) of the erase dielectric layer 118a (118b), and the thin portion of the second portion 132a (132b) of the erase dielectric layer 118a (118b) can also be improved. In addition to the rate.

The non-volatile memory of the present invention is stacked on the floating gate 140a There is no gap between the structure 120 and the floating gate 140b, so that the degree of integration of the memory cells can be improved. Moreover, the charge can be stored in both the floating gate 140a and the floating gate 140b, so that the data of the two bits can be stored in a single memory unit, and the storage capacity can be improved.

Next, the operation mode of the non-volatile memory of the present invention will be described, including operation modes such as stylization, erasing, and data reading. 4A and 4B are schematic diagrams showing an example of a program operation of a memory unit. 4C and 4D are schematic views showing an example of an erase operation of a memory cell. 4E and 4F are schematic diagrams showing an example of a reading operation on a memory cell.

Referring to FIG. 4A, when the floating gate FGa (left bit) of the selected memory cell M22 is programmed, a voltage Vcc is applied to the deep well region DW, and the voltage Vcc is, for example, a power supply voltage. A voltage of 0 volts is applied to the substrate sub. A voltage Vwlp is applied to the gate (word line WL1) of the selected memory cell M22 to form a channel in the substrate under the gate, and the voltage Vwlp is, for example, 0.6 to 1.2 volts. The gate of the unselected memory cell (word lines WL0, WL2) applies a voltage of 0 volts. Applying a voltage Vblp to the doped region (bit line BL1) of the selected memory cell M22; applying a voltage Vbli to the doped region (bit line BL2); applying a voltage Vcgp to the control gate (control gate line CG1); The pole (control gate line CG2) applies a voltage Vcc. The voltage Vblp is, for example, 3 to 7 volts; the voltage Vbli is, for example, 0.3 to 0.8 volts; and the voltage Vcgp is, for example, 5 to 9 volts. Under such a bias voltage, electrons are moved from the drain (bit line BL2) to the source (bit line BL1), and the floating gate FGa of the selected memory cell M22 is injected in the mode of source-side hot electron injection. (left bit). Due to the gate of the unselected memory cell (word lines WL0, WL2) With a voltage of 0 volts, the channel region cannot be formed and electrons cannot be injected into the floating gate of the unselected memory cell, so the unselected memory cells are not programmed.

Referring to FIG. 4B, when the floating gate FGb (right bit) of the selected memory cell M22 is programmed, a voltage Vcc is applied to the deep well region DW, and the voltage Vcc is, for example, a power supply voltage. A voltage of 0 volts is applied to the substrate sub. A voltage Vwlp is applied to the gate (word line WL1) of the selected memory cell M22 to form a channel in the substrate under the gate, and the voltage Vwlp is, for example, 0.6 to 1.2 volts. The gate of the unselected memory cell (word lines WL0, WL2) applies a voltage of 0 volts. Applying a voltage Vblp to the doped region (bit line BL2) of the selected memory cell M22; applying a voltage Vbli to the doped region (bit line BL1); applying a voltage Vcgp to the control gate (control gate line CG2); The polarity (control gate line CG1) is applied with a voltage Vcc voltage Vblp of, for example, 3 to 7 volts; the voltage Vbli is, for example, 0.3 to 0.8 volts; and the voltage Vcgp is, for example, 5 to 9 volts. Under such a bias voltage, electrons are moved from the drain (bit line BL1) to the source (bit line BL2), and the floating gate FGb of the selected memory cell M22 is injected in the source-side hot electron injection mode. (right bit). Since the gate of the unselected memory cell (word lines WL0, WL2) is applied with a voltage of 0 volts, the channel region cannot be formed, and electrons cannot be injected into the floating gate of the unselected memory cell, so the unselected memory cells are not programmed. .

Referring to FIG. 4C, when the floating gate FGa (left bit) of the selected memory cell M22 is erased, a voltage Vcge is applied to the control gate (control gate line CG1) of the selected memory cell M22; The control gate of the memory unit M22 (control gate line CG2) applies a voltage of 0 volts; the gate of the selected memory cell M22 (word line WL1) applies a voltage of 2 times Vcc; the gate of the unselected memory cell ( Character Lines WL0, WL2) apply a voltage of 0 volts; a voltage of Vcc is applied to the doped region (bit line BL1), the doped region (bit line BL2), the deep well region DW, and the substrate sub. The voltage Vcge is, for example, -8 to 0 volts. Using the voltage difference between the control gate (control gate line CG1) and the gate (word line WL1), the FN tunneling effect is induced, and the floating gate FGa (left bit) stored in the memory unit is electronically pulled out and Remove.

Referring to FIG. 4D, when the floating gate FGb (right bit) of the selected memory cell M22 is erased, a voltage Vcge is applied to the control gate (control gate line CG2) of the selected memory cell M22; The control gate of the memory cell M22 (control gate line CG1) applies a voltage of 0 volts; the gate of the selected memory cell M22 (word line WL1) applies a voltage of 2 times Vcc; the gate of the unselected memory cell ( The word lines WL0, WL2) apply a voltage of 0 volts; a voltage of Vcc is applied to the doped region (bit line BL1), the doped region (bit line BL2), the deep well region DW, and the substrate sub. The voltage Vcge is, for example, -8 to 0 volts. Using the voltage difference between the control gate (control gate line CG2) and the gate (word line WL1), the FN tunneling effect is induced, and the floating gate FGb (right bit) stored in the memory unit is electronically pulled out and Remove.

Referring to FIG. 4E, during the read operation, a voltage Vcc is applied to the deep well region DW, and a voltage of 0 volts is applied to the substrate sub; a voltage Vcc is applied to the gate of the selected memory cell M22 (the word line WL1); The control gate of the unit M22 (control gate line CG1) applies a voltage of 0 volts, a voltage Vcc is applied to the control gate (control gate line CG2); and is applied to the doped region (bit line BL2) of the selected memory cell M22. Voltage Vcc; the doped region (bit line BL1) applies a voltage of 0 volts. Among them, the voltage Vcc is, for example, a power supply voltage. In the case of the above bias, by detecting the memory The channel current of the unit is used to determine the digital information stored in the floating gate FGa (left bit) of the memory unit.

Referring to FIG. 4F, when performing a read operation, a voltage Vcc is applied to the deep well region DW, and a voltage of 0 volts is applied to the substrate sub; a voltage Vcc is applied to the gate of the selected memory cell M22 (the word line WL1); The control gate of the unit M22 (control gate line CG1) applies a voltage Vcc, applies a voltage of 0 volts to the control gate (control gate line CG2); and applies to the doped region (bit line BL1) of the selected memory cell M22. Voltage Vcc; the doped region (bit line BL2) applies a voltage of 0 volts. Among them, the voltage Vcc is, for example, a power supply voltage. In the case of the above bias voltage, the digital information stored in the floating gate FGb (right bit) of the memory unit can be determined by detecting the channel current of the memory unit. The threshold voltage of the memory unit of the present invention is between Vcc and 0: the threshold voltage after the memory cell is erased is less than zero.

In the method for operating a non-volatile memory of the present invention, when a stylizing operation is performed, a low voltage is applied to the gate, so that a channel can be formed in the substrate under the gate, and a source-side hot electron injection mode is adopted. Write electrons to the floating gate. When the erase operation is performed, the gate is used to erase the data, and the electrons are removed through the erase dielectric layer, thereby reducing the number of times the electrons pass through the tunnel dielectric layer, thereby improving reliability. In addition, the height of the first portion of the erase dielectric layer is 0.8 times to less than 1 times the height of the floating gate, and the floating gate is provided with a corner portion, and the angle of the corner portion is less than or equal to 90 degrees. The corner portion concentrates the electric field and efficiently pulls electrons out of the floating gate, increasing the speed at which data is erased. Although the present invention has been disclosed above by way of example, it is not The scope of protection of the present invention is intended to be limited to the scope of the invention, and the scope of the invention is intended to be limited by the scope of the invention. The definition is final.

100‧‧‧Base

118a, 118b‧‧‧wipe the dielectric layer

120‧‧‧Stack structure

122‧‧‧gate dielectric layer

124‧‧‧ gate

126‧‧‧Insulation

128‧‧‧Shenjing District

130a, 130b‧‧‧ part one

132a, 132b‧‧‧ part two

140a, 140b‧‧‧ floating gate

141‧‧‧ Corner

142a, 142b‧‧‧ tunneling dielectric layer

146, 148‧‧‧ doped area

150a, 150b‧‧‧ control gate

152‧‧‧Interruptor dielectric layer

M‧‧‧ memory unit

Claims (17)

A non-volatile memory, comprising: a first memory unit disposed on a substrate having a deep well region, the first memory unit comprising: a stacked structure comprising a gate dielectric layer sequentially disposed on the substrate, a gate and an insulating layer, wherein the gate serves as an erase gate or a word line; the first floating gate and the second floating gate are respectively disposed on sidewalls of the two sides of the stacked structure, and The first floating gate and the top of the second floating gate respectively have a corner portion; the first tunneling dielectric layer and the second tunneling dielectric layer are respectively disposed on the first floating gate Between the pole and the substrate and between the second floating gate and the substrate; a first erase dielectric layer and a second erase dielectric layer are respectively disposed on the gate and the first Between a floating gate and the gate and the second floating gate, the first erase dielectric layer and the second erase dielectric layer respectively comprise a first portion and are located on the first portion a second portion, wherein the thickness of the second portion is less than or equal to the first portion, and the corner portion is adjacent The second portion; the first doped region and the second doped region are respectively disposed in the substrate, wherein the first floating gate, the stacked structure is connected to the second floating gate And disposed on the substrate between the first doped region and the second doped region; a first control gate and a second control gate are respectively disposed on the first floating gate and the ground Said on the second floating gate; The inter-gate dielectric layer is disposed between the first control gate and the first floating gate and between the second control gate and the second floating gate. The non-volatile memory of claim 1, further comprising: a first bit line and a second bit line disposed in parallel on the substrate, wherein the first doped region is electrically connected To the first bit line, the second doped region is electrically connected to the second bit line. The non-volatile memory of claim 1, wherein the second memory unit is further included in the row direction, the second memory unit is disposed on the substrate, and the structure and the second memory unit are The first memory cells have the same structure and share the second doped regions. The non-volatile memory of claim 3, further comprising: a first bit line and a second bit line disposed in parallel on the substrate, wherein the first memory unit and the first The second doping region shared by the two memory cells is electrically connected to the first bit line, the first doping region of the first memory cell and the third doping of the second memory cell The regions are electrically connected to the second bit line, respectively. The non-volatile memory of claim 3, wherein the first memory unit and the second memory unit share the first control gate or the second control gate, and The first control gate or the second control gate fills an opening between the first memory unit and the second memory unit. The non-volatile memory of claim 1, wherein the third memory unit is further included in the column direction, and the third memory unit is disposed on the substrate The structure of the third memory unit is the same as the structure of the first memory unit, and the third memory unit and the first memory unit are serially connected by the first doped region, sharing the a gate, the first control gate, and the second control gate, and the first control gate and the second control gate fill the first memory unit and the third memory unit between. The non-volatile memory of claim 6, further comprising: a first bit line, a second bit line and a third bit line, disposed in parallel on the substrate, wherein the series is The first doping region of the first memory unit and the third doping region are electrically connected to the second bit line, and the second doping region of the first memory cell is electrically connected to the The first bit line is electrically connected to the third bit line of the third memory cell. The non-volatile memory of claim 1, wherein the first tunneling dielectric layer is further disposed between the first control gate and the first doped region; The second tunneling dielectric layer is further disposed between the second control gate and the second doped region. The non-volatile memory of claim 1, wherein a height of the first erase dielectric layer and the first portion of the second erase dielectric layer is the first floating The gate is 0.8 times to less than 1 times the height of the second floating gate. The non-volatile memory of claim 1, wherein the material of the first erase dielectric layer and the first portion of the second erase dielectric layer comprises hafnium oxide/tantalum nitride , yttrium oxide / tantalum nitride / yttrium oxide or ytterbium oxide. The non-volatile memory of claim 1, wherein the material of the insulating layer comprises cerium oxide. The non-volatile memory according to claim 1, wherein the material of the inter-gate dielectric layer comprises yttrium oxide/yttria/yttria or tantalum nitride/yttria or other high dielectric constant. Material. The non-volatile memory of claim 1, wherein the material of the first tunneling dielectric layer and the second tunneling dielectric layer comprises yttrium oxide, the first tunneling dielectric The thickness of the layer and the second tunneling dielectric layer is between 60 angstroms and 200 angstroms. The non-volatile memory of claim 1, wherein the material of the gate dielectric layer comprises ruthenium oxide, and the thickness of the gate dielectric layer is less than or equal to the first tunnel dielectric layer and The thickness of the second tunneling dielectric layer. The non-volatile memory of claim 1, wherein the material of the first erase dielectric layer and the second portion of the second erase dielectric layer comprises ruthenium oxide, The thickness of the second portion is between 100 angstroms and 180 angstroms. The non-volatile memory of claim 1, wherein the corner portion angle is less than or equal to 90 degrees. The non-volatile memory of claim 1, wherein the programmed threshold voltage of the first memory unit is between Vcc and 0: the first memory unit is erased The threshold voltage is less than zero.