CN106206588A - Nonvolatile memory - Google Patents
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- CN106206588A CN106206588A CN201510217351.2A CN201510217351A CN106206588A CN 106206588 A CN106206588 A CN 106206588A CN 201510217351 A CN201510217351 A CN 201510217351A CN 106206588 A CN106206588 A CN 106206588A
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Abstract
The present invention provides a kind of nonvolatile memory, has memory element.Memory element has stacked structure, first and second floating grid, gate dielectric layer of erasing, supplementary gate dielectric layer, first and second doped region, first and second control gate.Stacked structure has gate dielectric layer, auxiliary grid, insulating barrier and the grid of erasing sequentially arranged.First and second floating grid is separately positioned on the sidewall of stacked structure both sides.Gate dielectric layer of erasing is arranged on erases between grid and first and second floating grid.Supplementary gate dielectric layer is arranged between auxiliary grid and first and second floating grid.First and second doped region is separately positioned on stacked structure and first and second floating grid both sides.First and second control gate is separately positioned on first and second floating grid.The present invention can operate with low operating voltage, and then increases the reliability of semiconductor element.
Description
Technical field
The present invention relates to a kind of semiconductor element, particularly relate to a kind of nonvolatile memory.
Background technology
Nonvolatile memory due to have can repeatedly carry out being stored in of data, read, the action such as erase, and the data being stored in exist
Also the advantage that will not disappear after power-off, the most widely used in PC with electronic equipment.
Typical a kind of nonvolatile memory designs becomes to have stack type grid (Stack-Gate) structure, including sequentially arranging
Dielectric layer and control gate (Control Gate) between suprabasil tunnel oxide, floating grid (Floating gate), grid.Right
This flash memory component be programmed or erase operation time, be to apply suitably in source area, drain region and control gate respectively
Voltage, so that electronics injects in polysilicon floating gate, or pulls out electronics from polysilicon floating gate.
Grid coupling efficiency (Gate-Coupling in the operation of nonvolatile memory, between usual floating grid and control gate
Ratio, is called for short: GCR) the biggest, and the running voltage needed for its operation will be the lowest, and the speed of operation of flash memory is with efficiency just
Can greatly promote.The method wherein increasing grid coupling efficiency, includes the overlapping area increased between floating grid and control gate
(Overlap Area), the thickness of the dielectric layer reduced between floating grid and control gate and increase floating grid and control gate
Between grid between dielectric constant (the Dielectric Constant of dielectric layer；K) etc..
But, along with integrated circuit just develops, so must reduce non-volatile towards the element of miniaturization with higher integration
The memory cell size of memorizer is to promote its integration.Wherein, the size reducing memory element can be by reducing memory element
The methods such as the interval of grid length and bit line are reached.But, grid length diminishes and can shorten leading to below tunnel oxide
Road length (Channel Length), easily causes, between drain electrode and source electrode, abnormal the most through (Punch Through) occurs, as
This will have a strong impact on the electrical performance of this memory element.And, programming and or erase memory element time, electronics repeats to pass over
Tunnel oxide, will consume tunnel oxide, cause memory component reliability to reduce.
Summary of the invention
The present invention provides a kind of nonvolatile memory, can operate with low operating voltage, and then increases the reliability of semiconductor element.
The present invention provides a kind of nonvolatile memory, can improve the integration of element.
The present invention proposes a kind of nonvolatile memory, has the first memory element, is arranged in substrate.First memory element,
Including: stacked structure, the first floating grid and the second floating grid, the first tunneling dielectric layer and the second tunneling dielectric layer, first
Gate dielectric layer and second of erasing erase gate dielectric layer, the first supplementary gate dielectric layer and the second supplementary gate dielectric layer, the first doped region with
Dielectric layer between the second doped region, the first control gate and the second control gate and grid.Stacked structure includes being sequentially arranged base
Gate dielectric layer, auxiliary grid, insulating barrier and grid of erasing at the end.First floating grid and the second floating grid are respectively provided with
At the sidewall of the both sides of stacked structure, and the top of the first floating grid and the second floating grid is respectively provided with corner portion, corner portion
Adjacent to erasing grid, and corner portion height falls within and erases between gate height.First tunneling dielectric layer and the second tunneling dielectric layer, point
It is not arranged between the first floating grid and substrate and between the second floating grid and substrate.First erases gate dielectric layer and second
Erase gate dielectric layer, be separately positioned on and erase between grid and the first floating grid and erase between grid and the second floating grid.
First supplementary gate dielectric layer and the second supplementary gate dielectric layer, be separately positioned between auxiliary grid and the first floating grid and assist
Between grid and the second floating grid.First doped region and the second doped region, be respectively provided with in the substrate, wherein the first floating grid
Pole, stacked structure and the connection of the second floating grid are arranged in the substrate between the first doped region and the second doped region.First controls
Grid and the second control gate are separately positioned on the first floating grid and the second floating grid.Between grid, dielectric layer is arranged on first
Between control gate and the first floating grid and between the second control gate and the second floating grid.
In one embodiment of this invention, above-mentioned nonvolatile memory has the first bit line and the second bit line.First bit
Line and the second bit line are set in parallel in substrate, and wherein the first doped region is electrically connected to the first bit line, the second doped region electricity
Property is connected to the second bit line.
In one embodiment of this invention, above-mentioned nonvolatile memory the most also includes the second memory element, and second deposits
Storage unit is arranged in substrate, and the structure of the second memory element is identical with the structure of the first memory element, shares the second doped region.
In one embodiment of this invention, above-mentioned nonvolatile memory has the first bit line and the second bit line.First bit
Line and the second bit line are set in parallel in substrate, the second doped region electricity that wherein the first memory element and the second memory element share
Property is connected to the first bit line, and the first doped region of the first memory element and the 3rd doped region of the second memory element the most electrically connect
It is connected to the second bit line.
In one embodiment of this invention, above-mentioned first memory element and the second memory element share the first control gate or the second control
Grid processed, and the first control gate or the second control gate fill up the opening between the first memory element and the second memory element.
In one embodiment of this invention, above-mentioned nonvolatile memory the most also includes the 3rd memory element, and the 3rd deposits
Storage unit is arranged in substrate, and the structure of the 3rd memory element is identical with the structure of the first memory element, the 3rd memory element and the
One memory element is serially connected by the first doped region, shares auxiliary grid, grid of erasing, the first control gate and second and controls
Grid, and the first control gate and the second control gate fill up between the first memory element and the 3rd memory element.
In one embodiment of this invention, above-mentioned nonvolatile memory has the first bit line, the second bit line and the 3rd bit
Line.First bit line, the second bit line and the 3rd bit line, be set in parallel in substrate, wherein concatenate the first memory element with
First doped region of the 3rd memory element is electrically connected to the second bit line, and the second doped region of the first memory element is electrically connected to
First bit line, the 3rd doped region of the 3rd memory element is electrically connected to the 3rd bit line.
In one embodiment of this invention, above-mentioned first tunneling dielectric layer is additionally arranged between the first control gate and the first doped region；
Second tunneling dielectric layer is additionally arranged between the second control gate and the second doped region.
In one embodiment of this invention, the thickness of above-mentioned first supplementary gate dielectric layer and the second supplementary gate dielectric layer is more than or equal to
First gate dielectric layer and second of erasing is erased the thickness of gate dielectric layer.
In one embodiment of this invention, the material of above-mentioned first supplementary gate dielectric layer and the second supplementary gate dielectric layer includes silicon oxide
/ silicon nitride, silicon oxide/silicon nitride/silicon oxide or silicon oxide.
In one embodiment of this invention, the material of above-mentioned insulating barrier includes silicon oxide.
In one embodiment of this invention, between above-mentioned grid, the material of dielectric layer includes silicon oxide/silicon nitride/silicon oxide or silicon nitride
The material (k ＞ 4) of/silicon oxide or other high-ks.
In one embodiment of this invention, the material of above-mentioned first tunneling dielectric layer and the second tunneling dielectric layer includes silicon oxide, the
The thickness of one tunneling dielectric layer and the second tunneling dielectric layer is between 60 angstroms to 200 angstroms.
In one embodiment of this invention, the material of above-mentioned gate dielectric layer includes silicon oxide, and the thickness of gate dielectric layer is less than or equal to
First tunneling dielectric layer and the thickness of the second tunneling dielectric layer.
In one embodiment of this invention, above-mentioned first erases gate dielectric layer and the second material erasing gate dielectric layer includes silicon oxide,
First gate dielectric layer and second of erasing erases the thickness of gate dielectric layer between 100 angstroms to 180 angstroms.
In one embodiment of this invention, above-mentioned corner portion angle is less than or equal to 90 degree.Threshold after first memory element is programmed
Threshold voltage is between Vcc and 0: first memory element threshold voltage after erasing is less than 0.
The nonvolatile memory of the present invention, two memory cell structures adjacent in X-direction (line direction) are identical, share the first doping
District or the second doped region.And (column direction) is adjacent in the Y direction two memory cell structures are identical, share the first doped region or second and mix
Miscellaneous district, auxiliary grid (character line), erase grid and control gate.Therefore the integration of element can be improved.
The nonvolatile memory of the present invention, auxiliary grid be arranged in parallel with grid of erasing, and therefore can improve the integration of element.
In the nonvolatile memory of the present invention, the thinner thickness of the gate dielectric layer below auxiliary grid, when operating memory element,
Less voltage can be used to beat the channel region below opening/closing auxiliary grid, namely low operating voltage can be dropped.
In the nonvolatile memory of the present invention, control gate cladding floating grid, by increasing capacitance it is possible to increase control gate and floating grid it
Area folded by between, and improve the coupling efficiency of memory component.
In the nonvolatile memory of the present invention, owing to floating grid is provided with corner portion erasing between gate height, and this corner
The angle in portion be less than or equal to 90 degree, make electric field concentrate by corner portion, it is possible to decrease voltage of erasing, efficient by electronics from float
Put grid pull-out, improve the speed of data of erasing.
The nonvolatile memory of the present invention, between not having between the first floating grid, stacked structure and the second floating grid
Gap, therefore can promote the integration of memory element.And, electricity can be stored at the first floating grid and the second floating grid
Lotus, therefore can store the data of two bits in single memory cell, and can promote storage volume.
For the features described above of the present invention and advantage can be become apparent, special embodiment below, and coordinate accompanying drawing to elaborate
As follows.
Accompanying drawing explanation
Figure 1A is the top view of a kind of nonvolatile memory shown by embodiments of the invention；
Figure 1B is the generalized section of a kind of nonvolatile memory shown by embodiments of the invention；
Fig. 1 C is the electrical schematic diagram of a kind of nonvolatile memory shown by embodiments of the invention；
Fig. 2 A and Fig. 2 B is the schematic diagram of the example that memory element is programmed operation；
Fig. 2 C and Fig. 2 D is the schematic diagram of one example of operation of erasing memory element；
Fig. 2 E and Fig. 2 F is the schematic diagram of the example being read memory element；
Fig. 3 A is the top view of a kind of nonvolatile memory shown by embodiments of the invention；
Fig. 3 B is the generalized section of a kind of nonvolatile memory shown by embodiments of the invention；
Fig. 3 C is the electrical schematic diagram of a kind of nonvolatile memory shown by embodiments of the invention；
Fig. 4 A and Fig. 4 B is the schematic diagram of the example that memory element is programmed operation；
Fig. 4 C and Fig. 4 D is the schematic diagram of one example of operation of erasing memory element；
Fig. 4 E and Fig. 4 F is the schematic diagram of the example being read memory element.
Description of reference numerals:
100: substrate；
102: isolation structure；
104: action zone；
118: cap layer；
120: stacked structure；
122: gate dielectric layer；
124: auxiliary grid；
126,166: insulating barrier；
128: grid of erasing；
130a, 130b: supplementary gate dielectric layer；
132a, 132b: gate dielectric layer of erasing；
140a, 140b, FGa, FGb: floating grid；
141: corner portion；
142a, 142b: tunneling dielectric layer；
146,148: doped region；
150a, 150b: control gate；
152: dielectric layer between grid；
162: connector；
164: opening；
BL0～BL3: bit line；
CG0～CG5: control gate polar curve；
EG0～EG2: line of erasing；
M, M11～M33: memory element；
WL0～WL2: character line.
Detailed description of the invention
Figure 1A is the top view of a kind of nonvolatile memory shown by embodiments of the invention.Figure 1B is the enforcement of the present invention
The generalized section of a kind of nonvolatile memory shown by example.Figure 1B is shown is along the profile of A-A' line in Figure 1A.
Fig. 1 C is the electrical schematic diagram of a kind of nonvolatile memory shown by embodiments of the invention.
Refer to Figure 1A, Figure 1B and Fig. 1 C, nonvolatile memory include multiple memory element M11～M33, character line WL0～
WL2, line EG0～EG2 that erase, bit line BL0～BL3, control gate polar curve CG0～CG5.Memory element M11～M33
Be arranged in rows/column array.
Nonvolatile memory is arranged in substrate 100.Isolation structure 102 such as it is provided with, to define master in substrate 100
Dynamic district 104.Isolation structure 102 e.g. shallow slot isolation structure.
As shown in Figure 1A, memory element M includes stacked structure 120, supplementary gate dielectric layer 130a (130b), gate dielectric layer of erasing
132a (132b), floating grid 140a (140b), tunneling dielectric layer 142a (142b), doped region 146, doped region 148, control gate
Dielectric layer 152 between pole 150a (150b) and grid.
Stacked structure 120 from substrate 100 sequentially by gate dielectric layer 122, auxiliary grid 124, insulating barrier 126 and grid of erasing
Pole 128 is constituted.Gate dielectric layer 122 is e.g. arranged between auxiliary grid 124 and substrate 100.The material of gate dielectric layer 122
Matter e.g. silicon oxide.The thickness of the thickness of gate dielectric layer 122 e.g., less than or equal to tunneling dielectric layer 142.
Auxiliary grid 124 is e.g. arranged between gate dielectric layer 122 and insulating barrier 126.Grid 128 of erasing e.g. is arranged
On insulating barrier 126.Auxiliary grid 124, grid 128 of erasing extend the most in the Y direction.Auxiliary grid 124, grid of erasing
The conductor materials such as the material of pole 128 e.g. DOPOS doped polycrystalline silicon.Insulating barrier 126 is e.g. arranged on auxiliary grid 124 and erases
Between grid 128.The material of insulating barrier 126 e.g. silicon oxide.Erasing, cap layer is optionally set on grid 128
118, the material of cap layer 118 e.g. silicon oxide or silicon nitride.
Supplementary gate dielectric layer 130a (130b) is e.g. arranged between floating grid 140a (140b) and auxiliary grid 124.Supplementary gate
The material e.g. silicon oxide/silicon nitride/silicon oxide of dielectric layer 130a (130b), nitridation silicon/oxidative silicon or silicon oxide.Supplementary gate
The thickness of dielectric layer 130a (130b) is greater than or equal to erasing the thickness of gate dielectric layer 132a (132b).Erase gate dielectric layer
132a (132b) is e.g. arranged on and erases between grid 128 and floating grid 140a (140b).Erase gate dielectric layer 132a (132b)
Material e.g. silicon oxide.Erase the thickness of gate dielectric layer 132a (132b) such as between 100 angstroms to 180 angstroms.
Floating grid 140a and floating grid 140b is e.g. arranged on the sidewall of stacked structure 120 both sides, and this floating grid
The top of 140a and floating grid 140b is respectively provided with corner portion 141.This corner portion 141 neighbouring erase grid 128, and this turn
Corner 141 highly falls within erases between grid 128 height.This corner portion 141 angle is less than or equal to 90 degree.Floating grid 140a
And the conductor material such as the material of floating grid 140b e.g. DOPOS doped polycrystalline silicon.Floating grid 140a and floating grid 140b is respectively
Can be made up of one or more layers conductor layer.
Tunneling dielectric layer 142a is e.g. arranged between floating grid 140a and substrate 100；Tunneling dielectric layer 142b is e.g.
It is arranged between floating grid 140b and substrate 100.Tunneling dielectric layer 142a is e.g. additionally arranged at control gate 150a and mixes
Between miscellaneous district 146；Tunneling dielectric layer 142b is e.g. additionally arranged between control gate 150b and doped region 148.Tunneling Jie
The material of electric layer 142a and tunneling dielectric layer 142b e.g. silicon oxide.Tunneling dielectric layer 142a and the thickness of tunneling dielectric layer 142b
Degree is between 60 angstroms to 200 angstroms.
Doped region 146 is e.g. arranged in the substrate 100 that floating grid 140a is other.Doped region 148 is e.g. arranged on floating
In the substrate 100 that grid 140b is other.Floating grid 140a, stacked structure 120 are connected with floating grid 140b and are arranged on doping
In substrate 100 between district 146 and doped region 148.Doped region 146, doped region 148 e.g. contain N-type or p-type is mixed
The doped region of matter, end is depending on the design of element.
Control gate 150a is e.g. arranged on floating grid 140a；Control gate 150b is e.g. arranged on floating grid 140b
On.Control gate 150a and control gate 150b (column direction) the most in the Y direction extend.Control gate 150a and control gate
The conductor materials such as the material of pole 150b e.g. DOPOS doped polycrystalline silicon.Between grid, dielectric layer 152 is e.g. arranged on control gate 150a
And between floating grid 140a and between control gate 150b and floating grid 140b.Between grid, the material of dielectric layer 152 is such as
It is silicon oxide/silicon nitride/silicon oxide or nitridation silicon/oxidative silicon or the material (k ＞ 4) of other high-ks.
Interlayer insulating film (not shown) is e.g. arranged in substrate 100, and covers memory element M.The material of interlayer insulating film
E.g. silicon oxide, phosphorosilicate glass, boron-phosphorosilicate glass or other dielectric materials being suitable for.Multiple connectors 162 are e.g. arranged on
In interlayer insulating film.The material of the connector 162 e.g. conductor such as aluminum, tungsten material.Multiple bit line BL0～BL3 e.g. set
Putting on interlayer insulating film, bit line BL0～BL3 passes through the doped region 146 of connector 162 and each memory element M respectively or mixes
Miscellaneous district 148 is electrically connected with.The conductor materials such as the material of bit line BL0～BL3 e.g. aluminum, tungsten, copper.As shown in Figure 1 C,
Memory element M11～M33 have structure as illustrated in figures ia and ib.In the following description, memory element M in Figure 1B,
It is divided into left side bit a and right side bit b.
In X-direction (line direction), multiple memory element M are serially connected by doped region (doped region 146 or doped region 148).
For example, the structure of memory element M11 is identical with the structure of memory element M12, shares a doped region (doped region 146
Or doped region 148)；The structure of memory element M12 is identical with the structure of memory element M13, shares a doped region (doped region
146 or doped region 148)；…；The structure of memory element M31 is identical with the structure of memory element M32, shares a doped region
(doped region 146 or doped region 148)；The structure of memory element M32 is identical with the structure of memory element M33, shares one and mixes
Miscellaneous district (doped region 146 or doped region 148).
In the Y direction on (column direction), multiple memory element M are serially connected by doped region (doped region 146 or doped region 148),
And shared auxiliary grid 124, grid 128 and control gate 150a of erasing and control gate 150b.Control gate 150a
And control gate 150b fills up memory element M (such as: memory element M11, memory element M21 and memory element M31)
Between.For example, the structure of memory element M11 is identical with the structure of memory element M21, shares (the doping of a doped region
District 146 or doped region 148), the structure of a memory element M21 shared doped region identical with the structure of memory element M31 (is mixed
Miscellaneous district 146 or doped region 148)；…；The structure of memory element M13 is identical with the structure of memory element M23, shares one and mixes
Miscellaneous district (doped region 146 or doped region 148), the structure of memory element M23 is identical with the structure of memory element M33 shares one
Doped region (doped region 146 or doped region 148).
Bit line BL0～BL3 is e.g. separately positioned in substrate, these bit lines BL0～BL3 parallel in the row direction
Row.Configure a memory cell rows among two adjacent bit lines, and the doped region that this memory cell rows is comprised be in a staggered manner,
It is respectively connecting to the adjacent bit line of corresponding two (doped region 146 or doped region 148).For example, memory element M11,
Memory element M12, memory element M13 concatenation forms memory cell rows, starts to count from memory element M11, the 1st, 3
Doped region is electrically connected to bit line BL0, and the 2nd, 4 doped regions are electrically connected to bit line BL1.Memory element M21, deposit
Storage unit M22, memory element M23 concatenation forms memory cell rows, and the 1st, 3 doped regions are electrically connected to bit line BL2,
2nd, 4 doped regions are electrically connected to the 3rd article of bit line BL1.Memory element M31, memory element M32, memory element
M33 concatenation forms memory cell rows, and the 1st, 3 doped regions are electrically connected to bit line BL2, and the 2nd, 4 doped regions are electrical
It is connected to the 3rd article of bit line BL3.
And, in the row direction, for example, the doped region that memory element M11 of concatenation, memory element M12 share is electrical
Being connected to bit line BL1, the memory element M11 doped region unshared with memory element M12 is then respectively and electrically connected to bit line
BL0.In a column direction, for example, the doped region that memory element M11 of concatenation, memory element M21 share is electrically connected with
To bit line BL1, another doped region of memory element M11 is electrically connected to bit line BL0, and another of memory element M21 is mixed
Miscellaneous district is electrically connected to bit line BL2.
Character line WL0～WL2 is e.g. separately positioned in substrate, and these character lines WL0～WL2 is parallel on the direction of row
Arrangement, connects the auxiliary grid 124 of the memory element of same string respectively.For example, character line WL0 connects memory element
The auxiliary grid 124 of M11～M31.Character line WL1 connects memory element M12～the auxiliary grid 124 of M32.Character line
WL2 connects memory element M13～the auxiliary grid 124 of M33.
Line EG0～EG2 that erase e.g. is separately positioned in substrate, these line EG0～EG2 parallel on the direction of row of erasing
Row, connect the grid 128 of erasing of the memory element of same string respectively.For example, the line EG 0 that erases connect memory element M11～
The grid 128 of erasing of M31.The line EG1 that erases connects memory element M12～the grid 128 of erasing of M32.The line EG2 that erases is even
Connect the grid 128 of erasing of memory element M13～M33.
Control gate polar curve CG0～CG5 is separately positioned in substrate, and these control gates polar curve CG0～CG5 is parallel on the direction of row
Arrangement, connects control gate 150a or control gate 150b of the memory element of same string respectively.In the present embodiment, control gate
Polar curve CG0, CG2, CG4 connect control gate 150a of the memory element with string.Control gate polar curve CG1, CG3, CG5
Connect control gate 150b of the memory element with string.
In above-mentioned nonvolatile memory, the two memory element M structure adjacent in X-direction (line direction) are identical, share the
One doped region 146 or the second doped region 148.And (column direction) is adjacent in the Y direction two memory element M structure are identical, share
First doped region 146 or the second doped region 148, auxiliary grid (character line) 124, erase grid 128 and control gate
150a(150b).Therefore the integration of element can be improved.
In above-mentioned nonvolatile memory, auxiliary grid becomes stacked structure with gate configuration of erasing, and therefore can improve element
Integration.
In above-mentioned nonvolatile memory, the thinner thickness of gate dielectric layer 122, when operating memory element, it is possible to use
Less voltage beats the channel region below opening/closing auxiliary grid 124, namely can drop low operating voltage.Control gate
150a (150b) cladding floating grid 140a (140b), by increasing capacitance it is possible to increase control gate 150a (150b) and floating grid 140a (140b) it
Area folded by between, and improve the coupling efficiency of memory component.Owing to floating grid 140a (140b) is at grid 128 height of erasing
Between be provided with corner portion 141, and the angle of this corner portion 141 is less than or equal to 90 degree, makes electric field concentrate by corner portion 141,
Can reduce that voltage of erasing is efficient to be pulled out electronics from floating grid 140a (140b), improve the speed of data of erasing.
The nonvolatile memory of the present invention, owing to not having between floating grid 140a, stacked structure 120 and floating grid 140b
There is gap, therefore can promote the integration of memory element.And, can at floating grid 140a and floating grid 140b
Store electric charge, therefore can store the data of two bits in single memory cell, and storage volume can be promoted.
Then, the operator scheme of the nonvolatile memory of the present invention being described, including programming, erasing operates mould with digital independent etc.
Formula.Fig. 2 A and Fig. 2 B is the schematic diagram of the example that memory element is programmed operation.Fig. 2 C and Fig. 2 D is single to storage
Unit is carried out erasing the schematic diagram of an example of operation.Fig. 2 E and Fig. 2 F is showing of the example that is read memory element
It is intended to.
Refer to Fig. 2 A, when the floating grid FGa (left side bit) of selected memory cell M22 being programmed operation, in choosing
The auxiliary grid (character line WL1) determining memory element M22 applies voltage Vwlp, logical to be formed in the substrate below auxiliary grid
Road, voltage Vwlp e.g. 0.6～1.2 volt.The auxiliary grid (character line WL0, WL2) of non-selected memory element applies 0
The voltage of volt.Doped region (bit line BL1) at selected memory cell M22 applies voltage Vblp；Doped region (bit line BL2)
Apply voltage Vbli；Voltage Vcgp is applied in control gate (control gate polar curve CG2)；At control gate (control gate polar curve CG3)
Apply voltage vcc.The grid of erasing (erase line EG1) of selected memory cell M22 applies voltage Vegp and non-selected storage list
The grid of erasing (erase line EG0, EG2) of unit applies 0 volt.Voltage Vblp e.g. 3～7 volts；Voltage Vbli is e.g.
0.3 volt；Voltage Vcgp e.g. 5～9 volts；Voltage Vegp e.g. 3～7 volts.This kind bias under, make electronics by
Drain electrode (bit line BL2) is mobile toward source electrode (bit line BL1), the pattern injected with source side hot electron, injects selected memory cell
The floating grid FGa (left side bit) of M22.Owing to the auxiliary grid (character line WL0, WL2) of non-selected memory element applies 0
The voltage of volt, it is impossible to forming channel region, electronics cannot inject the floating grid of non-selected memory element, the most non-selected storage
Unit will not be programmed.
Refer to Fig. 2 B, when the floating grid FGb (right side bit) of selected memory cell M22 being programmed operation, in choosing
The auxiliary grid (character line WL1) determining memory element M22 applies voltage Vwlp, logical to be formed in the substrate below auxiliary grid
Road, voltage Vwlp e.g. 0.6～1.2 volt.The auxiliary grid (character line WL0, WL2) of non-selected memory element applies 0
The voltage of volt.Doped region (bit line BL2) at selected memory cell M22 applies voltage Vblp；Doped region (bit line BL1)
Apply voltage Vbli；Voltage Vcgp is applied in control gate (control gate polar curve CG3)；At control gate (control gate polar curve CG2)
Apply voltage vcc.The grid of erasing (erase line EG1) of selected memory cell M22 applies voltage Vegp and non-selected storage list
The grid of erasing (erase line EG0, EG2) of unit applies 0 volt.Voltage Vblp e.g. 3～7 volts；Voltage Vbli is e.g.
0.3 volt；Voltage Vcgp e.g. 5～9 volts；Voltage Vegp e.g. 3～7 volts.This kind bias under, make electronics by
Drain electrode (bit line BL1) is mobile toward source electrode (bit line BL2), the pattern injected with source side hot electron, injects selected memory cell
The floating grid FGb (right side bit) of M22.Owing to the auxiliary grid (character line WL0, WL2) of non-selected memory element applies 0
The voltage of volt, it is impossible to forming channel region, electronics cannot inject the floating grid of non-selected memory element, the most non-selected storage
Unit will not be programmed.
Refer to Fig. 2 C, when the floating grid FGa (left side bit) of selected memory cell M22 being erased operation, in choosing
The control gate (control gate polar curve CG2) determining memory element M22 applies voltage Vcge；Control at selected memory cell M22
Grid (control gate polar curve CG3) applies the voltage of 0 volt；Grid of erasing (erase line EG1) at selected memory cell M22 is executed
Making alive Vege；Grid of erasing (erase line EG0, EG2) in non-selected memory element applies the voltage of 0 volt.Voltage Vege
E.g. 6～12 volts；Voltage Vcge e.g.-8～0 volts.Grid (is smeared with erasing to utilize control gate (control gate polar curve CG2)
Except line EG1) voltage difference, cause FN tunneling effect, floating grid FGa (left side bit) electronics being stored in memory element is drawn
Go out and remove.
Refer to Fig. 2 D, when the floating grid FGb (right side bit) of selected memory cell M22 being erased operation, in choosing
The control gate (control gate polar curve CG3) determining memory element M22 applies voltage Vcge；Control at selected memory cell M22
Grid (control gate polar curve CG2) applies the voltage of 0 volt；Grid of erasing (erase line EG1) at selected memory cell M22 is executed
Making alive Vege；Grid of erasing (erase line EG0, EG2) in non-selected memory element applies the voltage of 0 volt.Voltage Vege
E.g. 6～12 volts；Voltage Vcge e.g.-8～0 volts.Grid (is smeared with erasing to utilize control gate (control gate polar curve CG3)
Except line EG1) voltage difference, cause FN tunneling effect, floating grid FGb (right side bit) electronics being stored in memory element is drawn
Go out and remove.
Refer to Fig. 2 E, when being read, the auxiliary grid (character line WL1) at selected memory cell M22 applies electricity
Pressure Vcc；Control gate (control gate polar curve CG2) at selected memory cell M22 applies the voltage of 0 volt, in control gate (control
Gate line CG3 processed) apply voltage vcc；Grid of erasing (erase line EG1) at selected memory cell M22 applies 0 volt；?
The doped region (bit line BL2) of selected memory cell M22 applies voltage vcc；Doped region (bit line BL1) applies the electricity of 0 volt
Pressure；Grid of erasing (erase line EG0, EG2) in non-selected memory element applies 0 volt.Wherein, voltage vcc is the most electric
Source voltage.In the case of above-mentioned bias, can judge to be stored in storage single by detecting the channel current size of memory element
Digital information in the floating grid FGa (left side bit) of unit.
Refer to Fig. 2 F, when being read, the auxiliary grid (character line WL1) at selected memory cell M22 applies electricity
Pressure Vcc；Control gate (control gate polar curve CG3) at selected memory cell M22 applies the voltage of 0 volt, in control gate (control
Gate line CG2 processed) apply voltage vcc；Grid of erasing (erase line EG1) at selected memory cell M22 applies 0 volt；?
The doped region (bit line BL1) of selected memory cell M22 applies voltage vcc；Doped region (bit line BL2) applies the electricity of 0 volt
Pressure；Grid of erasing (erase line EG0, EG2) in non-selected memory element applies 0 volt.Wherein, voltage vcc is the most electric
Source voltage.In the case of above-mentioned bias, can judge to be stored in storage single by detecting the channel current size of memory element
Digital information in the floating grid FGb (right side bit) of unit.
In the operational approach of the nonvolatile memory of the present invention, when being programmed operation, auxiliary grid is applied low-voltage,
Substrate below auxiliary grid can form passage, the pattern injected with source side hot electron, electronics is write floating grid.
When carrying out erasing operation, utilize grid of erasing to data of erasing, make electronics remove via gate dielectric layer of erasing, electronics can be reduced
Through the number of times of tunneling dielectric layer, and then improve reliability.Erase between gate height additionally, the corner portion of floating grid is arranged on,
And the angle of this corner portion is less than or equal to 90 degree, make electric field concentrate by corner portion, can efficient by electronics from floating grid
Pull-out, improves the speed of data of erasing.Threshold voltage after the memory element of the present invention is programmed is between Vcc and 0: deposit
Storage unit threshold voltage after erasing is less than 0.
Fig. 3 A is the top view of a kind of nonvolatile memory shown by another embodiment of the present invention.Fig. 3 B is the present invention's
The generalized section of a kind of nonvolatile memory shown by another embodiment.Fig. 3 B is shown is A-A' in Fig. 3 A
The profile of line.Fig. 3 C is the electrical schematic diagram of a kind of nonvolatile memory shown by embodiments of the invention.At Fig. 3 A～figure
In 3C, component is identical with Figure 1A～Fig. 1 C, gives identical label, and description is omitted.
Refer to Fig. 3 A, Fig. 3 B and Fig. 3 C, nonvolatile memory include multiple memory element M11～M33, character line WL0～
WL2, line EG0～EG2 that erase, bit line BL0～BL3, control gate polar curve CG0～CG3.Memory element M11～M33
Be arranged in rows/column array.
Nonvolatile memory is arranged in substrate 100.Isolation structure 102 such as it is provided with, to define master in substrate 100
Dynamic district 104.Isolation structure 102 e.g. shallow slot isolation structure.
As shown in Figure 3A, memory element M includes stacked structure 120, supplementary gate dielectric layer 130a (130b), gate dielectric layer of erasing
132a (132b), floating grid 140a (140b), tunneling dielectric layer 142a (142b), doped region 146, doped region 148, control gate
Dielectric layer 152 between pole 150a (150b) and grid.
Stacked structure 120 from substrate 100 sequentially by gate dielectric layer 122, auxiliary grid 124, insulating barrier 126 and grid of erasing
Pole 128 is constituted.Erasing, cap layer 118 is optionally set on grid 128.
Floating grid 140a and floating grid 140b is e.g. arranged on the sidewall of stacked structure 120 both sides, and this floating grid
The top of 140a and floating grid 140b is respectively provided with corner portion 141.This corner portion 141 neighbouring erase grid 128, and this turn
Corner 141 highly falls within erases between grid 128 height.This corner portion 141 angle is less than or equal to 90 degree.
Tunneling dielectric layer 142a is e.g. arranged between floating grid 140a and substrate 100；Tunneling dielectric layer 142b is e.g.
It is arranged between floating grid 140b and substrate 100.This tunneling dielectric layer 142a be e.g. additionally arranged at control gate 150a with
Between doped region 146；This tunneling dielectric layer 142b is e.g. additionally arranged between control gate 150b and doped region 148.
Doped region 146 is e.g. arranged in the substrate 100 that floating grid 140a is other.Doped region 148 is e.g. arranged on floating
In the substrate 100 that grid 140b is other.Floating grid 140a, stacked structure 120 are connected with floating grid 140b and are arranged on doping
In substrate 100 between district 146 and doped region 148.Doped region 146, doped region 148 e.g. contain N-type or p-type is mixed
The doped region of matter, end is depending on the design of element.
Control gate 150a and control gate 150b are provided in floating grid 140a and the floating grid of adjacent two memory element respectively
On the 140b of pole.Control gate 150a and control gate 150b (column direction) the most in the Y direction extend.Two adjacent storages are single
Unit shares institute's control gate 150a or control gate 150b, and control gate 150a and control gate 150b fill up adjacent two respectively
Opening between memory element.
Between grid dielectric layer 152 be e.g. arranged between control gate 150a and floating grid 140a and control gate 150b with
Between floating grid 140b.
Interlayer insulating film (not shown) is e.g. arranged in substrate 100, and covers memory element M.Multiple connectors 162 are such as
It is provided in interlayer insulating film.Multiple bit line BL0～BL3 are e.g. arranged on interlayer insulating film, bit line BL0～
BL3 is electrically connected with by doped region 146 or the doped region 148 of connector 162 with each memory element M respectively.Refer to Fig. 3 A,
Interlayer insulating film, control gate 150a and control gate 150b can be run through until exposing in order to form the opening 164 of connector 162
Go out doped region 146 and doped region 148.Between connector 162 and control gate 150a and connector 162 and control gate 150b it
Between can be formed with insulating barrier 166.The conductor materials such as the material of bit line BL0～BL3 e.g. aluminum, tungsten, copper.
As shown in Figure 3 C, memory element M11～M33 have the structure as shown in Fig. 3 A and Fig. 3 B.In the following description, figure
Memory element M in 1B, is divided into left side bit a and right side bit b.
In X-direction (line direction), multiple memory element M are serially connected by doped region (doped region 146 or doped region 148),
Adjacent memory element M can share control gate.For example, the structure of memory element M11 and the knot of memory element M12
Structure is identical, shares a doped region (doped region 146 or doped region 148), and share control gate (control gate 150a or
Control gate 150b)；The structure of memory element M12 is identical with the structure of memory element M13, shares a doped region (doped region
146 or doped region 148), and share a control gate (control gate 150a or control gate 150b)；…；Memory element M31
Structure identical with the structure of memory element M32, share a doped region (doped region 146 or doped region 148), and share one
Control gate (control gate 150a or control gate 150b)；The structure phase of the structure of memory element M32 and memory element M33
With, share a doped region (doped region 146 or doped region 148), and share control gate (control gate 150a or a control
Grid 150b).
In the Y direction on (column direction), multiple memory element M are serially connected by doped region (doped region 146 or doped region 148),
And shared auxiliary grid 124, grid 128 and control gate 150a of erasing and control gate 150b.Control gate 150a
And control gate 150b fills up memory element M (such as: memory element M11, memory element M21 and memory element M31)
Between.For example, the structure of memory element M11 is identical with the structure of memory element M21, shares (the doping of a doped region
District 146 or doped region 148), the structure of a memory element M21 shared doped region identical with the structure of memory element M31 (is mixed
Miscellaneous district 146 or doped region 148)；…；The structure of memory element M13 is identical with the structure of memory element M23, shares one
Doped region (doped region 146 or doped region 148), the structure of memory element M23 is identical with the structure of memory element M33 shares one
Individual doped region (doped region 146 or doped region 148).
Bit line BL0～BL3 is e.g. separately positioned in substrate, these bit lines BL0～BL3 parallel in the row direction
Row.Configure a memory cell rows among two adjacent bit lines, and the doped region that this memory cell rows is comprised be in a staggered manner,
It is respectively connecting to the adjacent bit line of corresponding two (doped region 146 or doped region 148).For example, memory element M11,
Memory element M12, memory element M13 concatenation forms memory cell rows, starts to count from memory element M11, the 1st, 3
Doped region is electrically connected to bit line BL0, and the 2nd, 4 doped regions are electrically connected to bit line BL1.Memory element M21, deposit
Storage unit M22, memory element M23 concatenation forms memory cell rows, and the 1st, 3 doped regions are electrically connected to bit line BL2,
2nd, 4 doped regions are electrically connected to the 3rd article of bit line BL1.Memory element M31, memory element M32, memory element
M33 concatenation forms memory cell rows, and the 1st, 3 doped regions are electrically connected to bit line BL2, and the 2nd, 4 doped regions are electrical
It is connected to the 3rd article of bit line BL3.
And, in the row direction, for example, the doped region that memory element M11 of concatenation, memory element M12 share is electrical
Being connected to bit line BL1, the memory element M11 doped region unshared with memory element M12 is then respectively and electrically connected to bit line
BL0.In a column direction, for example, the doped region that memory element M11 of concatenation, memory element M21 share is electrically connected with
To bit line BL1, another doped region of memory element M11 is electrically connected to bit line BL0, and another of memory element M21 is mixed
Miscellaneous district is electrically connected to bit line BL2.
Character line WL0～WL2 is e.g. separately positioned in substrate, and these character lines WL0～WL2 is parallel on the direction of row
Arrangement, connects the auxiliary grid 124 of the memory element of same string respectively.For example, character line WL0 connects memory element
The auxiliary grid 124 of M11～M31.Character line WL1 connects memory element M12～the auxiliary grid 124 of M32.Character line
WL2 connects memory element M13～the auxiliary grid 124 of M33.
Line EG0～EG2 that erase e.g. is separately positioned in substrate, these line EG0～EG2 parallel on the direction of row of erasing
Row, connect the grid 128 of erasing of the memory element of same string respectively.For example, the line EG 0 that erases connect memory element M11～
The grid 128 of erasing of M31.The line EG1 that erases connects memory element M12～the grid 128 of erasing of M32.The line EG2 that erases is even
Connect the grid 128 of erasing of memory element M13～M33.
Control gate polar curve CG0～CG3 is separately positioned in substrate, and these control gates polar curve CG0～CG3 is parallel on the direction of row
Arrangement, connects control gate 150a (150b) of the memory element of adjacent two row respectively.In the present embodiment, control gate polar curve CG0
Connect control gate 150a (150b) in the left side of memory element M11, M21, M31；It is single that control gate polar curve CG1 connects storage
Control gate 150a (150b) on right side of unit M11, M21, M31 and memory element M12, the left side of M22, M32
Control gate 150a (150b)；Control gate polar curve CG2 connects the control gate on the right side of memory element M12, M22, M32
150a (150b) and memory element M13, control gate 150a (150b) in left side of M23, M33；Control gate polar curve CG3
Connect control gate 150a (150b) on the right side of memory element M13, M23, M33.
In above-mentioned nonvolatile memory, the two memory element M structure adjacent in X-direction (line direction) are identical, share and mix
Miscellaneous district 146 or doped region 148 and control gate 150a (150b).And two memory element M that (column direction) is adjacent in the Y direction
Structure is identical, shares doped region 146 or doped region 148, auxiliary grid (character line) 124, erase grid 128 and control gate
150a(150b).Therefore the integration of element can be improved.
In above-mentioned nonvolatile memory, auxiliary grid becomes stacked structure with gate configuration of erasing, and therefore can improve element
Integration.
In above-mentioned nonvolatile memory, the thinner thickness of gate dielectric layer 122, when operating memory element, it is possible to use
Less voltage beats the channel region below opening/closing auxiliary grid 124, namely can drop low operating voltage.Control gate
150a (150b) cladding floating grid 140a (140b), by increasing capacitance it is possible to increase control gate 150a (150b) and floating grid 140a (140b) it
Between folded area, and improve memory component coupling efficiency.Owing to floating grid 140a (140b) is at grid 128 of erasing
It is provided with corner portion 141 between height, and the angle of this corner portion 141 is less than or equal to 90 degree, makes electric field by corner portion 141
Concentrate, it is possible to decrease voltage of erasing is efficient to be pulled out electronics from floating grid 140a (140b), improves the speed of data of erasing.
The nonvolatile memory of the present invention, owing to not having between floating grid 140a, stacked structure 120 and floating grid 140b
There is gap, therefore can promote the integration of memory element.And, can at floating grid 140a and floating grid 140b
Store electric charge, therefore can store the data of two bits in single memory cell, and storage volume can be promoted.
Then, the operator scheme of the nonvolatile memory of the present invention being described, including programming, erasing operates mould with digital independent etc.
Formula.Fig. 4 A and Fig. 4 B is the schematic diagram of the example that memory element is programmed operation.Fig. 4 C and Fig. 4 D is single to storage
Unit is carried out erasing the schematic diagram of an example of operation.Fig. 4 E and Fig. 4 F is showing of the example that is read memory element
It is intended to.
Refer to Fig. 4 A, when the floating grid FGa (left side bit) of selected memory cell M22 being programmed operation, in choosing
The auxiliary grid (character line WL1) determining memory element M22 applies voltage Vwlp, logical to be formed in the substrate below auxiliary grid
Road, voltage Vwlp e.g. 0.6～1.2 volt.The auxiliary grid (character line WL0, WL2) of non-selected memory element applies 0
The voltage of volt.Doped region (bit line BL1) at selected memory cell M22 applies voltage Vblp；Doped region (bit line BL2)
Apply voltage Vbli；Voltage Vcgp is applied in control gate (control gate polar curve CG1)；At control gate (control gate polar curve CG2)
Apply voltage vcc.The grid of erasing (erase line EG1) of selected memory cell M22 and the grid of erasing of non-selected memory element (are smeared
Except line EG0, EG2) apply voltage Vegp.Voltage Vblp e.g. 3～7 volts；Voltage Vbli e.g. 0.3 volt；Electricity
Pressure Vcgp e.g. 5～9 volts；Voltage Vegp e.g. 3～7 volts.Under this kind of bias, make electronics by the (bit line that drains
BL2) pattern that is mobile toward source electrode (bit line BL1), that inject with source side hot electron, injects the floating of selected memory cell M22
Grid FGa (left side bit).Auxiliary grid (character line WL0, WL2) due to non-selected memory element applies the voltage of 0 volt,
Cannot form channel region, electronics cannot inject the floating grid of non-selected memory element, and the most non-selected memory element will not be compiled
Journey.
Refer to Fig. 4 B, when the floating grid FGb (right side bit) of selected memory cell M22 being programmed operation, in choosing
The auxiliary grid (character line WL1) determining memory element M22 applies voltage Vwlp, logical to be formed in the substrate below auxiliary grid
Road, voltage Vwlp e.g. 0.6～1.2 volt.The auxiliary grid (character line WL0, WL2) of non-selected memory element applies 0
The voltage of volt.Doped region (bit line BL2) at selected memory cell M22 applies voltage Vblp；Doped region (bit line BL1)
Apply voltage Vbli；Voltage Vcgp is applied in control gate (control gate polar curve CG2)；At control gate (control gate polar curve CG1)
Apply voltage vcc.The grid of erasing (erase line EG1) of selected memory cell M22 and the grid of erasing of non-selected memory element (are smeared
Except line EG0, EG2) apply voltage Vegp.Voltage Vblp e.g. 3～7 volts；Voltage Vbli e.g. 0.3 volt；Electricity
Pressure Vcgp e.g. 5～9 volts；Voltage Vegp e.g. 3～7 volts.Under this kind of bias, make electronics by the (bit line that drains
BL1) pattern that is mobile toward source electrode (bit line BL2), that inject with source side hot electron, injects the floating of selected memory cell M22
Grid FGb (right side bit).Auxiliary grid (character line WL0, WL2) due to non-selected memory element applies the voltage of 0 volt,
Cannot form channel region, electronics cannot inject the floating grid of non-selected memory element, and the most non-selected memory element will not be compiled
Journey.
Refer to Fig. 4 C, when the floating grid FGa (left side bit) of selected memory cell M22 being erased operation, in choosing
The control gate (control gate polar curve CG1) determining memory element M22 applies voltage Vcge；Control at selected memory cell M22
Grid (control gate polar curve CG2) applies the voltage of 0 volt；Grid of erasing (erase line EG1) at selected memory cell M22 is executed
Making alive Vege；Grid of erasing (erase line EG0, EG2) in non-selected memory element applies the voltage of 0 volt.Voltage Vege
E.g. 6～12 volts；Voltage Vcge e.g.-8～0 volts.Grid (is smeared with erasing to utilize control gate (control gate polar curve CG1)
Except line EG1) voltage difference, cause FN tunneling effect, floating grid FGa (left side bit) electronics being stored in memory element is drawn
Go out and remove.
Refer to Fig. 4 D, when the floating grid FGb (right side bit) of selected memory cell M22 being erased operation, in choosing
The control gate (control gate polar curve CG2) determining memory element M22 applies voltage Vcge；Control at selected memory cell M22
Grid (control gate polar curve CG1) applies the voltage of 0 volt；Grid of erasing (erase line EG1) at selected memory cell M22 is executed
Making alive Vege；Grid of erasing (erase line EG0, EG2) in non-selected memory element applies the voltage of 0 volt.Voltage Vege
E.g. 6～12 volts；Voltage Vcge e.g.-8～0 volts.Grid (is smeared with erasing to utilize control gate (control gate polar curve CG2)
Except line EG1) voltage difference, cause FN tunneling effect, floating grid FGb (right side bit) electronics being stored in memory element is drawn
Go out and remove.
Refer to Fig. 4 E, when being read, the auxiliary grid (character line WL1) at selected memory cell M22 applies electricity
Pressure Vcc；Control gate (control gate polar curve CG1) at selected memory cell M22 applies the voltage of 0 volt, in control gate (control
Gate line CG2 processed) apply voltage vcc；Grid of erasing (erase line EG1) at selected memory cell M22 applies the electricity of 0 volt
Pressure；Doped region (bit line BL2) at selected memory cell M22 applies voltage vcc；Doped region (bit line BL1) applies 0 volt
Special voltage；Grid of erasing (erase line EG0, EG2) in non-selected memory element applies the voltage of 0 volt.Wherein, voltage
Vcc e.g. supply voltage.In the case of above-mentioned bias, storage can be judged by detecting the channel current size of memory element
It is stored in the digital information in the floating grid FGa (left side bit) of memory element.
Refer to Fig. 4 F, when being read, the auxiliary grid (character line WL1) at selected memory cell M22 applies electricity
Pressure Vcc；Control gate (control gate polar curve CG1) at selected memory cell M22 applies voltage vcc, (controls in control gate
Gate line CG2) apply the voltage of 0 volt；Grid of erasing (erase line EG1) at selected memory cell M22 applies 0 volt
Voltage；Doped region (bit line BL1) at selected memory cell M22 applies voltage vcc；Doped region (bit line BL2) applies 0
The voltage of volt；Grid of erasing (erase line EG0, EG2) in non-selected memory element applies the voltage of 0 volt.Wherein, electricity
Pressure Vcc e.g. supply voltage.In the case of above-mentioned bias, can sentence by detecting the channel current size of memory element
Digital information in the disconnected floating grid FGb (right side bit) being stored in memory element.
In the operational approach of the nonvolatile memory of the present invention, when being programmed operation, auxiliary grid is applied low-voltage,
Substrate below auxiliary grid can form passage, the pattern injected with source side hot electron, electronics is write floating grid.
When carrying out erasing operation, utilize grid of erasing to data of erasing, make electronics remove via gate dielectric layer of erasing, electronics can be reduced
Through the number of times of tunneling dielectric layer, and then improve reliability.Erase between gate height additionally, the corner portion of floating grid is arranged on,
And the angle of this corner portion is less than or equal to 90 degree, make electric field concentrate by corner portion, can efficient by electronics from floating grid
Pull-out, improves the speed of data of erasing.Threshold voltage after the memory element of the present invention is programmed is between Vcc and 0: deposit
Storage unit threshold voltage after erasing is less than 0.
Last it is noted that various embodiments above is only in order to illustrate technical scheme, it is not intended to limit；Although ginseng
According to foregoing embodiments, the present invention is described in detail, it will be understood by those within the art that: it is the most permissible
Technical scheme described in foregoing embodiments is modified, or the most some or all of technical characteristic is carried out equivalent replaces
Change；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (17)
1. a nonvolatile memory, it is characterised in that including:
First memory element, is arranged in substrate, described first memory element, including:
Stacked structure, including being sequentially arranged described suprabasil gate dielectric layer, auxiliary grid, insulating barrier and grid of erasing
Pole；
First floating grid and the second floating grid, be separately positioned on the sidewall of the both sides of described stacked structure, and described
The top of one floating grid and described second floating grid is respectively provided with corner portion, grid of erasing described in described corner portion is neighbouring, and
Described corner portion height is erased between gate height described in falling within；
First tunneling dielectric layer and the second tunneling dielectric layer, be separately positioned between described first floating grid and described substrate
And between described second floating grid and described substrate；
First gate dielectric layer and second of erasing is erased gate dielectric layer, be separately positioned on described in grid of erasing first floating with described
Between grid and described in erase between grid and described second floating grid；
First supplementary gate dielectric layer and the second supplementary gate dielectric layer, be separately positioned on described auxiliary grid first floating with described
Between grid and between described auxiliary grid and described second floating grid；
First doped region and the second doped region, be separately positioned in described substrate, wherein said first floating grid, described
Stacked structure is connected, with described second floating grid, the described substrate being arranged between described first doped region and described second doped region
On；
First control gate and the second control gate, be separately positioned on described first floating grid and described second floating grid
Extremely go up；And
Dielectric layer between grid, is arranged between described first control gate and described first floating grid and described second control
Between grid and described second floating grid.
Nonvolatile memory the most according to claim 1, it is characterised in that also include:
First bit line and the second bit line, be arranged in parallel on the substrate, and wherein said first doped region is electrically connected to institute
Stating the first bit line, described second doped region is electrically connected to described second bit line.
Nonvolatile memory the most according to claim 1, it is characterised in that the most also include the second storage list
Unit, described second memory element is arranged on the substrate, the structure of described second memory element and described first memory element
Structure is identical, shares described second doped region.
Nonvolatile memory the most according to claim 3, it is characterised in that also include:
First bit line and the second bit line, be arranged in parallel on the substrate, wherein said first memory element and described second
Described second doped region that memory element shares is electrically connected to described first bit line, described the first of described first memory element
Doped region is respectively and electrically connected to described second bit line with the 3rd doped region of described second memory element.
Nonvolatile memory the most according to claim 3, it is characterised in that described first memory element and described second
Memory element shares described first control gate or described second control gate, and described first control gate or described second controls
Grid fills up the opening between described first memory element and described second memory element.
Nonvolatile memory the most according to claim 1, it is characterised in that the most also include that the 3rd storage is single
Unit, described 3rd memory element is arranged on the substrate, the structure of described 3rd memory element and described first memory element
Structure is identical, and described 3rd memory element is serially connected by described first doped region with described first memory element, shares described
Auxiliary grid, described in erase grid, described first control gate and described second control gate, and described first control gate and
Described second control gate is filled up between described first memory element and described 3rd memory element.
Nonvolatile memory the most according to claim 6, it is characterised in that also include:
First bit line, the second bit line and the 3rd bit line, be arranged in parallel on the substrate, wherein concatenates described first and deposits
Storage unit is electrically connected to described second bit line with described first doped region of described 3rd memory element, and described first storage is single
Described second doped region of unit is electrically connected to described first bit line, and the 3rd doped region of described 3rd memory element is electrically connected with
To described 3rd bit line.
Nonvolatile memory the most according to claim 1, it is characterised in that described first tunneling dielectric layer is additionally arranged at
Between described first control gate and described first doped region；Described second tunneling dielectric layer is additionally arranged at described second control gate
And between described second doped region.
9. the nonvolatile memory stated according to claim 1, it is characterised in that described first supplementary gate dielectric layer is with described
The thickness of the second supplementary gate dielectric layer is erased more than or equal to described first gate dielectric layer and the described second thickness erasing gate dielectric layer
Degree.
Nonvolatile memory the most according to claim 1, it is characterised in that described first supplementary gate dielectric layer and institute
The material stating the second supplementary gate dielectric layer includes silicon oxide/silicon nitride, silicon oxide/silicon nitride/silicon oxide or silicon oxide.
11. nonvolatile memories according to claim 1, it is characterised in that the material of described insulating barrier includes oxidation
Silicon.
12. nonvolatile memories according to claim 1, it is characterised in that between described grid, the material of dielectric layer includes
Silicon oxide/silicon nitride/silicon oxide or nitridation silicon/oxidative silicon or the material of other high-ks k ＞ 4.
13. nonvolatile memories according to claim 1, it is characterised in that described first tunneling dielectric layer is with described
The material of the second tunneling dielectric layer includes silicon oxide, the thickness of described first tunneling dielectric layer and described second tunneling dielectric layer between
Between 60 angstroms to 200 angstroms.
14. nonvolatile memories according to claim 1, it is characterised in that the material of described gate dielectric layer includes oxygen
SiClx, the thickness of described gate dielectric layer is less than or equal to the thickness of described first tunneling dielectric layer with described second tunneling dielectric layer.
15. nonvolatile memories according to claim 1, it is characterised in that described first erases gate dielectric layer and institute
Stating the second material erasing gate dielectric layer and include silicon oxide, the described first gate dielectric layer of erasing is erased gate dielectric layer with described second
Thickness is between 100 angstroms to 180 angstroms.
16. nonvolatile memories according to claim 1, it is characterised in that described corner portion angle is less than or equal to
90 degree.
17. nonvolatile memories according to claim 1, it is characterised in that after described first memory element is programmed
Threshold voltage between Vcc and 0: described first memory element threshold voltage after erasing be less than 0.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108695332A (en) * | 2018-05-18 | 2018-10-23 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory and forming method thereof, control method |
| WO2022071982A1 (en) * | 2020-09-30 | 2022-04-07 | Silicon Storage Technology, Inc. | Split-gate non-volatile memory cells with erase gates disposed over word line gates, and method of making same |
| WO2022071979A1 (en) * | 2020-09-30 | 2022-04-07 | Silicon Storage Technology, Inc. | Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same |
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