CN101410979A - Scalable flash EEPROM memory cell with notched floating gate and graded source region - Google Patents
Scalable flash EEPROM memory cell with notched floating gate and graded source region Download PDFInfo
- Publication number
- CN101410979A CN101410979A CNA2004800188439A CN200480018843A CN101410979A CN 101410979 A CN101410979 A CN 101410979A CN A2004800188439 A CNA2004800188439 A CN A2004800188439A CN 200480018843 A CN200480018843 A CN 200480018843A CN 101410979 A CN101410979 A CN 101410979A
- Authority
- CN
- China
- Prior art keywords
- floating gate
- substrate
- insulating material
- channel region
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.
Description
That the application requires to propose on July 2nd, 2003, provisional application number is the priority of 60/484,882 U.S. Patent application.
Technical field
The present invention relates to electric erasable and read-only nonvolatile memory able to programme (EEPROM) unit or more specifically to quickflashing EEPROM.The invention still further relates to the memory array of this EEPROM memory cell of the arranged in form that comprises that some row and columns with this memory cell are matrix.
Background technology
A kind of flash memory device of prior art is overlapped grid flash EEPROM, and wherein single stack gate transistor is formed memory cell.It is programmed for traditional UV can wipe EPROM, uses and injects thermionic mechanism to floating gate, and wipe from the floating gate to the source region by Fowler-Nordheim tunnel effect mechanism.This device has following shortcoming: it is too high that (1) wipes sensitivity, even wherein be cancelled selected and when earth potential is biased when the grid of memory cell, memory cell can be erased to a negative threshold voltage, thereby make memory cell be in conduction state, and (2) high program current, it need come by independent supply voltage memory cell is programmed, for example referring to United States Patent (USP) 4698787.
Second type of flash memory device uses cuts apart the grid configuration.This configuration has eliminated that to wipe sensitivity too high, even this is that the conduction in the raceway groove need be setovered at the control gate on another part raceway groove because floating gate is crossed to be wiped.Yet configuration is identical with stack gate with erase mechanism in programming.The shortcoming of this configuration is that it has increased the size of memory cell and has disposed the requirement that it bears alignment sensitivity possibly owing to cut apart grid.For example referring to United States Patent (USP) 5029130.
Another type flash memory cell is used so-called source side injection technique, thereby it minimizes hot electron programming electric current chip power and presses multiplier to can be used for providing from single 5 or enough program currents of 3.3V power supply.Yet the structure of these memory cell still may have following shortcoming: (1) alignment sensitivity, (2) lack scalability and (3) need be compromise between cell size and coupling ratio.For example referring to United States Patent (USP) 5194925.
United States Patent (USP) 5303187,4462090 and 5280446 discloses has the single transistor memory cell of selecting grid, control gate, source electrode and four terminals that drain.Yet disclosed memory cell is wiped by electron tunnel (capable referring to the 5th hurdle 64-68) from the floating gate to the substrate in the United States Patent (USP) 5303187.Because bigger electric capacity between floating gate and substrate and since the weak coupling ratio this be unwelcome.Therefore, need a kind of higher voltage to wipe.In addition, need negative voltage to be provided for the electromotive force of the erase operation of n type memory cell.This just need provide the processing of high PMOS junction breakdown voltage and high field isolation threshold voltage and the low effect of PMOS transistor own, so that this circuit can provide the negative voltage of enough amplitudes to obtain necessary erase operation.
United States Patent (USP) 4462090 and 5280446 all discloses and has been used to select the grid of cutting apart of grid to dispose.Be used to select this of grid to cut apart the grid configuration because misalignment may cause punch through sensitivity.
United States Patent (USP) 5338952 discloses a kind of grid memory cell of cutting apart, and it has the floating gate that forms pad, and this pad deployment is at the adjacent of selecting grid and below control gate.Yet utilize this capacitive coupling that has not enough quantity between floating gate and the control gate that is configured in.
At last, above-mentioned design may suffer snowslide or bring to puncture during erase operation, and wherein the source knot is biased the higher electromotive force that compares.Puncture voltage critically rely on the knot curvature and the knot edge oxide thickness.Along with memory cell is constantly dwindled dimensionally, because the minimizing of thermal cycle in scalable technology, the optimization degree of curvature is restricted.
Summary of the invention
The present invention is a kind of electric erasable and programmable memory device, the substrate that comprises the first conductive type semiconductor material, what form in substrate has certain distance at interval and have first and second zones of second conduction type that is different from first conduction type, has channel region therebetween, the conduction that is formed on the channel region first portion and insulate is with it selected grid, conductive floating gate with bottom surface, it is configured on first area and the channel region second portion and by insulating material and insulate with it, wherein recess is formed on the bottom surface, have the edge that aligns with the edge, first area or be configured in edge on the first area, and conductive control grid has the first that is configured in the floating gate adjacent.
Another aspect of the present invention, electric erasable and programmable memory device comprise: the substrate of the first conductive type semiconductor material, what form in substrate has certain distance at interval and have first and second zones of second conduction type that is different from first conduction type, has channel region therebetween, wherein channel region comprises adjacent to the first of first area and adjacent to the second portion of second area, the conduction that is configured on the channel region second portion and insulate is with it selected grid, be used to control the conductivity of channel region second portion, conductive floating gate with the first that is configured on the first area fully and insulate with it, be used to produce the fringing field of control channel region first portion conductivity, wherein floating gate first comprises and is configured on the first area fully and the bottom surface of insulation with it and stretch out from the bottom surface and away from a side of substrate, and conductive control grid, it has the first with the adjacent setting of floating gate.
Another aspect of the present invention is a kind of method of making storage device on the Semiconductor substrate of first conduction type, be included in to form on the substrate and have certain distance first and second zones at interval, it has second conduction type that is different from first conduction type, wherein channel region is limited in the substrate between first and second zones, the conduction that forms on channel region first portion and insulate is with it selected grid, formation has the conductive floating gate of bottom surface, it is configured on first area and the channel region second portion and insulation with it, wherein the formation of floating gate comprises, on the bottom surface, form recess, this bottom surface has the edge that aligns with the edge, first area or is arranged on edge on the first area, and the formation conductive control grid, it has the first with the adjacent setting of floating gate.
A further aspect of the invention is the method for storage device, comprise: what form in substrate has certain distance at interval and have first and second zones of second conduction type that is different from first conduction type, wherein channel region is limited in the substrate between first and second zones, and wherein channel region comprises first adjacent with the first area and the second portion adjacent with second area, the selection grid of the conduction that on the channel region second portion, forms and insulate with it, be used to control the conductivity of channel region second portion, formation has the conductive floating gate of the first that is arranged on the first area fully and insulate with it, be used to produce the fringing field of control channel region first portion conductivity, wherein floating gate first comprises and is arranged on the first area fully and the bottom surface of insulation with it and stretch out from the bottom surface and away from a side of substrate, and the formation conductive control grid, it has the first with the adjacent setting of floating gate.
By reference specification, claims and accompanying drawing, other target of the present invention and feature will become obvious.
Description of drawings
Accompanying drawing 1A has showed the treatment step that is used to make memory cell of the present invention successively to the cross-sectional view strength of the substrate of 1H.
The schematic cross sectional view of accompanying drawing 2 memory cell of the present invention.
Accompanying drawing 3A has showed first alternative embodiment of the treatment step that is used to make memory cell of the present invention successively to the cross-sectional view strength of the substrate of 3C.
Accompanying drawing 4A has showed second alternative embodiment of the treatment step that is used to make memory cell of the present invention successively to the cross-sectional view strength of the substrate of 4C.
Accompanying drawing 5A has showed the 3rd alternative embodiment of the treatment step that is used to make memory cell of the present invention successively to the cross-sectional view strength of the substrate of 5D.
Accompanying drawing 6A has showed the 4th alternative embodiment of the treatment step that is used to make memory cell of the present invention successively to the cross-sectional view strength of the substrate of 6C.
Embodiment
Memory cell is made
Accompanying drawing 1A illustrates manufacture method according to non-volatile memory cells of the present invention to 1E.Parameter described below depends on design rule and process technology generation.What it will be appreciated by those skilled in the art that is that the present invention is not limited to any concrete process technology generation, also is not limited to the particular value of any technological parameter described below.In addition, following method is described the formation that concentrates on single memory cell, and in fact a large amount of this memory cell form simultaneously, and it joins end to end at the active area of arranging with row and expands.The row of this memory cell are that the row by insulating regions separate, and formation wherein is well known in the art.
It should be noted that, as used herein, term " top " and " ... on " all comprise " and directly exist ... on " (do not have intermediate materials, element or place therebetween interval) and " exist indirectly ... on " (intermediate materials, element or place be arranged with therebetween at interval).Similarly term " adjacent " comprises " direct neighbor " (interval that does not have intermediate materials, element or be provided with) and " adjacent indirectly " (intermediate materials, element or the interval that is provided with) therebetween therebetween.For example, " above substrate " forms element and can comprise directly on substrate and do not have intermediate materials/element to form element betwixt, and is connected on the substrate, has one or more intermediate materials/elements betwixt and form element.
Accompanying drawing 1A illustrates the cross-sectional view strength of Semiconductor substrate (or substrate trap) 10, and it is P conduction type and being known in the art preferably.Ground floor insulating material 12, preferably silicon dioxide (hereinafter referred to as " oxide ") is formed on the substrate 10 by the known technology such as oxidation or oxidate (for example chemical vapour desposition or CVD), and it has about 30
The degree of depth.One deck polysilicon 14 (hereinafter referred to as " polysilicon ") is formed at the top of oxide layer 12.The formation of polysilicon layer 14 can produce by known processing, such as low pressure chemical vapor deposition or LPCVD.Polysilicon mixes by in-situ method or by traditional injection fully.In a preferred embodiment, polysilicon layer 14 has about 1000
The degree of depth, and be injected into As (3.0E15 dosage, 25KeV injects energy).Second layer insulating material 16 is formed on the polysilicon layer 14, preferably handles by the HTO oxidate.On oxide layer 16, apply suitable photo anti-corrosion agent material then, and carry out masks to remove photo anti-corrosion agent material (striding across the striped 20 that the line direction of a plurality of row of active area extends) from some masks area selectively.Wherein remove photo anti-corrosion agent material, in striped 20, use standard etch technology (being anisotropic etch processes) that the lower part of oxide layer 16 and polysilicon layer 14 is etched away.Wherein do not remove photoresist, keep 14 layers of oxide skin(coating) 16 and polysilicons.Remove remaining photo anti-corrosion agent material, produce the structure shown in accompanying drawing 1A.
Sidewall surfaces along remaining structure forms insulation spacer then.Being formed on of pad is known in the art, and be included in a kind of material of deposition on the profile of structure, carry out anisotropic etch processes subsequently, remove this material from the horizontal surface of this structure whereby, and on the surface of the vertical direction that remains in this structure that this material can't harm in a large number.In this case, synthetic pad forms as follows.Oxide skin(coating) 22 is formed on this structure, and silicon nitride (" nitride ") layer 24 is formed on the oxide layer 22, shown in accompanying drawing 1B.Carry out the anisotropic nitride etching, be controlled anisotropy oxide etch subsequently, nitride except that synthetic pad 26 (nitride layer 24 that comprises the shim-like on the L shaped shape oxide layer 22) and great majority (but preferably not every) oxide layer 22/24 are removed, shown in accompanying drawing 1C.Use anisotropic etching to avoid destruction to substrate by the oxide of not exclusively removing on the substrate 10 12 (and some possible oxides 22).
Use nitride etch to remove remaining nitride 24.Part to this structure is carried out mask, and injects to form first area (being the source region) 30 in substrate 10 by the whole surface of this structure being carried out suitable ion then.Source region 30 has the conduction type (for example N mixes) that is different from substrate 10 (for example P mixes).In this case, the source region is that N+ mixes.Wet etching is then used in the oxide 12/22 of removing any exposure, forms the oxidizing process of oxide layer 32 subsequently on the expose portion of substrate.The structure that produces is shown in accompanying drawing 1D.
Then by form one deck polysilicon 36 (shown in accompanying drawing 1E) on this structure, polysilicon pad 34 is formed at the adjacent of oxide layer 22, carries out the anisotropy etching polysilicon subsequently to stay polysilicon pad 34.Carry out suitable implantation step with the expansion first area 30 in case they by classification to prevent junction breakdown, it is shown in accompanying drawing 1F.
Ensuing masks protection is positioned at those polysilicon pads 34 with source region 30 adjacent settings.Then using the etching polysilicon step to remove does not have the polysilicon pad 34 of protection.Oxide etching is then used in the expose portion of removing oxide 22 and 32.Insulating barrier 40 be formed at then on this structure (ONO layer preferably for example, it comprises three thin layers of the insulating material of successive sedimentation, such as oxide, nitride and oxide, it has respectively～60
,～70
,～60
Thickness).The thick-layer of polysilicon is deposited on this structure (1600 then
) the top.The polysilicon of ensuing masks protection deposition is positioned at those parts around the source region 30.The part that not have protection of the polysilicon of deposition is removed in the etching polysilicon step, is left at the polysilicon layer 42 of layout on the source region 30 and extends upward and on oxide layer 22 and 16.Then this total being carried out suitable ion injects with the exposed portion formation second area (being the drain region) 38 at substrate 10.Insulation spacer 48 is formed on the substrate adjacent with polysilicon/oxide skin(coating) 14/16 then, carries out another ion subsequently and injects with expansion second area 38, make they by classification to prevent junction breakdown.Final structure is shown in accompanying drawing 1G and 1H.
The final structure of memory cell of the present invention comprises the channel region 44 that is limited to source electrode 30 and drains the substrate between 38.Polysilicon layer 14 forms the selection grid of memory cell, and it is arranged in the first of channel region 44 and insulation with it.Polysilicon pad 34 forms the floating gate of memory cell, and it is arranged on the second portion of channel region 44 and insulation with it.Polysilicon layer 42 forms the control gate of memory cell.
Memory cell operation
Operating in the U.S. Patent No. 5912843 of three polysilicon memory cell described, and incorporates into here and with reference to its disclosed content.
Memory cell erase or write " 1 "
In order to write " 1 " or to wipe memory element 1, it causes memory element 1 to be in conduction state, to source electrode apply a high voltage (～12V).Drain electrode, selection grid and control gate all are positioned at earth potential.Because floating gate and select between the grid and the coupling of the high capacitance between floating gate and the control gate, and owing to very little capacitive coupling between source region and the floating gate, and because overlapping between source region and the floating gate, the applied voltage of high percentage has appearred between source electrode and floating gate.This causes electronics to be tunneling to source electrode by the Fowler-Nordheim tunneling mechanism from floating gate, and is not to substrate, stays the floating gate with relative positive charge.
For the supply voltage of 12V, knot can produce the tunneling mechanism of taking band in the source, and it will strengthen the amplitude of source current.Because chip power presses multiplier to be generally used for providing high voltage, will need a more sane voltage multiplier design so take the tunnel current of band to.
The possibility mode of eraseable memory unit be to control gate apply back bias voltage (～-8 to-10V), and select grid to remain on earth potential or remain on the back bias voltage same with control gate, and only promote source voltage to 5V or approach Vcc, such as 6-7V.The advantage of this method is that source voltage is in lower potential now.By reducing source voltage, for higher electric current deliverability, it allows directly to provide source voltage from the Vcc power supply or from voltage multiplier by pump stage still less.
Memory cell is programmed or is write " 0 "
In order to write " 0 " to memory cell, it causes memory cell to be in non-conductive state, applies a high pressure (～5 to 8V) to source electrode.Apply second high pressure (～10 to 12V) to control gate.Drain voltage remains on 0 V or little bias voltage (～0.3 to 1.0 volt).Little voltage is applied to the selection grid, and this voltage just in time is higher than the transistorized threshold voltage vt of selecting the grid below (for example Vt+ Δ V, wherein Δ V～0.1V is to .5V).Select the voltage of grid to cause transistor, be about a microampere magnitude from the little electric current of drain-to-source conduction.Owing to be applied to the high pressure of control gate and source region, the current potential at floating gate place is high.The high potential of floating gate will cause being drawn high of channel region below the floating gate.The surface potential of tight substrate below the floating gate left side edge be determined as be lower than floating gate voltage (～8V) about one volt.Owing to select grid to be biased just above threshold voltage, as mentioned above, select the channel potential below the grid to approach drain voltage, it is 0V or little bias voltage.Therefore approximately the voltage difference of 8V is formed on the zone and the zone in the tight raceway groove below floating gate in the raceway groove below selecting grid tightly.Tightly the zone of the raceway groove below selecting grid and tight below floating gate the gap width between the zone of raceway groove approximately be 500
Therefore form 1.5 to 4MV/cm electric field, it is enough high so that cause hot electron to be injected into floating gate from raceway groove, and this makes floating gate electronegative.
Memory element reads
At last, in order to read memory element, apply earth potential to the source region.The voltage that reads of approximate volt puts on drain region and Vcc voltage (for example be used for 0.18 μ m technology～1.8 volts) and puts on the selection grid.If floating gate is positive charge (is floating gate be discharge electronics), the channel region that is located immediately at so below the floating gate is opened.When selecting grid to rise to reading potential, directly the channel region below the selection grid also is opened.Therefore, whole channel region will be opened, and make electronics flow to the drain region from the source region.This conduction state will be defined as the memory erase one state.
On the other hand, if floating gate is electronegative, directly a little less than the quilt of the channel region below the floating gate, opens or close fully.Even, have little or no electric current and flow through raceway groove when selecting grid and drain region to rise to reading potential.In this case, compare electric current with one state be very little or do not have electric current at all.This non-conductive state will be defined as memory program " 0 " state.
Alternative embodiment
Accompanying drawing 3A illustrates an alternative embodiment to 3C, and wherein floating gate extends upward and selecting to be used to strengthen capacitive coupling on the grid.This is by formation layers of additional materials 50 (for example nitride) on the oxide in structure shown in accompanying drawing 1A 16, and the suitable photo anti-corrosion agent material 52 of formation is finished on layer 50, shown in accompanying drawing 3A.Next be plasma etching treatment (ashing), it removes the exposed surface of photoresist 52.This etching process causes reducing the width (for example about 300 of photoresist 52
), make the part of nitride layer 50 expose.Ensuing nitride etch is removed the exposed side part of nitride layer 50, and this exposed side part is no longer protected by photoresist 52, reduces the width of nitride layer effectively, shown in accompanying drawing 3B.
After removing photoresist 52,1B carries out above-mentioned residue treatment step to produce the structure shown in the accompanying drawing 3C to 1H with reference to the accompanying drawings.Utilize this embodiment, have the coupling that strengthens between control gate and floating gate, it is combined with the recess 46 that is used for bigger puncture voltage.
Second alternative embodiment
The insulation that is used to strengthen between floating gate and the edge, source region at floating gate formation recess is not limited to the floating gate that forms as pad.For example, the United States Patent (USP) 6057575 of reference in the lump here (' 575 patent) illustrates floating gate and forms material layer.Shown in the accompanying drawing 1a of ' 575 patents, insulating material is formed at selects grid top and adjacent with it, and floating gate is formed on the insulating material.Can revise this embodiment, form the puncture voltage that recess increases device in the floating gate to be included in.
Accompanying drawing 4A illustrates modification to the embodiment of the accompanying drawing 1a of 575 patents to 4C.After selecting grid 60 to be formed on the insulating barrier 62, insulating barrier 64 is formed on this structure, comprises wherein the laterally L type part of adjacent layer 60/62.Nitride spacer 24 is formed at the adjacent of the L type part 22 of layer 64 then with the same manner as mentioned above, and shown in accompanying drawing 4A.After removing nitride 24, one deck insulating material 64 is formed on this structure, succeeded by form floating gate 66 on insulating material 64, shown in accompanying drawing 4B.Form another insulating barrier 68 and control gate 70 according to the treatment step of describing in the patent of ' 575 then, produce the final structure shown in the accompanying drawing 4C.Floating gate 66 comprises the protuberance 66a of the recess 70a in the lower surface of control gate 70.
The 3rd alternative embodiment
Accompanying drawing 5A illustrates the 3rd alternative embodiment to 5D, and wherein recess 46 does not form in floating gate, and opposite floating gate is arranged on the source region fully.Begin with the structure shown in accompanying drawing 1A, insulation spacer 80 laterally forms (depositing and etching by using oxide 16 to insulate as etching stopping) adjacent to polysilicon 14 and oxide 16, shown in accompanying drawing 5A.Oxide layer 32 is formed on the expose portion of substrate, is preferably undertaken by oxidation.Suitable ion injects and is used for forming first (source electrode) zone 30.Then, polysilicon pad 82 laterally forms (by polysilicon deposition and etching) adjacent to insulation spacer 80.Carry out that second ion injects with expansion first area 30 so that their classifications to prevent junction breakdown, shown in accompanying drawing 5B.1G carries out and remains treatment step as mentioned above to finish this structure with reference to the accompanying drawings, and it is shown in accompanying drawing 5C.
Accompanying drawing 5D illustrates the conducting element of final structure, wherein floating gate 82 is arranged on the source region, the 44a of first of channel region 44 passes through to select grid 14 by vertically superposed (and Be Controlled), and the second portion 44b of channel region 44 laterally is departed from, and not vertically overlapped by floating gate 82.Yet floating gate 82 can apply enough control to open (conduction) and to close the second portion 44b of (non-conductive) channel region second portion 44b (promptly passing through fringing field).For those application that exist restriction on the voltage that is applied to the source region, this embodiment has superiority.
The 4th alternative embodiment
Accompanying drawing 6A illustrates the 4th alternative embodiment to 6C, and it is similar to the 3rd change embodiment, but wherein non-pad floating gate has be arranged on fully on the source region one than lower part.Begin (but having wide polysilicon/oxide skin(coating) 14/16) with structure shown in accompanying drawing 1A, insulation spacer 90 laterally forms (by using the insulation deposition such as nitride adjacent to polysilicon 14 and oxide 16, use oxide 16 to carry out etching afterwards as etching stopping), shown in accompanying drawing 6A.Oxide etch is used for removing the expose portion of oxide layer 12, forms oxide layer 32 subsequently on the expose portion of substrate, is preferably undertaken by oxidation.Suitable ion injects and is used for forming first (source electrode) zone 30, shown in accompanying drawing 6B.Then, polysilicon layer 92 is formed on this structure, and insulating barrier 94 is formed on the polysilicon layer 92 subsequently, and then polysilicon layer 96 is formed on the insulating barrier 94., carry out ion injection for the second time and prevent voltage breakdown after the end with aligning polysilicon layer 92/96 at suitable masks and polysilicon/insulation etching with expansion first area 30.Drain region 38 can form by aforesaid similar fashion, produces the structure shown in the accompanying drawing 6C.
Layer 92 is formed floating gate, and layer 96 is formed control gate.Floating gate 92 have on oxide layer 32 and source region 30 extend than lower part 92a.Only the top 92b of floating gate 92 is not orthogonal on the source region 30.Yet, floating gate can apply enough control to the direct part 44b (promptly passing through fringing field) of the channel region below insulation spacer 90 than lower part 92a, to open (conduction) and to close the part 44b of (non-conductive) channel region.
Be understandable that the present invention is not limited to embodiment aforesaid and that illustrate herein, but comprises any and all changes that belong in the accessory claim scope.For example, aforesaid material, processing and several examples only are exemplary, and should not be considered to limit claim.In addition, what accessory rights required and specification can obviously be seen is that not all method step all need be carried out according to the order accurately that illustrates or require, but allows the correct any order that forms nonvolatile memory cell of the present invention.At last, the simple layer material can be formed this material of multilayer or materials similar, and vice versa.
Claims (30)
1. electric erasable and programmable memory device comprise:
The substrate of the semi-conducting material of first conduction type;
What form in substrate has certain distance at interval and have first and second zones of second conduction type that is different from first conduction type, has channel region therebetween;
Be formed at the conduction that also insulate with it on the first of channel region and select grid;
Conductive floating gate with bottom surface, described bottom surface is arranged on the second portion of first area and channel region and by insulating material insulate with it, wherein recess is formed on the described bottom surface, and this bottom surface has the edge that the edge with the first area aligns or has the edge that is arranged on the first area; And
Conductive control grid has the first that is provided with adjacent to floating gate.
2. the device of claim 1, wherein floating gate comprises and is arranged on the first on the recess and second portion on the recess is not set, and wherein with the thickness of the insulating material part of the first of floating gate and insulated substrate greater than with the second portion of floating gate and the insulating material thickness partly of insulated substrate.
3. the device of claim 2, wherein floating gate comprises and extending upward and in the third part of selecting on the grid.
4. the device of claim 1, wherein floating gate forms the pad on the insulating material.
5. the device of claim 1, wherein the first of control gate is laterally adjacent to the floating gate setting, and wherein control gate comprises and extending upward and the second portion on floating gate.
6. the device of claim 5, wherein the first of control gate is set directly on the insulating material that directly is arranged on the first area, and the second portion of control gate is set directly on the insulating material that directly is arranged on the floating gate.
7. the device of claim 5, wherein:
Floating gate is included in the protuberance on the upper surface of floating gate;
Control gate comprises the bottom surface that is formed with second recess on it;
The protuberance of floating gate is in the face of second recess and insulation with it.
8. the device of claim 2, wherein the recess edge comprises usually the part perpendicular to the floating gate bottom surface of substrate surface.
9. electric erasable and programmable memory device comprise:
The substrate of the semi-conducting material of first conduction type;
What form in substrate has certain distance at interval and have first and second zones of second conduction type that is different from first conduction type, has channel region therebetween; Wherein channel region comprises first adjacent with the first area and the second portion adjacent with second area;
Conduction selects grid to be formed on the second portion of channel region and insulation with it, is used to control the conductivity of the second portion of channel region;
Conductive floating gate with the first that is arranged on the first area fully and insulate with it, be used to produce the fringing field of first's conductivity of control channel region, wherein the first of floating gate comprises and is arranged on the first area fully and the bottom surface of insulation with it and stretch out from the bottom surface and away from a side of substrate; And
Conductive control grid has the first that is provided with adjacent to floating gate.
10. the device of claim 9, wherein the side is aimed at the edge of first area.
11. the device of claim 9, wherein floating gate comprises and extending upward and at the second portion of selecting on the grid.
12. the device of claim 9, wherein floating gate forms pad.
13. the device of claim 9, wherein the first of control gate is laterally adjacent to the floating gate setting, and wherein control gate comprises and extending upward and the second portion on floating gate.
14. the device of claim 9, wherein the side of floating gate is usually perpendicular to the surface of substrate.
15. a method of making storage device on the Semiconductor substrate of first conduction type comprises:
On substrate, form and have certain distance at interval and have first and second zones of second conduction type that is different from first conduction type, wherein channel region be limited at first and second area between substrate in;
On the first of channel region, form conduction and select grid and insulation with it;
Formation has the conductive floating gate of bottom surface, this bottom surface is arranged on the second portion of first area and channel region and insulation with it, wherein the formation of floating gate is included in and forms a recess on the bottom surface, and this bottom surface has the edge that aligns with the edge, first area or has the edge that is arranged on the first area; And
Form conductive control grid, it has the first that is provided with adjacent to floating gate.
16. the method for claim 15, wherein the formation of floating gate comprises:
On substrate, form the insulating material of varied in thickness; With
On insulating material, form electric conducting material.
17. the method for claim 16, wherein the formation of floating gate further comprises:
Carrying out anisotropic etching removes with the electric conducting material the pad of electric conducting material that will be on being arranged on insulating material.
18. the method for claim 16, wherein insulating material comprises having the first of thickness greater than the thickness of the second portion of insulating material, and wherein floating gate comprises:
First is arranged in the first of recess and insulating material; With
Second portion is arranged on the second portion of insulating material and not on recess.
19. the method for claim 18, wherein the formation of floating gate comprises and extending upward and in the third part of selecting the floating gate on the grid.
20. the method for claim 15, wherein the formation of control gate comprises:
Form laterally adjacent to the first of the control gate of floating gate and
Formation extends upward and the second portion of the control gate on floating gate.
21. the method for claim 15, wherein:
The bottom surface that the formation of control gate is included in control gate forms second recess; And
The formation of floating gate is included on the upper surface of floating gate and forms protuberance, and wherein the protuberance of floating gate is in the face of second recess and insulation with it.
22. the method for claim 15, wherein the formation at recess edge comprises the part that forms usually perpendicular to the floating gate bottom surface of substrate surface.
23. the method for claim 16, wherein:
The insulating material that forms varied in thickness on substrate comprises:
On substrate, form the synthetic pad of first and second insulating material;
Remove second insulating material, first insulating material is arranged on the substrate;
On substrate and adjacent to the first insulating material place, form the 3rd insulation material layer;
Wherein the thickness of the 3rd insulation material layer is less than the thickness of first insulating material, and wherein floating gate is formed on the 3rd insulating material and first insulating material.
24. the method for claim 23 wherein forms synthetic pad and comprises:
Form first insulation material layer at substrate with along the sidewall of selecting grid;
On first insulation material layer, form second insulation material layer; And
Carrying out anisotropic etching is arranged on substrate and removes adjacent to first and second insulation material layers the pad of first and second insulating material of selection grid removing.
25. a method of making storage device on the Semiconductor substrate of first conduction type comprises:
On substrate, form first and the second area that have the certain distance interval and have second conduction type that is different from first conduction type, wherein channel region be limited at first and second area between substrate in, and wherein channel region comprises the first of adjacent first area and the second portion of adjacent second area;
On the second portion of channel region, form conduction and select grid and insulation with it, be used to control the conductivity of the second portion of channel region;
Formation has the conductive floating gate of the first that is arranged on the first area fully and insulate with it, be used to produce the fringing field of first's conductivity of control channel region, wherein the first of floating gate comprises and is arranged on the first area fully and the bottom surface of insulation with it and stretch out from the bottom surface and away from the side of substrate; And
Form conductive control grid, it has the first that is provided with adjacent to floating gate.
26. the method for claim 25, wherein the edge of side and first area aligns.
27. the method for claim 25, wherein floating gate comprises and extending upward and at the second portion of selecting on the grid.
28. the method for claim 27, wherein the formation of floating gate comprises:
On the first area, form insulating material;
On insulating material, form electric conducting material;
Carrying out anisotropic etching removes with the electric conducting material the pad of electric conducting material that will be on being arranged on insulating material.
29. the method for claim 25, wherein the formation of control gate comprises:
Form laterally adjacent to the control gate first of floating gate and
Formation extends upward and the second portion of the control gate on floating gate.
30. the device of claim 25, wherein the side of floating gate is usually perpendicular to the surface of substrate.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US48488203P | 2003-07-02 | 2003-07-02 | |
| US60/484,882 | 2003-07-02 | ||
| US10/878,099 | 2004-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101410979A true CN101410979A (en) | 2009-04-15 |
Family
ID=40572824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2004800188439A Pending CN101410979A (en) | 2003-07-02 | 2004-06-29 | Scalable flash EEPROM memory cell with notched floating gate and graded source region |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101410979A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800226A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | Polysilicon storage unit |
| CN103794610A (en) * | 2014-01-28 | 2014-05-14 | 北京芯盈速腾电子科技有限责任公司 | Non-volatile memory unit and manufacturing method of non-volatile memory unit |
| CN105575783A (en) * | 2014-10-09 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic apparatus |
| CN106158872A (en) * | 2015-03-31 | 2016-11-23 | 物联记忆体科技股份有限公司 | Nonvolatile memory |
| CN106158870A (en) * | 2015-03-10 | 2016-11-23 | 物联记忆体科技股份有限公司 | Non-volatile Memory And Erasing Method Thereof |
| CN106206588A (en) * | 2015-04-30 | 2016-12-07 | 物联记忆体科技股份有限公司 | Nonvolatile memory |
| CN106684085A (en) * | 2015-11-11 | 2017-05-17 | 联华电子股份有限公司 | Semiconductor element and fabrication method therefor |
| CN111952308A (en) * | 2019-05-15 | 2020-11-17 | 力晶积成电子制造股份有限公司 | Flash memory with auxiliary gate and manufacturing method thereof |
-
2004
- 2004-06-29 CN CNA2004800188439A patent/CN101410979A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800226B (en) * | 2010-03-12 | 2014-02-19 | 上海宏力半导体制造有限公司 | Polysilicon storage unit |
| CN101800226A (en) * | 2010-03-12 | 2010-08-11 | 上海宏力半导体制造有限公司 | Polysilicon storage unit |
| CN103794610B (en) * | 2014-01-28 | 2016-08-17 | 北京芯盈速腾电子科技有限责任公司 | Non-volatile memory cell and manufacture method thereof |
| CN103794610A (en) * | 2014-01-28 | 2014-05-14 | 北京芯盈速腾电子科技有限责任公司 | Non-volatile memory unit and manufacturing method of non-volatile memory unit |
| CN105575783B (en) * | 2014-10-09 | 2018-05-08 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic device |
| CN105575783A (en) * | 2014-10-09 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic apparatus |
| CN106158870A (en) * | 2015-03-10 | 2016-11-23 | 物联记忆体科技股份有限公司 | Non-volatile Memory And Erasing Method Thereof |
| CN106158870B (en) * | 2015-03-10 | 2019-06-11 | 物联记忆体科技股份有限公司 | Non-volatile memory and erasing method thereof |
| CN106158872A (en) * | 2015-03-31 | 2016-11-23 | 物联记忆体科技股份有限公司 | Nonvolatile memory |
| CN106158872B (en) * | 2015-03-31 | 2019-06-11 | 物联记忆体科技股份有限公司 | Nonvolatile memory |
| CN106206588A (en) * | 2015-04-30 | 2016-12-07 | 物联记忆体科技股份有限公司 | Nonvolatile memory |
| CN106206588B (en) * | 2015-04-30 | 2019-08-06 | 物联记忆体科技股份有限公司 | Nonvolatile memory |
| CN106684085A (en) * | 2015-11-11 | 2017-05-17 | 联华电子股份有限公司 | Semiconductor element and fabrication method therefor |
| CN106684085B (en) * | 2015-11-11 | 2021-02-02 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
| CN111952308A (en) * | 2019-05-15 | 2020-11-17 | 力晶积成电子制造股份有限公司 | Flash memory with auxiliary gate and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7199424B2 (en) | Scalable flash EEPROM memory cell with notched floating gate and graded source region | |
| US6621115B2 (en) | Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate | |
| US9892790B2 (en) | Method of programming a continuous-channel flash memory device | |
| US6747310B2 (en) | Flash memory cells with separated self-aligned select and erase gates, and process of fabrication | |
| US7247907B2 (en) | Bidirectional split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing | |
| JP2833627B2 (en) | Memory device | |
| US7928499B2 (en) | Profile of flash memory cells | |
| CN101174652B (en) | Self-aligned method and a memory array made thereby | |
| US20010033513A1 (en) | Split-gate flash cell for virtual ground architecture | |
| US20020182829A1 (en) | Method for forming nitride read only memory with indium pocket region | |
| EP3449486A1 (en) | Split-gate, twin-bit non-volatile memory cell | |
| US6521944B1 (en) | Split gate memory cell with a floating gate in the corner of a trench | |
| US8334558B2 (en) | Method to fabricate self-aligned source and drain in split gate flash | |
| CN101410979A (en) | Scalable flash EEPROM memory cell with notched floating gate and graded source region | |
| US7119396B2 (en) | NROM device | |
| US20060091449A1 (en) | Stacked gate memory cell with erase to gate, array, and method of manufacturing | |
| EP0612108B1 (en) | Double polysilicon EEPROM cell and corresponding manufacturing process | |
| KR100199369B1 (en) | Manufacture of nonvolatile memory cell | |
| CN111916456B (en) | Scalable logic gate non-volatile memory array and method of manufacturing the same | |
| KR100451491B1 (en) | Flash y pyrom cell and its manufacturing method | |
| KR100688489B1 (en) | Non-volatile memory and method of fabricating thereof | |
| KR20010011708A (en) | An nonvolatile memory cell and fabricating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20090415 |