CN106684085B - Semiconductor element and manufacturing method thereof - Google Patents

Semiconductor element and manufacturing method thereof Download PDF

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Publication number
CN106684085B
CN106684085B CN201510764951.0A CN201510764951A CN106684085B CN 106684085 B CN106684085 B CN 106684085B CN 201510764951 A CN201510764951 A CN 201510764951A CN 106684085 B CN106684085 B CN 106684085B
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gate
layer
region
memory
charge storage
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CN106684085A (en
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张原祥
邱意珊
张志谦
杨建军
张文娟
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United Microelectronics Corp
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United Microelectronics Corp
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    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
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    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The manufacturing method of the semiconductor element comprises the following steps. A plurality of selection gates are formed on a memory region of a semiconductor substrate. Two charge storage structures are formed between two adjacent select gates. A source region is formed in the semiconductor substrate, and the source region is formed between two adjacent select gates. An insulating block is formed between the two charge storage structures and over the source region. A storage gate is formed over the insulating block and is connected to the two charge storage structures.

Description

Semiconductor element and manufacturing method thereof
Technical Field
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device with a memory gate and two charge storage structures disposed in correspondence to each other to increase cell density and a method for fabricating the same.
Background
Semiconductor memories are semiconductor devices for storing data in computers or electronic products, and can be broadly classified into volatile memories (vollatile) and nonvolatile memories, wherein the nonvolatile memories are widely used because they have the characteristic of not losing stored data due to power supply interruption. As one of the non-volatile memories, the SONOS memory structure mainly has a nitride layer sandwiched between two oxide layers, the nitride layer is used as an electron or electric charge trapping layer, and the two oxide layers above and below the charge trapping layer are respectively used as a charge tunneling layer and a charge blocking layer. Such an oxide-nitride-oxide (ONO) structure, which is a main element of an information storage device, is disposed on a semiconductor substrate, and a floating silicon gate may be disposed thereon, so that it is called a SONOS memory.
However, as computer microprocessors become more powerful, the need for high capacity and low cost memory increases. To meet this trend and the continuing challenge of high integration in semiconductor technology, memory structures are becoming smaller and more complex. Therefore, how to effectively improve the integration level and the electrical performance through design changes is a goal of the related industries.
Disclosure of Invention
The invention provides a semiconductor element and a manufacturing method thereof, wherein a storage grid electrode and a source electrode region are overlapped and insulated from each other, and the storage grid electrode is simultaneously connected with two charge storage structures, so that the purposes of reducing the size of the element and further improving the integration level of the element are achieved.
According to an embodiment of the present invention, a method for fabricating a semiconductor device includes the following steps. A plurality of selection gates are formed on a memory region of a semiconductor substrate. Two charge storage structures are formed between two adjacent select gates. A source region is formed in the semiconductor substrate, and the source region is formed between two adjacent select gates. An insulating block is formed between the two charge storage structures and over the source region. A storage gate is formed over the insulating block and is connected to the two charge storage structures.
According to an embodiment of the present invention, a semiconductor device is provided, which includes a semiconductor substrate, a plurality of select gates, two charge storage structures, a source region, an insulating block, and a storage gate. The semiconductor substrate has a memory region. The selection gate is disposed on the memory region of the semiconductor substrate. The two charge storage structures are arranged between two adjacent selection gates. The source region is arranged in the semiconductor substrate and is arranged between two adjacent selection gates. The insulating block is arranged on the source region and between the two charge storage structures. The storage grid is arranged on the insulating block and is connected with the two charge storage structures.
Drawings
FIGS. 1 to 17 are schematic views illustrating a method for fabricating a semiconductor device according to a first embodiment of the present invention, wherein
FIG. 2 is a schematic view of a subsequent fabrication process of FIG. 1;
FIG. 3 is a schematic view of the manufacturing method subsequent to FIG. 2;
FIG. 4 is a schematic view of the manufacturing method subsequent to FIG. 3;
FIG. 5 is a schematic view of the manufacturing method subsequent to FIG. 4;
FIG. 6 is a schematic view of the manufacturing method subsequent to FIG. 5;
FIG. 7 is a schematic view of the manufacturing method subsequent to FIG. 6;
FIG. 8 is a schematic view of the manufacturing method subsequent to FIG. 7;
FIG. 9 is a schematic view of the manufacturing method subsequent to FIG. 8;
FIG. 10 is a schematic view of the manufacturing method subsequent to FIG. 9;
FIG. 11 is a schematic view of a subsequent fabrication process of FIG. 10;
FIG. 12 is a schematic view of the fabrication method subsequent to FIG. 11;
FIG. 13 is a schematic view of a subsequent fabrication process of FIG. 12;
FIG. 14 is a schematic view of a subsequent fabrication process of FIG. 13;
FIG. 15 is a schematic view of a subsequent fabrication process of FIG. 14;
FIG. 16 is a schematic view of a subsequent fabrication process of FIG. 15;
FIG. 17 is a schematic view of a subsequent fabrication process of FIG. 16;
FIG. 18 is a diagram of a semiconductor device according to a second embodiment of the present invention;
FIG. 19 is a diagram of a semiconductor device according to a third embodiment of the present invention;
FIG. 20 is a diagram of a semiconductor device according to a fourth embodiment of the present invention;
FIG. 21 is a diagram of a semiconductor device according to a fifth embodiment of the present invention;
fig. 22 is a schematic view of a semiconductor device according to a sixth embodiment of the present invention.
Description of the main elements
10 semiconductor substrate
11 shallow trench isolation
21 gate dielectric layer
22 polysilicon material
23 first mask
31 first oxide layer
32 nitride layer
33 first spacer
34 second oxide layer
35 insulating block
39 charge storage structure
41 interface layer
42 high dielectric constant dielectric layer
42U U type high dielectric constant structure
43 Barrier layer
51 polysilicon layer
52 second mask
53 third mask
55 drain region
55A source/drain region
56 second spacer
57 third spacer
61 self-aligned silicide
62 first silicide
63 second silicide
71 etch stop layer
72 first interlayer dielectric layer
80 metallic conductive material
91 second interlayer dielectric layer
92 contact plug
101-106 semiconductor element
D1 horizontal direction
Perpendicular direction of D2
DG virtual gate
G metal grid
MG storage grid
R1 memory area
R2 logical area
SG selection grid
SL source region
Detailed Description
Please refer to fig. 1 to 17. Fig. 1 to 17 are schematic diagrams illustrating a method for manufacturing a semiconductor device according to a first embodiment of the invention. The method for manufacturing a semiconductor device of the present embodiment includes the following steps. First, as shown in fig. 1, a plurality of select gates SG are formed on a memory region R1 of a semiconductor substrate 10. The semiconductor substrate 10 of the present embodiment may include a silicon substrate (silicon substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon germanium semiconductor substrate (silicon germanium substrate), a silicon carbide substrate (silicon carbide substrate), a silicon-on-insulator (SOI) substrate, and the like, but is not limited thereto. In addition, the semiconductor substrate 10 may have the memory region R1 and the logic region R2 for forming memory cells and logic cells, respectively, and the isolation between the memory region R1 and the logic region R2 may be provided by the shallow trench isolation 11 formed in the semiconductor substrate 10. The select gate SG of the present embodiment may be formed of a polysilicon material 22, and more specifically, a gate dielectric layer 21 and a polysilicon material 22 may be sequentially formed on the semiconductor substrate 10, and then the polysilicon material 22 and the gate dielectric layer 21 are patterned by using the first mask 23 to form the select gate SG, but the invention is not limited thereto. In other embodiments of the present invention, the select gate SG may be formed by other conductive materials and/or other manufacturing methods as required.
Next, as shown in fig. 1 to 4, two charge storage structures 39 are formed between two adjacent select gates SG in a horizontal direction D1. The method for fabricating the charge storage structure 39 of the present embodiment may include, but is not limited to, first, forming a first oxide layer 31 and a nitride layer 32 conformally (conformally) as shown in fig. 1. The first oxide layer 31 is conformally formed on the semiconductor substrate 10, the select gate SG and the first mask 23, and the nitride layer 32 is formed on the first oxide layer 31. Next, as shown in fig. 2, first spacers 33 are formed on the nitride layer 32 on the sidewalls of each of the select gates SG, and then a mask (not shown) is used to remove a portion of the nitride layer 32 between two adjacent select gates SG and between two adjacent first spacers 33, and an ion implantation process is performed to form a source region SL in the semiconductor substrate 10, which may be removed after the source region SL is formed. The source region SL may include, for example, a source line or other shaped source region. The source region SL is formed between two adjacent select gates SG, and the source region SL may correspond to a region between two adjacent select gates SG that is not covered by the nitride layer 32, but is not limited thereto. Then, as shown in fig. 2 to fig. 3, the first spacer 33 and the first oxide layer 31 on the source region SL are removed, and a second oxide layer 34 and an insulating block 35 are formed by an oxidation process. The second oxide layer 34 is conformally formed on the nitride layer 32, and the insulating block 35 is formed between the two charge storage structures 39 and on the source region SL. Due to the difference between the materials of the source region SL and the nitride layer 32 exposed during the oxidation process, the oxidation rate of the source region SL is faster than that of the other nitride layer 32 during the oxidation process, and the insulating block 35 is formed to have a thickness thicker than that of the second oxide layer 34. In other words, the second oxide layer 34 and the insulating block 35 of the present embodiment are formed by the same oxidation process, and the insulating block 35 can be self-aligned (self-aligned) formed on the source region SL, but the invention is not limited thereto. In other embodiments of the present invention, the second oxide layer 34 and the insulating block 35 may be formed by different processes, if necessary.
Then, as shown in fig. 4, a mask (not shown) is used to remove a portion of the first oxide layer 31, the nitride layer 32 and the second oxide layer 34, so as to form two charge storage structures 39 between two adjacent select gates SG, and the mask is removed after the formation of the charge storage structures 39. Each charge storage structure 39 is composed of the remaining first oxide layer 31, nitride layer 32, and second oxide layer 34. The two charge storage structures 39 are respectively located on two sides of the insulating block 35 in the horizontal direction D1, and each charge storage structure 39 can partially cover the first mask 23 in a vertical direction D2 orthogonal to the horizontal direction D1, but not limited thereto. In the present embodiment, the first oxide layer 31, the second oxide layer 34 and the insulating block 35 may be formed of silicon oxide, the nitride layer 32 may be formed of silicon nitride, and the charge storage structure 39 may be regarded as an oxide-nitride-oxide (ONO) structure, but not limited thereto. In other embodiments of the present invention, the charge storage structure 39 may be formed of other suitable materials and/or structures as desired.
Next, as shown in FIG. 5, an interface layer 41, a high-k dielectric layer 42 and a barrier layer 43 are formed on the logic region R2 and the memory region R1 of the semiconductor substrate 10. The barrier layer 43 is formed on the high-k dielectric layer 42, and a portion of the high-k dielectric layer 42 and a portion of the barrier layer 43 are formed between two adjacent select gates SG. The high-k dielectric layer 42 may be selected from hafnium oxide (HfO)2) Hafnium silicate oxide (HfSiO)4) Hafnium silicate oxynitride (HfSiON), aluminum oxide (Al)2O3) Lanthanum oxide (La)2O3) Tantalum oxide (Ta), and a process for producing the same2O5) Yttrium oxide (Y)2O3) Zirconium oxide (ZrO)2) Strontium titanate (SrTiO), strontium titanate oxide (srf)3) Zirconium silicate oxide (ZrSiO)4) Hafnium zirconate (HfZrO) oxide4) Strontium bismuth tantalum oxide (SrBi)2Ta2O9SBT), lead zirconate titanate (PbZr)xTi1-xO3PZT) and barium strontium titanate (Ba)xSr1-xTiO3BST), and the barrier layer 43 may include nickel (Ni), titanium (Ti), titanium nitride (TiN), Tantalum (Ta), Tantalum nitride (TaN), titanium aluminum oxide (tiaio), or other suitable single-layer or multi-layer stacked structure.
Thereafter, as shown in fig. 6 to 7, the high-k dielectric layer 42 and the barrier layer 43 above the source region SL in the portion between two adjacent select gates SG are removed by a mask (not shown), and after the mask is removed, a polysilicon layer 51 is formed on the memory region R1 and the logic region R2, the polysilicon layer 51 on the logic region R2 can be used to form dummy gates (not shown in fig. 6 and 7) in a subsequent manufacturing process, and the polysilicon layer 51 on the memory region R1 partially fills the space between two adjacent select gates SG to form a memory gate (also referred to as a control gate, not shown in fig. 6 and 7) on the insulating block 35 between two adjacent select gates SG. In addition, as shown in fig. 7 to 10, in order to control the heights of the polysilicon layer 51 in the memory region R1 and the polysilicon layer 51 in the logic region R2 to be approximately consistent, the manufacturing method of the present embodiment may include, but is not limited to, the following steps, first, as shown in fig. 7, forming a second mask 52 on the polysilicon layer 51 in the logic region R2, and forming another polysilicon layer 51 (as a sacrificial layer) on the second mask 52 and the polysilicon layer 51 in the memory region R1. Next, as shown in fig. 8, a planarization process, such as a Chemical Mechanical Polishing (CMP) process, is performed to remove portions of the polysilicon layer 51 and/or the second mask 52, the charge storage structure 39, the interface layer 41, the high-k dielectric layer 42 and/or the barrier layer 43 on the first mask 23, so that the top surface of the second mask 52 is substantially flush with the top surface of the polysilicon layer 51 in the memory region R1. After the planarization process, a third mask 53 is formed on the second mask 52, and then an etching process with a lower etching selectivity is performed as shown in fig. 8 to 9 to make the polysilicon layer 51 of the logic region R2 substantially equal to the polysilicon layer 51 of the memory region R1, and the second mask 52 and the third mask 53 are removed.
Then, as shown in fig. 10, a dummy gate DG is formed in the logic region R2 of the semiconductor substrate 10 and a memory gate MG is formed in the memory region R1 of the semiconductor substrate 10 by removing a portion of the polysilicon layer 51, the high-k dielectric layer 42 and the barrier layer 43 through a mask (not shown), and then the mask is removed. The dummy gate DG and the memory gate MG of the present embodiment are formed of the same polysilicon layer (e.g., the polysilicon layer 51 of the present embodiment), so as to achieve the effects of integration and simplification of the manufacturing process, but not limited thereto. In other embodiments of the present invention, the dummy gate DG and the memory gate MG may be formed by different materials and/or other manufacturing processes as required. In the present embodiment, the memory gate MG is formed between two adjacent select gates SG and located on the insulating block 35, and the memory gate MG is connected to the two charge storage structures 39 between the two adjacent select gates SG, so that the memory gate MG can be respectively matched with the two adjacent select gates SG to respectively control the two charge storage structures 39. In other words, two adjacent select gates SG and the corresponding charge storage structures 39 share one memory gate MG and one source region SL, thereby achieving the purpose of reducing the device size and further increasing the device integration. In addition, the cross-sectional shape of the charge storage structure 39 of the present embodiment may preferably include an L-shaped structure, and the storage gate MG may partially overlap with both the charge storage structures 39 in the horizontal direction D1 and the vertical direction D2, but not limited thereto. In the present embodiment, a portion of the high-k dielectric layer 42 and the barrier layer 43 is sandwiched between the memory gate MG and the charge storage structure 39 in the first direction D1, but not limited thereto.
As shown in fig. 11, the method of manufacturing the present embodiment may further include forming a lightly doped region (not shown), a drain region 55 and a source/drain region 55A in the semiconductor substrate 10 at the outer sides of the two select gates SG corresponding to the memory gate MG and in the semiconductor substrate 10 at the two sides of the dummy gate DG, and forming a second spacer 56 and a third spacer 57 at the outer sides of the two select gates SG and the two sides of the dummy gate DG, respectively. Then, as shown in fig. 12, a digging process is performed on the memory gate MG by using a mask (not shown) to remove a portion of the memory gate MG to lower the height of the memory gate MG, and the mask is removed after the digging process. As shown in fig. 13, the manufacturing method of the present embodiment may also optionally include removing a portion of the select gate SG to lower the height of the select gate SG in a specific region, so as to define a corresponding region of a contact structure subsequently formed to be connected to the select gate SG, but the invention is not limited thereto. Next, as shown in fig. 14, after the above-mentioned digging process, self-aligned silicide (salicide) 61 may be formed on the memory gate MG and at least a portion of the select gate SG, a first silicide 62 may be formed in the semiconductor substrate 10 on the outer side of the two select gates SG corresponding to the memory gate MG, and a second silicide 63 may be formed in the semiconductor substrate 10 on the two sides of the dummy gate DG. The salicide 61, the first silicide 62, and the second silicide 63 may be formed together and may include metal silicide, respectively, but the invention is not limited thereto. The salicide 61, the first silicide 62, and the second silicide 63 may be formed separately with different materials and/or manufacturing processes as needed in other embodiments of the invention.
Then, as shown in fig. 15, an etch stop layer 71 and a first interlayer dielectric layer 72 are formed on the memory region R1 and the logic region R2 of the semiconductor substrate 10, and a planarization process is performed to expose the dummy gate DG of the logic region R2. Next, as shown in fig. 15 to 16, the dummy gate DG of the logic region R2 is removed and replaced with a metal gate G, and the method of removing the dummy gate DG and replacing the dummy gate DG with the metal gate G may include a Replacement Metal Gate (RMG) manufacturing process, but is not limited thereto. The metal gate G may include a metal conductive material 80 and a corresponding work function layer (not shown). In the present embodiment, the high-k dielectric layer 42 is formed before the dummy gate DG is removed, so that it can be regarded as a high-k first (high-k first) process, but the invention is not limited thereto. In other embodiments of the present invention, a high-k last process can be optionally used. Then, as shown in fig. 17, a second interlayer dielectric layer 91 is formed to cover the memory region R1 and the logic region R2, and a plurality of contact plugs 92 are formed to penetrate through the second interlayer dielectric layer 91 and the corresponding other material layers to be electrically connected to the memory gate MG, the select gate SG, the drain region 55, and the source/drain regions 55A, respectively. Through the above-described manufacturing method, the semiconductor element 101 shown in fig. 17 can be obtained.
As shown in fig. 17, the semiconductor device 101 of the present embodiment includes a semiconductor substrate 10, a plurality of select gates SG, two charge storage structures 39, a source region SL, an insulating block 35, and a storage gate MG. The semiconductor substrate 10 has a memory region R1. The select gate SG is disposed on the memory region R1 of the semiconductor substrate 10. Two charge storage structures 39 are disposed between two adjacent select gates SG. The source region SL is disposed in the semiconductor substrate 10 and between two adjacent select gates SG. The insulating block 35 is disposed on the source region SL and between the two charge storage structures 39. The storage gate MG is disposed on the insulation block 35, and the storage gate MG is connected to the two charge storage structures 39. Each charge storage structure 39 includes a first oxide layer 31, a nitride layer 32, and a second oxide layer 34. A nitride layer 32 is disposed on the first oxide layer 31, and a second oxide layer 34 is disposed on the nitride layer 32. In addition, the semiconductor device 101 may further include a high-k dielectric layer 42 and a barrier layer 43 disposed on the memory region R1 and the logic region R2 of the semiconductor substrate 10, wherein the barrier layer 43 is disposed on the high-k dielectric layer 42.
In the manufacturing method of the present embodiment, a portion of the high-k dielectric layer 42 and a portion of the barrier layer 43 are disposed between two adjacent select gates SG, and at least a portion of the high-k dielectric layer 42 and at least a portion of the barrier layer 43 are disposed between the storage gate MG and the charge storage structure 39, but the invention is not limited thereto. In other embodiments of the present invention, the high-k dielectric layer 42 and the barrier layer 43 between two adjacent select gates SG may be completely removed as required. In this embodiment, the memory gates MG and the select gates SG may be made of polysilicon, and in this case, the semiconductor device 101 may further include a self-aligned silicide 61 disposed on the memory gates MG and at least one of the select gates SG for effectively electrically connecting the corresponding contact plugs 92. The material characteristics and technical features of the components in the semiconductor device 101 of the present embodiment are described in the above-mentioned manufacturing method, and therefore are not described herein again. It should be noted that, in the semiconductor device 101 of the present embodiment, the memory gates MG and the source regions SL simultaneously correspond to the two charge storage structures 39 and the two select gates SG, so that the device size can be reduced and the device integration can be improved. In addition, since the memory gate MG and the source region SL are overlapped in the vertical direction D2, the insulating block 35 is required to be disposed between the memory gate MG and the source region SL for isolation, and the insulating block 35 and the second oxide layer 34 in the charge storage structure 39 can be formed through the same oxidation process, thereby achieving the effect of further simplifying the manufacturing process.
The following description will mainly describe different parts of each embodiment, and in order to simplify the description, the description will not repeat the description of the same parts. In addition, the same elements in the embodiments of the present invention are denoted by the same reference numerals to facilitate comparison between the embodiments.
Please refer to fig. 18. Fig. 18 is a schematic diagram of a semiconductor device 102 according to a second embodiment of the invention. As shown in fig. 18, the difference from the first embodiment is that in the method for fabricating the semiconductor device 102, the high-k dielectric layer 42 and the barrier layer 43 are formed after the dummy gate (not shown in fig. 18) is removed, so that it can be regarded as a high-k last process. Thus, the high-k dielectric layer 42 in the logic region R2 and at least a portion of the high-k dielectric layer 42 in the memory region R1 may each include a U-shaped high-k structure 42U. In addition, in the present embodiment, the memory gate MG and the metal gate G of the logic region R2 can be formed by the alternative metal gate manufacturing process of the first embodiment, so the memory gate MG of the present embodiment can also include the metal conductive material 80, the metal conductive material 80 of the memory gate MG is surrounded by the U-shaped high-k structure 42U of the memory region R1, and the metal conductive material 80 of the metal gate G is surrounded by the U-shaped high-k structure 42U of the logic region R2.
Please refer to fig. 19. Fig. 19 is a schematic diagram of a semiconductor device 103 according to a third embodiment of the invention. As shown in fig. 19, the difference between the second embodiment and the first embodiment is that the high-k dielectric layer 42 of the present embodiment is formed before the dummy gate (not shown in fig. 19) is removed, but the memory gate MG and the metal gate G of the logic region R2 can be formed by the alternative metal gate manufacturing process of the first embodiment, so that the memory gate MG of the present embodiment can include the metal conductive material 80.
Please refer to fig. 20. Fig. 20 is a schematic view of a semiconductor device 104 according to a fourth embodiment of the invention. As shown in fig. 20, the difference between the second embodiment and the above-mentioned embodiment is that the select gate SG and the metal gate G of the logic region R2 are formed by the alternative metal gate manufacturing process of the first embodiment, so that the select gate SG comprises a metal conductive material 80, and the metal conductive material 80 of the select gate SG is surrounded by the U-shaped high-k structure 42U of the memory region R1. In other words, the select gate SG of the memory region R1 of the semiconductor device 104 of the present embodiment may also include a metal gate structure, thereby avoiding the depletion and tunneling that may occur when a polysilicon material is used to form the select gate SG, which is a positive benefit for the scaling of the memory device.
Please refer to fig. 21. Fig. 21 is a schematic view of a semiconductor device 105 according to a fifth embodiment of the invention. As shown in fig. 21, the difference between the fourth embodiment and the fourth embodiment is that the memory gate MG, the select gate SG and the metal gate G of the logic region R2 of the present embodiment can be formed by the alternative metal gate manufacturing process of the first embodiment, so that the memory gate MG and the select gate SG can respectively include the metal conductive material 80, and the metal conductive material 80 of the select gate SG and the metal conductive material 80 of the memory gate MG can also be respectively surrounded by the U-shaped high-k structure 42U of the memory region R1.
Please refer to fig. 22. Fig. 22 is a schematic view of a semiconductor device 106 according to a sixth embodiment of the invention. As shown in fig. 22, the difference from the fifth embodiment is that the high-k dielectric layer 42 and the barrier layer 43 may not be disposed between the two charge storage structures 39, so that the memory gate MG can directly contact the two corresponding charge storage structures 39.
In summary, the semiconductor device and the manufacturing method thereof of the present invention overlap and insulate the memory gate and the source region, and connect the memory gate to the two charge storage structures simultaneously, thereby achieving the purpose of reducing the device size and further improving the device integration. In addition, the insulating block for isolating the memory gate from the source region can be formed together with the second oxide layer in the charge storage structure by the same oxidation process, thereby further simplifying the process. The memory grid or/and the selection grid of the memory area can also be manufactured by the same alternative metal grid manufacturing process with the metal grid of the logic area according to requirements, so that the effects of simplifying the manufacturing process, improving the element performance and the like are achieved.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Claims (17)

1. A method for manufacturing a semiconductor element comprises the following steps:
forming a plurality of selection gates on a memory region of a semiconductor substrate;
forming two charge storage structures between two adjacent select gates;
forming a source region in the semiconductor substrate, wherein the source region is formed between the two adjacent select gates;
forming an insulating block between the two charge storage structures and on the source region; and
forming a storage gate over the insulating block, wherein the storage gate is connected to the two charge storage structures,
wherein each of the charge storage structures comprises:
a first oxide layer;
a nitride layer formed on the first oxide layer; and
a second oxide layer formed on the nitride layer, wherein the second oxide layer and the insulating block are formed by the same oxidation process,
wherein the source region is formed after the first oxide layer and the nitride layer and before the second oxide layer.
2. The method for manufacturing a semiconductor element according to claim 1, further comprising:
a dummy gate is formed on a logic region of the semiconductor substrate.
3. The method of claim 2, wherein the dummy gate and the memory gate are formed of a polysilicon layer.
4. The method for manufacturing a semiconductor element according to claim 3, further comprising:
performing a tunneling process on the storage gate; and
after the drive-in process, a self-aligned silicide is formed on the memory gate.
5. The method for manufacturing a semiconductor element according to claim 2, further comprising:
the dummy gate of the logic region is removed and replaced with a metal gate, wherein the method of removing the dummy gate and replacing the dummy gate with the metal gate comprises a Replacement Metal Gate (RMG) process.
6. The method for manufacturing a semiconductor element according to claim 5, further comprising:
forming a high-k dielectric layer on the logic region and the memory region of the semiconductor substrate; and
a barrier layer is formed on the high-k dielectric layer, wherein a portion of the high-k dielectric layer and a portion of the barrier layer are formed between the two adjacent select gates.
7. The method according to claim 6, wherein the high-k dielectric layer is formed before the dummy gate is removed.
8. The method as defined in claim 6, wherein the high-k dielectric layer and the barrier layer are formed after the dummy gate is removed.
9. The method of claim 6, wherein at least a portion of the high-k dielectric layer and at least a portion of the barrier layer are disposed between the memory gate and the charge storage structure.
10. The method of claim 5, wherein the memory gate and the metal gate of the logic region are formed by the replacement metal gate process, and the memory gate comprises a metal conductive material.
11. The method of claim 5, wherein the select gate and the metal gate of the logic region are formed by the replacement metal gate fabrication process, and the select gate comprises a metal conductive material.
12. A semiconductor component, comprising:
a semiconductor substrate having a memory region;
a plurality of select gates disposed on the memory region of the semiconductor substrate;
the two charge storage structures are arranged between two adjacent selection grids;
a source region disposed in the semiconductor substrate and between the two adjacent select gates;
the insulating block is arranged on the source electrode region and between the two charge storage structures;
the storage grid electrode is a polycrystalline silicon grid electrode and is arranged on the insulating block, wherein the storage grid electrode is connected with the two charge storage structures;
a high-k dielectric layer disposed on the memory region and a logic region of the semiconductor substrate; and
a barrier layer disposed on the high-k dielectric layer, wherein a portion of the high-k dielectric layer and a portion of the barrier layer are disposed between the two adjacent select gates,
wherein at least a portion of the high-k dielectric layer and at least a portion of the barrier layer are disposed between the polysilicon gate and the charge storage structure.
13. The semiconductor device of claim 12, wherein each of said charge storage structures comprises:
a first oxide layer;
a nitride layer disposed on the first oxide layer; and
and a second oxide layer disposed on the nitride layer.
14. The semiconductor device as defined in claim 12, wherein the plurality of select gates are comprised of polysilicon, and the semiconductor device further comprises a salicide disposed over the memory gate and at least one of the select gates.
15. The semiconductor device as defined in claim 12, wherein the high-k dielectric layer on the logic region and the high-k dielectric layer on the memory region each comprise a U-shaped high-k structure.
16. The semiconductor device as defined in claim 15, wherein the select gate comprises a metal conductive material surrounded by the U-shaped high-k structure of the memory region.
17. The semiconductor device as defined in claim 15, wherein the memory gate comprises a metal conductive material surrounded by the U-shaped high-k structure of the memory region.
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