KR20010011708A - An nonvolatile memory cell and fabricating method thereof - Google Patents

Abstract

PURPOSE: A non-volatile memory cell and manufacturing method is to improve the coupling ratio and to embody high integration in EEP ROM and flash memory device. CONSTITUTION: The first gate(23) is formed like concaveness and the second gate(25) like convexity. Both gates(22,23) are in gear. Therefore, The coupling ratio increases with increasing contact area of both the gates. A source region(26) and a drain region(27) are formed in the substrate located at both lowers of the first gate(23). The source region(26) is common source with which neighbor cells share. The source region(26) improves the coupling ratio and operating speed of a program according to retainment of rich ions.

Description

Nonvolatile memory cell and fabrication method

The present invention relates to a nonvolatile memory cell and a method of manufacturing the same, and in particular, by forming a curved floating gate and a control gate inserted into a curved portion in a concave-convex shape to improve the coupling ratio and secure erase characteristics. The present invention relates to a nonvolatile memory device of a semiconductor device including an Ipyrom, a flash memory device, and the like, which implements high integration to improve program characteristics, and a method of manufacturing the same.

The flash memory cell is a nonvolatile memory device having a structure in which a floating gate and a control gate are stacked and can erase memory array cells simultaneously.

In the flash memory cell, a high voltage is applied to the control gate, and hot-electrons formed in the channel are injected into the floating gate to perform a program operation. At this time, the ratio of the voltage applied to the floating gate with respect to the voltage applied to the control gate is called a coupling ratio. As the coupling ratio increases, the efficiency of the program increases.

The erase operation is performed by applying a high voltage to a source region having a deep junction to inject electrons of the floating gate into a source region or a semiconductor substrate by a mechanism of Fowler-Nordheim tunneling. In addition, an erase operation may be performed by adding an additional erase gate to tunnel electrons stored in the floating gate to the erase gate.

In order to improve the efficiency in the erase operation, the thickness of the gate insulating layer under the floating gate is reduced, which reduces the coupling ratio and lowers the voltage applied to the floating gate. Therefore, it is necessary to improve the erase efficiency while increasing the program efficiency by preventing the coupling ratio from decreasing.

1A and 1B are cross-sectional views respectively viewed in a channel length direction and a channel width direction of a flash memory cell which is a nonvolatile memory device according to the prior art.

1A and 1B, an impurity is formed by interposing a first gate insulating film 12 in a predetermined portion of a P-type semiconductor substrate 10 having a LOCOS type field oxide film 11 defining an active region and an isolation region. The floating gate 13 is formed with a first gate made of this doped polycrystalline silicon.

The control gate 15 serving as the second gate is formed on the floating gate 13 via the second gate insulating film 14. The control gate 15 is formed by patterning the strip in the form of stripes crossing the longitudinal direction of the channel.

The source region 17 and the drain region 16 doped with N-type impurities at a high concentration are formed in the substrate 10 positioned at both lower ends of the floating gate 13.

The flash memory cell having the above-described structure applies a gate voltage of about 12V to the control gate 15 while the source region 17 is grounded during a program operation, and drains about 5 to 6V to the drain region 16. The voltage Vd is applied. Accordingly, a channel is formed in the semiconductor substrate 10 under the floating gate 13 by the gate voltage Vg applied to the control gate 15, and the drain voltage Vd applied to the drain region 16. The accelerated electrons are injected into the floating gate 13 by crossing the energy barrier of the first gate insulating layer 12. Therefore, the cell is programmed with a high threshold voltage.

In the above, the programming efficiency depends on the magnitude of the voltage induced in the floating gate 13 with respect to the gate voltage Vg applied to the control gate 15. That is, the greater the coupling ratio representing the magnitude of the voltage induced in the floating gate 13 with respect to the gate voltage Vg applied to the control gate 15, the greater the programming efficiency. The coupling ratio becomes larger as the capacitance of the first gate insulating film 12 becomes smaller or as the capacitance of the second gate insulating film 14 increases. Therefore, in order to increase the capacitance of the second gate insulating film 14, the second gate insulating film 14 may be formed of an oxide-nitride-oxide (hereinafter referred to as ONO) structure.

When the data programmed into the flash memory cell is erased, the control gate 15 is grounded, or a source voltage Vs of 15 V or more is applied to the source region 17 while the voltage is applied to the floating gate. The electrons in 13 are tunneled to the source region 17. The electrons move from the floating gate 13 to the source region 17 by the FN tunneling mechanism through the first gate insulating layer 12, whereby the threshold voltage of the cell is lowered. Erased. In this case, when the nonvolatile memory device is an EPROM device, an ultraviolet erase method is used. In the case of an EEPROM & Flash cell, a high voltage is applied to a source / drain or bulk to erase the nonvolatile memory device.

In addition, the read operation of the nonvolatile memory device consists of determining the on / off state of the cell by reading the threshold voltage of the cell transistor. That is, when 5V is applied to the control gate 15 and 1V is applied to the drain 16, the program cell is turned off to a high threshold voltage (at least 5V or more), and the erase cell is turned to a low threshold voltage. It is determined to be on.

However, the conventional technique described above forms a field oxide film by the LOCOS method, which is disadvantageous to cell density due to a bird's beak problem and the like, and forms a flat stacked gate so that the first gate floating gate and the second gate control are formed. Since the coupling ratio of the gate is small, the program speed characteristic is lowered, and it is difficult to realize stable erase characteristics when implementing EPIROM and Flash Cell.

Accordingly, an object of the present invention is to form a floating gate having a curved shape and a control gate having a shape inserted into the curved portion in the form of mutual irregularities, thereby improving the coupling ratio, securing erase characteristics, and implementing high integration to improve program characteristics. The present invention provides a nonvolatile memory cell of a semiconductor device including an Ipyrom, a flash memory device, and the like, and a method of manufacturing the same.

To this end, the nonvolatile memory cell according to the present invention includes a semiconductor substrate of a first conductivity type, an uneven insulating pattern defining an active region and an isolation region formed in a predetermined portion of the semiconductor substrate, and an upper surface of the active region and the insulating pattern. A first gate extending in a portion and formed in a first direction, a first gate insulating film interposed between the first gate and the active region substrate, a second gate insulating film covering the first gate, and a second gate insulating film; And a second gate running in one direction and a second conductivity type impurity diffusion region formed in the second direction in the active region at the lower end of the first gate side surface.

To this end, another method of manufacturing a nonvolatile memory cell according to the present invention includes forming an insulating layer pattern exposing an active region on a predetermined portion of a first conductive semiconductor substrate, and interposing a first gate insulating layer on a predetermined portion of the active region. Forming the first gate with a predetermined thickness so as to extend to a part of the side surface and the upper surface of the insulating film pattern in the first direction, forming a second gate insulating film covering the exposed surface of the first gate, and forming a second gate. Forming a second gate covering the insulating layer in a first direction, and forming an impurity diffusion region in an active region in a second direction at a lower end portion of a side surface of the first gate in a second direction.

1A and 1B are cross-sectional views, respectively, as viewed in a channel length direction and a channel width direction of a conventional nonvolatile memory cell.

2A through 2C are cross-sectional views of a nonvolatile memory cell according to the present invention as viewed from the layout, channel width direction and channel length direction, respectively.

3A through 5 are cross-sectional views of a nonvolatile memory cell according to an embodiment of the present invention as viewed in a channel length direction and a channel width direction, respectively.

The present invention provides a memory cell that improves the coupling ratio and chip integration, which are one of the main elements of program characteristics, in implementing nonvolatile memory cells such as EEPROM and Flash, and a manufacturing method thereof. .

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views respectively viewed from a layout, a channel width direction, and a channel length direction of a nonvolatile memory cell according to the present invention, and FIG. 2B is a cross-sectional view taken along the line II ′ of FIG. 2A. FIG. 2C is a cross-sectional view taken along the line II-II ′ of FIG. 2A.

2A to 2C, an oxide film pattern 21 defining an active region and an isolation region is formed on a predetermined portion on a p-type silicon substrate 20, which is a semiconductor substrate 20. The oxide layer pattern 21 is not formed in the active region and covers the substrate 20 in the isolation region.

The control gate 25, which is the second gate 25 and crosses the active region, is formed in the vertical direction for a long time.

As shown in FIG. 2B, the floating gate 23, which is the first gate 23, is positioned under the second gate 25, and the first gates adjacent to each other with the oxide layer pattern 21 therebetween. It is isolated from each other. In addition, the first gate 23 in the channel width direction partially fills the valleys between the oxide film patterns 21 and forms a yaw shape extending to an upper portion of the oxide film pattern 21. Meanwhile, a first gate insulating film 22 made of an oxide film is interposed between the first gate 23 and the silicon substrate 20 in the active region.

In this case, the oxide layer pattern 21 at the end of the portion where the first gate 23 extends may have a recessed upper portion.

A second gate insulating film 24 made of an oxide film is formed on the recessed oxide film pattern 21 portion and the surface of the first gate 230 to form the same pattern as that of the second gate 25 and extend in the vertical direction. The gate insulating film 24 is interposed between the second gate 25 and the first gate 23.

On the other hand, the cross-sectional structure of the second gate 25 in the channel width direction is in the form of an iron shape that engages with a concave portion of the first gate 23 having a concave shape to form a second gate insulating film 24. These intervening irregularities form the interlocking form. Therefore, the corresponding area of the second gate 25 and the first gate 23 is increased to improve the coupling ratio, and smooth the erase operation using the F-N tunneling effect.

A source region 26 and a drain region 27 doped with N-type impurities at a high concentration are formed on the substrate 20 positioned at both lower ends of the first gate 23. In this case, the source region 26 is a common source shared with neighboring cells, and the source region 26 retains abundant charge by additional ion implantation, thereby improving the program operation speed as well as an improved coupling ratio during the program operation. In addition, the portion of the substrate 20 between the source region 26 and the drain region 27 corresponding to the lower portion of the first gate 23 becomes a channel region.

The nonvolatile memory cell having the above-described structure inverts the channel region by applying a gate voltage Vg of about 12V to the control gate, which is the second gate 25, with the source region 26 grounded during a program operation. And a drain voltage Vd of about 7V is applied to the drain region 27. Accordingly, a channel is formed in the semiconductor substrate 20 under the floating gate 23 by the gate voltage Vg applied to the control gate 25, and the drain voltage Vd applied to the drain region 27. The accelerated electrons are injected into the floating gate 23 by crossing the energy barrier of the first gate insulating layer 22. Therefore, the cell is programmed with a high threshold voltage. At this time, as described above, the program operation speed is improved due to the rich charge and the improved coupling ratio by the additional ion implantation of the source region 26.

In the above, the programming efficiency depends on the magnitude of the voltage induced in the floating gate 23 with respect to the gate voltage Vg applied to the control gate 25. That is, the greater the coupling ratio representing the magnitude of the voltage induced in the floating gate 23 with respect to the gate voltage Vg applied to the control gate 25, the greater the programming efficiency. The coupling ratio becomes larger as the capacitance of the first gate insulating film 22 becomes smaller or as the capacitance of the second gate insulating film 24 increases. Therefore, in the present invention, in order to increase the capacitance of the second gate insulating film 24, an oxide-nitride-oxide film (hereinafter referred to as ONO) is formed and the corresponding area of the floating gate and the control gate is increased. To form a concave-convex structure.

When erasing the data programmed in the flash memory cell, the control gate 25 is grounded or floated by applying a source voltage Vs to the source region 26 at a high voltage of 15 V or more while being applied as a '' voltage. The electrons in the gate 23 are tunneled into the source region 26. The electrons move from the floating gate 23 to the source region 26 by the FN tunneling mechanism through the first gate insulating layer 22, whereby the cell has a low threshold voltage. Erased.

In addition, the read operation of the nonvolatile memory device consists of determining the on / off state of the cell by reading the threshold voltage of the cell transistor. That is, when 5V is applied to the control gate 25 and 1V is applied to the drain 27, the program cell is turned off to a high threshold voltage (at least 5V or more), and the erase cell is turned to a low threshold voltage. It is determined to be on.

3A to 5 are process cross-sectional views of a nonvolatile memory cell according to the present invention as viewed in a channel length direction and a channel width direction, respectively.

Referring to FIGS. 3A and 3B, an insulating film pattern 21 defining an active region and an isolation region is formed by depositing a thick insulating film on a silicon substrate 21, which is a p-type semiconductor substrate 20, and then patterning a predetermined shape. Form. In this case, the insulating film pattern 21 is formed by forming an oxide film such as HLD by chemical vapor deposition and then patterning the photolithography. Thus, the surface of the substrate 20, which is an active region of the memory device, is exposed.

Then, the surface of the exposed substrate 20 is oxidized by a thermal oxidation method to form a thermal oxide film, and then polysilicon doped with impurities to the first conductive layer to form a first gate, which is a floating gate, is formed by chemical vapor deposition. It is formed on the surface of the thermal oxide film and the insulating film pattern 21 to have a predetermined thickness.

Next, the first conductive layer and the thermal oxide film are first patterned by photolithography to leave the first conductive layer and the thermal oxide film in the form of a band remaining in the first direction. At this time, the remaining thermal oxide film 22 becomes the first gate insulating film 22. In this case, the first direction is a channel width direction, that is, a direction orthogonal to the source / drain region.

Partial surface of the insulating film pattern 21 is exposed by second patterning again on the remaining first conductive layer by photolithography. At this time, the etching direction is a second direction perpendicular to the first direction. Accordingly, the second patterned first conductive layer becomes a first gate 23 that is a floating gate, and is isolated from neighboring first gates with an insulating layer pattern 21 therebetween. In addition, the first gate 23 in the channel width direction partially fills the valleys between the oxide film patterns 21 and forms a yaw shape extending to an upper portion of the oxide film pattern 21. As described above, a first gate insulating film 22 made of an oxide film is interposed between the first gate 23 and the silicon substrate 20 in the active region.

4A and 4B, a groove is formed by removing a portion of the exposed insulating layer pattern by using the first gate 23 as an etch mask pattern.

An oxide film for forming a second gate insulating film is formed on the exposed surface of the first gate 23 and the substrate including the insulating film pattern 21, and then polysilicon doped with impurities is formed thereon to form a floating gate. To deposit the second conductive layer. In this case, the second gate insulating film may be formed as an ONO film to improve capacitance.

In addition, the second gate 25, which is a control gate including a second conductive layer remaining by performing photolithography etching on the second conductive layer and the oxide film so as to have the same shape as in the first patterning of the first gate 23, remains. A second gate insulating film 24 made of one oxide film is formed. At this time, the second gate 25 has an iron shape that engages with the concave portion of the first gate 23 having a concave shape to form an unevenness having the second gate insulating film 24 interposed therebetween. The first gate 23 and the second gate 25 form some concave shape at the grooves of the insulating film pattern 21. Therefore, the corresponding area of the second gate 25 and the first gate 23 is increased to improve the coupling ratio, and smooth the erase operation using the F-N tunneling effect.

Referring to FIG. 5, the source region 26 and the drain region 27 are formed by performing a high concentration of n-type impurity ions in the exposed active region. Then, an ion implantation mask is formed by a photomasking process, and n-type impurity ion implantation is further performed only in the source region 26.

In this case, the source region 26 is a common source shared with neighboring cells, and the source region 26 retains abundant charge by additional ion implantation, thereby improving the program operation speed as well as an improved coupling ratio during the program operation. In addition, the portion of the substrate 20 between the source region 26 and the drain region 27 corresponding to the lower portion of the first gate 23 becomes a channel region.

The embodiment of the present invention is formed by the oxide film pattern formed by the chemical vapor deposition method of the insulating film pattern 21 for device isolation can be applied to the field oxide film formed by the conventional LOCOS method.

Therefore, the present invention forms the first gate having a bent shape using the uneven structure of the insulating film pattern, thereby increasing the coupling ratio with the second gate and forming an additional ion implanted source region to improve the programming characteristics and the erase operation characteristics. In addition, there is an advantage of improving the integration degree of the device by implementing a common source structure.

Claims (8)

A first conductive semiconductor substrate, An uneven insulating pattern defining an active region and an isolation region formed in a predetermined portion on the semiconductor substrate; A first gate extending in a portion of the upper surface of the active region and the insulating layer pattern in a first direction; A first gate insulating film interposed between the first gate and the active region substrate; A second gate insulating film covering the first gate; A second gate covering the second gate insulating layer and running long in the first direction; And a second conductivity type impurity diffusion region formed in the active region under the first gate side surface in a second direction. The nonvolatile memory cell of claim 1, wherein an upper portion of the insulating layer pattern is recessed in an end portion of a portion in which the first gate extends. The nonvolatile memory cell of claim 1, wherein the source of the impurity diffusion region is a common source commonly used with Yiwu cells. Forming an insulating film pattern exposing an active region on a predetermined portion of the first conductive semiconductor substrate; Forming a first gate having a first gate insulating film interposed in a predetermined portion of the active region to a predetermined thickness in a first direction so as to extend to a part of the side surface and the upper surface of the insulating film pattern; Forming a second gate insulating film covering the exposed surface of the first gate; Forming a second gate covering the second gate insulating layer in the first direction, And forming an impurity diffusion region in the active region in the second direction and in the lower region of the side surface of the first gate in the second direction. The method of claim 1, wherein the insulating layer pattern is formed by depositing an insulating layer by chemical vapor deposition and then patterning the insulating layer. The method of claim 1, wherein the insulating layer pattern is formed to have an upper structure recessed in a portion where the first gate extends. The method of claim 1, wherein the source region of the impurity diffusion region increases the concentration of impurity ions by additional ion implantation. The method of claim 7, wherein the source region is a common source region commonly used with neighboring cells.