CN101118926A - Multi-order non-volatility memory and manufacturing method and operation method therefor - Google Patents
Multi-order non-volatility memory and manufacturing method and operation method therefor Download PDFInfo
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- CN101118926A CN101118926A CNA2006101082201A CN200610108220A CN101118926A CN 101118926 A CN101118926 A CN 101118926A CN A2006101082201 A CNA2006101082201 A CN A2006101082201A CN 200610108220 A CN200610108220 A CN 200610108220A CN 101118926 A CN101118926 A CN 101118926A
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Abstract
The present invention relates to a multi step nonvolatility memory and comprises a storing unit on the base board. The storing unit comprises a controlling grid, an electricity storing layer, an adulteration area, a selective grid and an assisting grid; the controlling grid is arranged on the base board; the electricity storing layer is arranged between the controlling grid and the base board; the adulteration area is positioned in the first side base board of the controlling grid; the selective grid is positioned on the side wall of the first side of the controlling grid and is positioned on the base board between the controlling grid and the adulteration area; the assisting grid is positioned on the side wall of the second side of the controlling grid; and the base board will form a reversion layer under the assisting grid when the assisting grid is exerted with the voltage.
Description
Technical field
The present invention relates to a kind of semiconductor element, particularly relate to a kind of multi-level non-volatile memory body and manufacture method thereof and method of operation.
Background technology
Non-volatile memory component can repeatedly carry out the actions such as depositing in, read, erase of data owing to having, and the advantage that the data that deposit in also can not disappear after outage, thus become personal computer and electronic equipment a kind of memory component of extensively adopting.
Typical non-volatile memory component is to make floating grid (FloatingGate) and control grid (Control Gate) with the polysilicon that mixes.The control grid is set directly on the floating grid, and floating grid is separated by with dielectric layer with controlling between the grid, and between floating grid and the substrate with tunnel oxide (TunnelOxide) be separated by (being so-called stacked gate flash memory).And, when erasing,, and cause the erroneous judgement problem of data for fear of memory because of the phenomenon of excessively erasing is too serious.So, can above controlling grid and floating grid sidewall, substrate, establish selection grid (Select Gate) in addition, and form separated grid (Split Gate) structure.
Generally speaking, at present the non-volatile memory array that more often uses of industry for example is NOR gate (NOR) type array structure.In existing NOR gate (NOR) type array, per two memory cell are shared the contact hole of a bit lines and are shared a source electrode line.Therefore, each memory cell can take the size of half contact hole and half source electrode line width.Because each memory cell is all directly linked by bit line, so in NOR gate (NOR) type array, the operation that memory cell can read arbitrarily and write, and because the resistance of series connection is less, the electric current of memory cell when read operation is bigger, and the speed that reads is also just very fast.
Yet, when the memory in the NOR type non-volatility memorizer is used as multi-level cell memory, because it is less to be used to differentiate the start voltage distribution of each data mode.So, in the programming operations of existing NOR type non-volatility memorizer, just need carry out repeatedly sequencing step and sequencing and confirm step,, so will spend the long time so that the sequencing memory cell accurately is in the start voltage distribution of setting.
Summary of the invention
Therefore, purpose of the present invention just provides a kind of multi-level non-volatile memory body and manufacture method and method of operation, can improve the reliability of element.
A further object of the present invention provides a kind of multi-level non-volatile memory body and manufacture method and method of operation, and its technology is simple, and can increase process allowance.
Another purpose of the present invention provides a kind of multi-level non-volatile memory body and manufacture method and method of operation, can shorten the sequencing time of memory cell, accelerates the speed of erasing.
The invention provides a kind of multi-level non-volatile memory body, comprise first memory cell that is arranged on the substrate.This first memory cell comprises control grid, electric charge storage layer, doped region, selection grid and auxiliary grid.The control grid is arranged on the substrate.Electric charge storage layer is arranged between control grid and the substrate.Doped region is arranged in the substrate of first side of controlling grid.The selection grid is arranged on the sidewall of first side of control grid, and on the substrate between control grid and the doped region.Auxiliary grid is arranged in the sidewall of second side of controlling grid, and when auxiliary grid applies voltage, forms inversion layer in the substrate of auxiliary grid below.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also comprise first dielectric layer, second dielectric layer, the 3rd dielectric layer and the 4th dielectric layer.First dielectric layer is arranged between electric charge storage layer and the substrate.Second dielectric layer is arranged between electric charge storage layer and the control grid.The 3rd dielectric layer is arranged on auxiliary grid and controls between grid, the electric charge storage layer, and between auxiliary grid and the substrate.The 4th dielectric layer is arranged on the selection grid and controls between grid, the electric charge storage layer, and selects between grid and the substrate.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, be formed with clearance wall between above-mentioned the 3rd dielectric layer and control grid, the electric charge storage layer.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, be formed with clearance wall between above-mentioned the 4th dielectric layer and the control grid.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the material of said first dielectric layer comprises silica.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the material of said second dielectric layer comprises silicon oxide/silicon nitride/silicon oxide.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, above-mentioned the 3rd dielectric layer and the 4th dielectric layer are thermal oxide.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the thickness of above-mentioned the 3rd dielectric layer and the 4th dielectric layer is between 100 dust to 200 dusts.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also comprise second memory cell.Second memory cell has identical structure with first memory cell, and second memory cell and first memory cell with the mirror image symmetrical manner in abutting connection with setting.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, above-mentioned second memory cell is arranged on first side of first memory cell, and shares doped region with first memory cell.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, above-mentioned second memory cell is arranged on second side of first memory cell, and shares auxiliary electrode with first memory cell.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also comprise cap layer.This cap layer is arranged on the control grid.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, protrude in to above-mentioned electric charge storage layer part of horizontal this control grid, and have corner in abutting connection with the position of selecting grid.
The invention provides a kind of multi-level non-volatile memory body, comprise most memory cell, most bit lines, most bar control gate line, most bar selection gate line, most bar supplementary gate polar curve and most transistors.A most memory cell are provided with on substrate embarks on journey/column array.Each memory cell comprises control grid, electric charge storage layer, doped region, selection grid, auxiliary grid.The control grid is arranged on the substrate.Electric charge storage layer is arranged between control grid and the substrate.Doped region is arranged in the substrate of first side of controlling grid.The selection grid is arranged on the sidewall of first side of control grid, and on the substrate between control grid and the doped region.Auxiliary grid is arranged on the sidewall of second side of control grid, wherein with the memory cell in the delegation with the mirror image symmetrical manner in abutting connection with setting.Most bit lines are arranged in parallel on line direction, connect the doped region with the memory cell of delegation.Most bar control gate line are arranged in parallel on column direction, connect the control grid of the memory cell of same row.Most bars select gate line to be arranged in parallel on column direction, connect the selection grid of the memory cell of same row.Most bar supplementary gate polar curves are arranged in parallel on column direction, connect the auxiliary grid of the memory cell of same row.Transistor drain connects the substrate of supplementary gate polar curve below respectively.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also comprise first dielectric layer, second dielectric layer, the 3rd dielectric layer, the 4th dielectric layer.First dielectric layer is arranged between electric charge storage layer and the substrate.Second dielectric layer is arranged between electric charge storage layer and the control grid.The 3rd dielectric layer is arranged on auxiliary grid and controls between grid, the electric charge storage layer, and between auxiliary grid and the substrate.The 4th dielectric layer is arranged on the selection grid and controls between grid, the electric charge storage layer, and selects between grid and the substrate.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, be formed with clearance wall between above-mentioned the 3rd dielectric layer and control grid, the electric charge storage layer.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, be formed with clearance wall between above-mentioned the 4th dielectric layer and the control grid.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the material of said first dielectric layer comprises silica.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the material of said second dielectric layer comprises silicon oxide/silicon nitride/silicon oxide.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, wherein the 3rd dielectric layer and the 4th dielectric layer are thermal oxide.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, protrude in to above-mentioned electric charge storage layer part of horizontal the control grid, and have corner in abutting connection with the position of selecting grid.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, adjacent two memory cell of above-mentioned mirror images of each other symmetry are to share the drain region.
According to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, adjacent two memory cell of above-mentioned mirror images of each other symmetry are to share auxiliary grid.
In the multi-level non-volatile memory body of the present invention, two adjacent memory cell for example are that two promptly adjacent memory cell are shared auxiliary grid or doped region with the configuration of mirror image symmetrical manner.Therefore the structure of multi-level non-volatile memory body of the present invention not only can be simplified manufacturing process, reduce manufacturing cost, also can improve the integrated level of element simultaneously.
And, when opening the passage below the auxiliary grid when being applied with voltage on the auxiliary grid and forming inversion layer, on inversion layer, apply voltage, make the inversion layer of auxiliary grid below can be in pre-charge state.When sequencing non-volatility memorizer of the present invention, by the mode of self-accelerated charge injection (channelself-boosting), utilize the source side injection effect to carry out the memory cell sequencing, can improve sequencing speed.And when this non-volatility memorizer during as multi-level cell memory, the start voltage of control store unit after sequencing is positioned at the scope that sets exactly when programming operations.
The invention provides a kind of manufacture method of multi-level non-volatile memory body, comprise the following steps.At first, form tunneling dielectric layer, electric charge storage layer successively on substrate, and form at least two stack layers on electric charge storage layer, wherein each two stack layer comprises dielectric layer between door, control grid and cap layer successively.Then, remove the electric charge storage layer between two stack layers, to form first groove.Behind two stack layer sidewalls and first trenched side-wall formation clearance wall, remove the electric charge storage layer in the two stack layers outside as mask with clearance wall.Then, on substrate, form dielectric layer.Between two stack layers, form auxiliary grid, and form the selection grid respectively at the sidewall in the two stack layers outside.Afterwards, in the substrate in the two stack layers outside, form doped region respectively, and select grid between stack layer and doped region.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, above-mentioned dielectric layer comprises thermal oxide.
According to the manufacture method of the described non-volatility memorizer of the preferred embodiments of the present invention, the thickness of above-mentioned dielectric layer is between 100 dust to 200 dusts.
According to the manufacture method of the described non-volatility memorizer of the preferred embodiments of the present invention, wherein between two stack layers, form auxiliary grid, and the sidewall in the two stack layers outsides forms respectively and selects the method for grid as follows.At first form conductor material layer on substrate, this conductor material layer fills up first groove, carries out etch back process then, removes the segment conductor material layer, up to exposing cap layer.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the material of above-mentioned tunneling dielectric layer comprises silica.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the formation method of above-mentioned tunneling dielectric layer comprises thermal oxidation method.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between above-mentioned door.
According to the manufacture method of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the material of above-mentioned electric charge storage layer comprises doped polycrystalline silicon.
In the manufacture method of non-volatility memorizer of the present invention, owing to adopt the mode of aiming at voluntarily to form auxiliary grid and selection grid, do not need to use photoetching process, therefore can save manufacturing cost, increase process allowance.
And, because formed electric charge storage layer has a corner near the part of selecting grid, therefore when memory cell is erased, electric field is concentrated, be drawn out to the erase operation for use speed of selecting grid from electric charge storage layer and can improve electronics by this corner.
The invention provides a kind of method of operation of multi-level non-volatile memory body, be applicable to memory cell.This memory cell comprises control grid, electric charge storage layer, drain region, selection grid and auxiliary grid.The control grid is arranged on the substrate.Electric charge storage layer is arranged between control grid and the substrate.The drain region is arranged in the substrate of first side of controlling grid.The selection grid is arranged on the sidewall of first side of control grid, and on the substrate between control grid and the doped region.Auxiliary grid is arranged on the sidewall of second side of control grid, and the method is included in when carrying out programming operations, applies first voltage at auxiliary grid in advance, forming inversion layer in the substrate below auxiliary grid, and applies second voltage at inversion layer.Then, apply tertiary voltage at the control grid, selecting grid to apply the 4th voltage, apply the 5th voltage in the drain region, wherein first voltage is greater than the start voltage of auxiliary grid, and tertiary voltage is greater than first voltage, and the 4th voltage is more than or equal to the start voltage of selecting grid, second voltage is greater than the 5th voltage, to utilize source side injection effect sequencing memory cell.
According to the method for operation of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, first voltage is about 8 volts; Second voltage is about 5 volts; Tertiary voltage is about 10 volts; The 4th voltage is about 1.5 volts; The 5th voltage is about 0 volt.
Method of operation according to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also be included in when carrying out erase operation for use, selecting grid to apply the 6th voltage, so that the electronics that is stored in the electric charge storage layer is drawn out and removes via the selection grid, wherein the voltage difference of the 6th voltage and substrate can cause the FN tunneling effect.
According to the method for operation of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the 6th voltage is about 11 to 15 volts.
Method of operation according to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also be included in when carrying out read operation, apply the 7th voltage at auxiliary grid, apply the 8th voltage at the control grid, selecting grid to apply the 9th voltage, apply the tenth voltage in the drain region, with reading cells, the 9th voltage is greater than the start voltage of selecting grid.
According to the method for operation of the described non-volatility memorizer of the preferred embodiments of the present invention, the 7th voltage is Vcc (supply voltage), and the 8th voltage is about 1.4 volts, and the 9th voltage is Vcc (supply voltage), and the tenth voltage is about 1.5 volts.
The invention provides a kind of method of operation of multi-level non-volatile memory body, be applicable to the memory cell array that constitutes by most memory cell.Each memory cell comprises control grid, electric charge storage layer, doped region, selection grid, auxiliary grid.The control grid is arranged on the substrate.Electric charge storage layer is arranged between control grid and the substrate.Doped region is arranged in the substrate of first side of controlling grid.The selection grid is arranged on the sidewall of first side of control grid, and on the substrate between control grid and the doped region.Auxiliary grid is arranged on the sidewall of second side of control grid, wherein with the memory cell in the delegation with the mirror image symmetrical manner in abutting connection with setting.Most bit lines are arranged in parallel on line direction, connect the doped region with the memory cell of delegation.Most bar control gate line are arranged in parallel on column direction, connect the control grid of the memory cell of same row.Most bars select gate line to be arranged in parallel on column direction, connect the selection grid of the memory cell of same row.Most bar supplementary gate polar curves are arranged in parallel on column direction, connect the auxiliary grid of the memory cell of same row.Transistor drain connects the substrate of supplementary gate polar curve below.The method is included in when carrying out programming operations, apply first voltage at transistorized grid in advance, apply second voltage at transistorized source electrode, apply tertiary voltage at the supplementary gate polar curve, to form inversion layer in the substrate below the supplementary gate polar curve, make the inversion layer conducting that second voltage be arranged, change this transistorized grid voltage afterwards and be 0 volt to close this transistorized passage, make this inversion layer be in pre-charge state, then auxiliary grid voltage is pulled to about 8 volts, about voltage to 5 volt with coupling (coupling) inversion layer.Apply the 4th voltage in selected control gate line, apply the 5th voltage at selected selection gate line, apply the 6th voltage at selected bit line, wherein tertiary voltage is greater than the start voltage of auxiliary grid, the 4th voltage is greater than tertiary voltage, the 5th voltage is more than or equal to the start voltage of selecting grid, and second voltage is greater than the 6th voltage, to utilize source side injection effect sequencing selected memory cell.
According to the method for operation of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, first voltage is Vcc (supply voltage); Second voltage is Vcc (supply voltage)-Vth (starting voltage of transistor); Tertiary voltage is Vcc (supply voltage); The 4th voltage is about 10 volts; The 5th voltage is about 1.5 volts; The 6th voltage is about 0 volt.
Method of operation according to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also be included in when carrying out erase operation for use, selecting grid to apply the 7th voltage, so that the electronics that is stored in the electric charge storage layer is drawn out and removes via the selection gate line, wherein the voltage difference of the 7th voltage and substrate can cause the FN tunneling effect.
According to the method for operation of the described multi-level non-volatile memory body of the preferred embodiments of the present invention, the 7th voltage is about 11 to 15 volts.
Method of operation according to the described multi-level non-volatile memory body of the preferred embodiments of the present invention, also be included in when carrying out read operation, apply the 8th voltage at selected supplementary gate polar curve, apply the 9th voltage in selected control gate line, apply the tenth voltage at selected selection gate line, apply the 11 voltage at selected bit line, with reading cells, the tenth voltage is greater than the start voltage of selecting grid.
According to the method for operation of the described non-volatility memorizer of the preferred embodiments of the present invention, the 8th voltage is Vcc (supply voltage), and the 9th voltage is about 1.4 volts, and the tenth voltage is Vcc (supply voltage), and the 11 voltage is about 1.5 volts.
In the method for operation of multi-level non-volatile memory body of the present invention, inject the mode of (channel self-boosting) owing to adopt self-accelerated charge, utilize the source side injection effect to carry out the memory cell sequencing, make the passage of auxiliary grid charge to setting voltage in advance, and can fast sequencing memory cell.And, utilize to select the grid memory cell of erasing, make electronics remove via erasing grid, can reduce the number of times that electronics passes through tunneling dielectric layer, and improve the element reliability.In addition, electric charge storage layer is in abutting connection with selecting the grid part to have corner.When erasing, by this corner electric field is concentrated, be drawn out to the erase operation for use speed of selecting grid from electric charge storage layer and can improve electronics.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below.
Description of drawings
Fig. 1 is the sectional view of the non-volatile memory structure showed according to embodiments of the invention.
Fig. 2 A be shown as is carried out the schematic diagram of the example of programming operations to memory cell.
Fig. 2 B be shown as is carried out the schematic diagram of the example of erase operation for use to memory cell.
Fig. 2 C be shown as is carried out the schematic diagram of the example of read operation to memory cell.
The electrical schematic diagram of the embodiment of the memory cell array that Fig. 3 is made of multi-order non-volatility memory cell of the present invention for displaying.
Fig. 4 A be shown as is carried out the schematic diagram of the example of programming operations to memory array.
Fig. 4 B be shown as is carried out the schematic diagram of the example of erase operation for use to memory array.
Fig. 4 C be shown as is carried out the schematic diagram of the example of read operation to memory set.
Fig. 5 A to Fig. 5 G is the flow process schematic cross-section of the manufacture method of the non-volatility memorizer showed according to embodiments of the invention.
The simple symbol explanation
100,200: substrate
102: tunneling dielectric layer
104,204,204a: electric charge storage layer
106,206,206a: dielectric layer between door
108, CG: control grid
110,210: cap layer
111,212: stack layer
112a, 112b, 220: clearance wall
114,228: doped region
116, SG: select grid
118, AG: auxiliary grid
120,122,202,222: dielectric layer.
124, L, L1, L2: inversion layer
126: corner
128, BL1～BL4: bit line
130,232: connector
208,224,226,234: conductor layer
214: the mask layer of pattern
216: opening
218: groove
222: dielectric layer
230: interlayer insulating film
AG: auxiliary grid
AL1～AL2: supplementary gate polar curve
CL1～CL4: control gate line.
D: drain region
D1, D2: drain electrode
G1～G2: grid
Q1～Q4, Q11～Q44: memory cell
S1, S2: source electrode
T1, T2: transistor
Embodiment
Fig. 1 is the sectional view of the structure of the non-volatility memorizer showed according to embodiments of the invention.
Please refer to Fig. 1, the multi-level non-volatile memory body that the present invention proposes is made of a plurality of memory cell Q1, the Q2, Q3, the Q4 that are arranged on the substrate 100.Each memory cell Q1, Q2, Q3, Q4 comprise dielectric layer 106 between tunneling dielectric layer 102, electric charge storage layer 104, door, control grid 108, cap layer 110, clearance wall 112a, 112b, doped region 114, select grid 116, auxiliary grid 118 and dielectric layer 120,122.Dielectric layer 106, control grid 108, cap layer 110 constitute stack layer 111 between door.
Electric charge storage layer 104 for example is arranged between control grid 108 and the substrate 100.The material of electric charge storage layer 104 for example is that conductor material (as doped polycrystalline silicon) maybe can make electric charge be absorbed in material wherein, for example silicon nitride, silicon oxynitride, tantalum oxide, strontium titanates or hafnium oxide etc.
Tunneling dielectric layer 102 for example is arranged on the substrate 100 of electric charge storage layer 104 belows, and the material of tunneling dielectric layer 102 for example is a silica.
Between auxiliary grid 118 and control grid 108, electric charge storage layer 104, for example be provided with clearance wall 112b.Selecting for example to be provided with clearance wall 112a between grid 116 and the control grid 108.The material of clearance wall 112a, 112b for example is a silicon nitride.Owing to protrude in to electric charge storage layer 104 part of horizontal control grid 108 and be positioned at clearance wall 112a below, make electric charge storage layer 104 have a corner 126 near the part of selecting grid 116d, therefore when memory cell is erased, by this corner 126 electric field is concentrated, be drawn out to the erase operation for use speed of selecting grid 116 from electric charge storage layer 104 and can improve electronics.
In addition, doped region 114 for example is to be electrically connected to bit line 128 by connector 130.Connector 130 for example is a conductor material with the material of bit line 128.
In the multi-level non-volatile memory body of the present invention, two adjacent memory cell for example are that two promptly adjacent memory cell are shared auxiliary grid or doped region with the configuration of mirror image symmetrical manner.For instance, memory cell Q1 and memory cell Q2 share auxiliary grid; Memory cell Q2 and memory cell Q3 share doped region; Memory cell Q3 and memory cell Q4 share auxiliary grid.Therefore the structure of multi-level non-volatile memory body of the present invention not only can be simplified manufacturing process, reduce manufacturing cost, also can improve the integrated level of element simultaneously.
And, when opening the passage of auxiliary grid 118 belows and forming inversion layer 124, on inversion layer 124, apply voltage when being applied with voltage on the auxiliary grid 118, make the inversion layer 124 of auxiliary grid 118 belows can be in pre-charge state.When sequencing non-volatility memorizer of the present invention, by the mode of self-accelerated charge injection (channel self-boosting), utilize the source side injection effect to carry out the memory cell sequencing, can improve sequencing speed.And when this non-volatility memorizer during as multi-level cell memory, accurately the start voltage of control store unit after sequencing is positioned at the scope that sets when programming operations.
For instance, this multi-level cell memory is to read voltage Vref1, Vref2, Vref3 by benchmark, differentiate four kinds of different start voltages (Threshold Voltage) Vth1, Vth2, Vth3, Vth4, Vth1＜Vref1＜Vth2＜Vref2＜Vth3＜Vref3＜Vth4.Vth1 for example is less than 0 volt, is expressed as " 00 " state; Vref1 for example is about 0 volt; Vth2 is 0.2～2 volt for example, is expressed as " 01 " state; Vref2 for example is 2.2 volts; Vth3 is 2.4～4.2 volts for example, is expressed as " 10 " state; Vref3 for example is 4.4 volts; Vth4 for example is greater than 4.4 volts, is expressed as " 11 " state.When sequencing, in the time of making memory cell be in " 01 " or " 10 " state, the start voltage of memory cell is dropped in the scope of 0.2～2 volt or 2.4～4.2 volts accurately.Because the scope of the start voltage when memory cell is in " 01 " or " 10 " state, therefore need carry out repeatedly sequencing step and sequencing and confirm step, so that the sequencing memory cell accurately is in the start voltage of setting, so will spend the long time.Yet, inject the mode of (channel self-boosting) if adopt self-accelerated charge, utilize the source side injection effect to carry out the memory cell sequencing, make the passage of auxiliary grid charge to setting voltage in advance, and sequencing memory cell fast is to " 01 " or " 10 " state.As for " 11 " state, then can adopt the mode of self-accelerated charge injection (channel self-boosting) or not adopt self-accelerated charge to inject the mode of (channel self-boosting), carry out the sequencing of memory cell.
Then, the operator scheme of multi-order non-volatility memory cell of the present invention is described, it comprises sequencing, erases and operator schemes such as data read.Fig. 2 A be shown as is carried out the schematic diagram of the example of programming operations to memory cell.Fig. 2 B be shown as is carried out the schematic diagram of the example of erase operation for use to memory cell.Fig. 2 C be shown as is carried out the schematic diagram of the example of read operation to memory cell.
Please refer to Fig. 2 A, when carrying out programming operations, apply voltage Vag at auxiliary grid AG in advance,, and on inversion layer L, apply voltage Vl with formation inversion layer L in the substrate of auxiliary grid AG below.Wherein voltage Vag is greater than the start voltage of auxiliary grid AG, and voltage Vag for example is about 8 volts.Voltage Vl for example is 5 volts.
Then, on control grid CG, apply voltage Vp1; Selecting to apply voltage Vp2 on the grid SG, on the D of drain region, apply voltage Vp3.Voltage Vp1 is greater than voltage Vag, and voltage Vp1 for example is about 10 volts; Voltage Vp2 is more than or equal to the start voltage of selecting grid SG, and voltage Vp2 for example is about 1.5 volts; Voltage Vl is greater than voltage Vp3, and voltage Vp3 for example is about 0 volt, to utilize source side injection effect sequencing memory cell.
Please refer to Fig. 2 B, when carrying out erase operation for use, selecting to apply voltage Ve1 on the grid SG, and with substrate floating, so that the electronics that is stored in the electric charge storage layer is drawn out and removes via selection grid SG, wherein the voltage difference of voltage Ve1 and substrate can cause the FN tunneling effect.Voltage Ve1 for example is about 11 to 15 volts.
Please refer to Fig. 2 C, when carrying out read operation, on auxiliary grid AG, apply voltage Vr1, on control grid CG, apply voltage Vr2,, in the D of drain region, apply voltage Vr4, with reading cells selecting to apply voltage Vr2 on the grid.Wherein, voltage Vr1 for example is that voltage Vr1 for example is Vcc (supply voltage) by the resistance decision of the substrate of auxiliary grid below.Voltage Vr2 for example is about 1.4 volts.Voltage Vr3 is greater than the start voltage of selecting grid, and voltage Vr3 for example is Vcc (supply voltage).Voltage Vr4 for example is about 1.5 volts.
Under above-mentioned bias condition, can judge the digital information that is stored in this memory cell by the channel current size of detection of stored unit.
In method of operation of the present invention, inject the mode of (channelself-boosting) owing to adopt self-accelerated charge, utilize the source side injection effect to carry out the memory cell sequencing, make the passage of auxiliary grid charge to setting voltage in advance, and can fast sequencing memory cell.And, utilize to select the grid memory cell of erasing, make electronics remove via selecting grid, can reduce the number of times that electronics passes through tunneling dielectric layer, and improve the element reliability.In addition, electric charge storage layer is in abutting connection with selecting the grid part to have corner.When erasing, by this corner electric field is concentrated, be drawn out to the erase operation for use speed of selecting grid from electric charge storage layer and can improve electronics.
The electrical schematic diagram of the embodiment of the memory cell array that Fig. 3 is made of multi-order non-volatility memory cell of the present invention for displaying.
As shown in Figure 3, memory cell array for example is made up of memory cell Q11～Q44, many supplementary gate polar curve AL1～AL2, multiple bit lines BL1～BL4 and many control gate line CL1～CL4.The structure of memory cell Q11～Q44 is as described above shown in the Q1～Q4 among Fig. 1.
Memory cell Q11～Q44 is arranged in rows/column array.On directions X (line direction), memory cell Q11～Q14 for example is into mirror configuration.Two adjacent memory cell Q11～Q14 can share an auxiliary grid or drain region.For instance, memory cell Q11 and Q12 share auxiliary grid; Memory cell Q12 and Q13 share the drain region; Memory cell Q13 and Q14 share auxiliary grid.
Many supplementary gate polar curve AL1～AL2 is arranged in parallel on Y direction (column direction), and connects the auxiliary grid of the memory cell of same row.For instance, supplementary gate polar curve AL1 connects the auxiliary grid of memory cell Q11～memory cell Q41 and memory cell Q12～memory cell Q42; Supplementary gate polar curve AL2 connects the auxiliary grid of memory cell Q13～memory cell Q43 and memory cell Q14～memory cell Q44.
Multiple bit lines BL1～BL4 is arranged in parallel on directions X (line direction), connects the drain region with the memory cell of delegation.For instance, bit line BL1 connects the drain region of memory cell Q11～memory cell Q14; Bit line BL2 connects the drain region of memory cell Q21～memory cell Q24; ...; The rest may be inferred, and bit line BL4 connects the drain region of memory cell Q41～memory cell Q44.
Many control gate line CL1～CL6 is arranged in parallel on column direction, and connects the control grid of the memory cell of same row.For instance, control gate line CL1 connects the control grid of memory cell Q11～memory cell Q41; Control gate line CL2 connects the control grid of memory cell Q12～memory cell Q42; ...; The rest may be inferred, and control gate line CL4 connects the control grid of memory cell Q14～memory cell Q44.
Select gate line SL1～SL4 on column direction, to be arranged in parallel, and connect the selection grid of the memory cell of same row for many.For instance, select gate line SL1 to connect the selection grid of memory cell Q11～memory cell Q41; Select gate line SL2 to connect the selection grid of memory cell Q12～memory cell Q42; ...; The rest may be inferred, selects gate line SL4 to connect the selection grid of memory cell Q14～memory cell Q44.
The drain D 1 of transistor T 1, T2, D2 connect the substrate of supplementary gate polar curve AL1～AL2 below.Open the passage below supplementary gate polar curve AL1, the AL2 when being applied with voltage on supplementary gate polar curve AL1, the AL2 and form inversion layer, and the grid G 1 of transistor T 1, T2, G2 are applied with voltage and when opening the passage of transistor T 1, T2, and the electric current that is applied to source S 1, the S2 of transistor T 1, T2 promptly can be via drain D 1, D2 and is circulated to inversion layer below supplementary gate polar curve AL1, the AL2.Then, close the passage of transistor T 1, T2 and draw high the voltage of supplementary gate polar curve AL1, AL2, make the inversion layer of supplementary gate polar curve AL1, AL2 below can be in pre-charge state, promptly the voltage of inversion layer cuts transistor T 1, T2 starting voltage greater than source S 1, S2 voltage.When sequencing non-volatility memorizer of the present invention, inject (channel self-boosting) by self-accelerated charge and carry out sequencing, can improve sequencing speed.And when this non-volatility memorizer during as multi-level cell memory, accurately the start voltage of control store unit after sequencing is positioned at the scope that sets when programming operations.
Then, the operator scheme of non-volatile memory array of the present invention is described, it comprises sequencing, erases and operator schemes such as data read.With regard to the method for operation of non-volatility memorizer of the present invention, below only provide preferred embodiment as an illustration.But the method for operation of non-volatile memory array of the present invention is not limited to these methods.Wherein, Fig. 4 A be shown as is carried out the schematic diagram of the example of programming operations to memory array.Fig. 4 B be shown as is carried out the schematic diagram of the example of erase operation for use to all memory cell.Fig. 4 memory array that C is shown as is carried out the schematic diagram of the example of read operation.And, be to be that example is done explanation in following explanation with memory cell Q13 shown in Figure 3.
Please refer to Fig. 3 and Fig. 4 A, when memory cell Q13 is carried out programming operations, on the grid of transistor T 1, T2, apply voltage Vtg in advance; On the source S 1 of transistor T 1, T2, S2, apply voltage Vts; On supplementary gate polar curve AL2, apply voltage Val, to form inversion layer L2 in the substrate below supplementary gate polar curve AL2, and make inversion layer L2 conducting that voltage Vts-Vth be arranged, wherein Vth is the starting voltage of transistor T 1, T2, the voltage of supplementary gate polar curve AL1 is then kept 0 volt, so can not form inversion layer in the substrate of its below.Then, close the passage of transistor T 1, T2, and the voltage of supplementary gate polar curve AL2 is drawn high to about 8 volts,, therefore make inversion layer L2 can be in pre-charge state with about the voltage to 5 of coupling inversion layer L2 volt.Wherein, voltage Vtg for example is the start voltage Vth that is greater than or equal to transistor T 1, T2, to open the passage of transistor T 1, T2.Voltage Vtg for example is Vcc (supply voltage).Voltage Vts for example is Vcc (supply voltage).Voltage Val for example is the start voltage that is greater than or equal to auxiliary grid, for example is to begin for Vcc (supply voltage), and transistor T 1, T2 just draw high to about 8 volts after closing by the time.
Then, apply voltage Vp1 on selected control gate line CL3, apply voltage Vp2 on selected selection gate line SL3, apply voltage Vp3 on selected bit line BL1, voltage Vp1 for example is about 10 volts; Voltage Vp2 is more than or equal to the start voltage of selecting grid SG, and voltage Vp2 for example is about 1.5 volts; Voltage Vts is greater than voltage Vp3, and voltage Vp3 for example is about 0 volt, to utilize source side injection effect sequencing selected memory cell Q13.
When carrying out the said procedure operation, for sharing control gate line CL3 with selected memory cell Q13, selecting for other non-selected memory cell Q23, Q33 and Q43 of gate line SL3 and supplementary gate polar curve AL2, then can on non-selected bit line BL2, BL3 that these non-selected memory cell Q23, Q33 and Q43 are coupled and BL4, apply voltage, to suppress non-selected memory cell Q23, Q33 and Q43 by sequencing.In addition, because non-selected control gate line CL1, CL2, CL4 do not apply voltage, so other non-selected memory cell Q11～Q41, Q12～Q42 and Q14～Q44 can be by sequencing.
Please refer to Fig. 3 and Fig. 4 B, when carrying out erase operation for use, selecting to apply voltage Ve1 on gate line SL1～SL4, and with substrate floating, be drawn out and remove via the selection grid so that be stored in the electronics of the electric charge storage layer of all memory cell Q11～Q41, Q12～Q42, Q13～Q43 and Q14～Q44, wherein the voltage difference of voltage Ve1 and substrate can cause the FN tunneling effect.Voltage Ve1 for example is about 11 to 15 volts.
Please refer to Fig. 3 and Fig. 4 C, when carrying out read operation, on selected supplementary gate polar curve AL2, apply voltage Vr1, on selected control gate line CL3, apply voltage Vr2, on selected selection gate line SL3, apply voltage Vt3, on selected bit line BL1, apply voltage Vt4, with reading cells Q13.Wherein, voltage Vr1 for example is that voltage Vr1 for example is Vcc (supply voltage) by the resistance decision of the substrate of supplementary gate polar curve below.Voltage Vr2 for example is about 1.4 volts.Voltage Vr3 for example is Vcc (supply voltage) greater than the start voltage of selecting grid.Voltage Vr4 for example is about 1.5 volts.Then do not apply voltage or float as for non-selected supplementary gate polar curve AL1, non-selected control gate line CL1, CL2, CL4, non-selected selection gate line SL1, SL2, SL4, non-selected bit line BL2, BL3, BL4.
Under above-mentioned bias condition, can judge the digital information that is stored among this memory cell Q13 by the channel current size of detection of stored unit Q13.
In method of operation of the present invention, inject the mode of (self-boosted-chargeinjection) owing to adopt self-accelerated charge, utilize the source side injection effect to carry out the memory cell sequencing, make the passage of auxiliary grid charge to setting voltage in advance, and can fast sequencing memory cell.And, utilize to select the grid memory cell of erasing, make electronics remove via selecting grid, can reduce the number of times that electronics passes through tunneling dielectric layer, and improve the element reliability.In addition, electric charge storage layer is in abutting connection with selecting the grid part to have corner.When erasing, by this corner electric field is concentrated, be drawn out to the erase operation for use speed of selecting grid from electric charge storage layer and can improve electronics.
The manufacture method of non-volatility memorizer of the present invention then, is described.Fig. 5 A to Fig. 5 G is the flow process schematic cross-section of the manufacture method of the non-volatility memorizer showed according to embodiments of the invention.
At first, please refer to Fig. 5 A, substrate 200 is provided.This substrate 200 for example is a silicon substrate.Cambium layer dielectric layer 202 on substrate 200.The material of dielectric layer 202 for example is a silica, and the formation method of dielectric layer 202 for example is a thermal oxidation method.Then, on dielectric layer 202, form one deck electric charge storage layer 204.The material of electric charge storage layer 204 for example is that conductor material (as doped polycrystalline silicon) maybe can make electric charge be absorbed in material wherein, for example silicon nitride, silicon oxynitride, tantalum oxide, strontium titanates or hafnium oxide etc.When the material of electric charge storage layer 204 is doped polycrystalline silicon, its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, carry out the ion implantation step to form it, perhaps also can adopt the mode of injecting admixture when participating in the cintest to form it with chemical vapour deposition technique.And when electric charge storage layer 204 was conductor material, this electric charge storage layer 204 for example was (not show) into strips.
Then, forming dielectric layer 206 between door on the substrate 200.The material of dielectric layer 206 for example is a silicon oxide/silicon nitride/silicon oxide between door, and its formation method for example is after forming one deck silicon oxide layer with thermal oxidation method earlier, to utilize chemical vapour deposition technique to form one deck silicon nitride layer and another layer silicon oxide layer successively again.Certainly, the material of dielectric layer 206 also can be silica or nitrogenize silicon/oxidative silicon etc. between the door.
Then, please refer to Fig. 5 B, on dielectric layer between door 206, form one deck conductor layer (not showing) and one deck cap layer (not showing).Then, dielectric layer 206 between pattern cap layer, conductor layer and door is to form a plurality of stack layers 212 that are made of dielectric layer 206a, conductor layer 208 and cap layer 210 between door.The material of conductor layer 208 for example is a doped polycrystalline silicon, its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, carry out the ion implantation step to form it, perhaps also can adopt the mode of injecting admixture when participating in the cintest to form it with chemical vapour deposition technique.Conductor layer 208 for example is as the control grid.The material of cap layer 210 for example is silicon nitride or silica, and its formation method for example is a chemical vapour deposition technique.
Then, please refer to Fig. 5 C, on substrate 200, form the mask layer 214 of a layer pattern.The mask layer 214 of this pattern has opening 216, and this opening 216 exposes the conductor layer 204 between per two stack layers 212 at least.Then, the mask layer 214 of pattern is a mask, removes the conductor layer 204 between per two stack layers 212, to form groove 218.The formation method of above-mentioned groove 218 for example is to carry out etch process, removes conductor layer 204 between per two stack layers 212 to exposing dielectric layer 202 surfaces.The material of patterned mask layer 214 for example is a photo anti-corrosion agent material, and the formation method of the mask layer 214 of pattern for example is a photoetching process.
Continue it, please refer to Fig. 5 D, remove the mask layer 214 of pattern.The method that removes the mask layer 214 of pattern for example is after removing most mask layer with plasma ashing technology earlier, to carry out wet-cleaned technology again.Afterwards, in stack layer 212 sidewalls and groove 214 sidewalls, form clearance wall 220.The material of clearance wall 220 for example is silicon nitride or other dielectric material.The formation method of clearance wall 220 for example is to form one deck spacer material layer earlier, with the conformal whole base plate 200 that covers.Then, carry out anisotropic etching process, remove part spacer material layer, to form it.
Then, please refer to Fig. 5 E, is mask with clearance wall 220, stack layer 212, removes the conductor layer 204 that is exposed, to form electric charge storage layer 204a below each stack layer 212.Wherein the dielectric layer 202 between electric charge storage layer 204a and substrate 200 for example is as tunneling dielectric layer.Then, on substrate, form conformal dielectric layer 222.The material of dielectric layer 222 for example is the high-temperature thermal oxidation silicon layer, and its formation method for example is the high-temperature thermal oxidation method.
Subsequently, please refer to Fig. 5 F, between two stack layers 212, form conductor layer 224, and in the sidewall in two stack layers, 212 outsides, form conductor layer 226 respectively.Conductor layer 224 fills up groove 218.The material of conductor layer 224 and conductor layer 226 for example is a doped polycrystalline silicon, its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, carry out the ion implantation step to form it, perhaps also can adopt the mode of injecting admixture when participating in the cintest to form it with chemical vapour deposition technique.Utilize said method elder generation after forming one deck doped polysilicon layer on the substrate 200, carry out etch back process (anisotropic etching process) and remove the part doped polysilicon layer, can form conductor layer 224 and conductor layer 226 up to exposing cap layer 210.Conductor layer 224 for example is as auxiliary grid.Dielectric layer 222 between conductor layer 224 and substrate 200 and dielectric layer 202 for example are as the auxiliary grid dielectric layer.Conductor layer 226 for example is as selecting grid.Dielectric layer 222 between conductor layer 226 and substrate 200 and dielectric layer 202 for example are as selecting gate dielectric.Wherein the thickness summation of dielectric layer 222 and dielectric layer 202 for example is between 120 dust to 130 dusts.
Then, in the substrate 200 in two stack layers, 212 outsides, form doped region 228 respectively.This doped region 228 for example is as the drain region.The formation method of doped region 228 for example is to carry out ion implantation technology.Wherein, conductor layer 226 for example is formed on the substrate 200 between doped region 228 and the conductor layer 208.
Subsequently, please refer to Fig. 5 G, on substrate 200, form interlayer insulating film 230.The material of interlayer insulating film 230 for example is silica, phosphorosilicate glass, boron-phosphorosilicate glass or other dielectric material that is fit to, and its formation method for example is a chemical vapour deposition technique.Then, in interlayer insulating film 230, form the connector 232 that is electrically connected with doped region 228.The formation method of connector 232 for example is first pattern interlayer insulating film 230 to form the opening that exposes doped region 228, inserts conductor material then in opening and forms it.
Afterwards, on interlayer insulating film 230, form the conductor layer 234 that is electrically connected with connector 232.Conductor layer 234 for example is as bit line.The follow-up technology of finishing non-volatility memorizer is known by those skilled in the art, does not repeat them here.
In the manufacture method of non-volatility memorizer of the present invention, owing to adopt the mode of aiming at voluntarily to form auxiliary grid (conductor layer 224) and selection grid (conductor layer 226), do not need to use photoetching process, therefore can save manufacturing cost, increase process allowance.
And, because formed electric charge storage layer 204a has a corner near the part of selecting grid (conductor layer 226), therefore when memory cell is erased, by this corner electric field is concentrated, be drawn out to the erase operation for use speed of selecting grid (conductor layer 226) from electric charge storage layer 204a and can improve electronics.
In sum, multi-level non-volatile memory body of the present invention, two adjacent memory cell for example are with the configuration of mirror image symmetrical manner, that is shared auxiliary grid of two adjacent memory cell or doped region, therefore can improve the integrated level of element.
And, when opening the passage below the auxiliary grid when being applied with voltage on the auxiliary grid and forming inversion layer, apply voltage at inversion layer, make the inversion layer of auxiliary grid below can be in pre-charge state.When sequencing non-volatility memorizer of the present invention, by the mode of self-accelerated charge injection (self-boosted-charge injection), utilize the source side injection effect to carry out the memory cell sequencing, can improve sequencing speed.And when this non-volatility memorizer during as multi-level cell memory, accurately the start voltage of control store unit after sequencing is positioned at the scope that sets when programming operations.
In addition, because formed electric charge storage layer has a corner near the part of selecting grid, therefore when memory cell is erased, electric field is concentrated, be drawn out to the erase operation for use speed of selecting grid from electric charge storage layer and can improve electronics by this corner.
In addition, multi-level non-volatile memory body manufacture method of the present invention is simple, can reduce manufacturing cost, and increases process allowance.
Though the present invention discloses as above with embodiment; yet it is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; can carry out a little change and modification to it, so protection scope of the present invention is with being as the criterion that claims were defined.
Claims (44)
1. multi-level non-volatile memory body comprises:
First memory cell is arranged on the substrate, and this first memory cell comprises:
The control grid is arranged on this substrate;
Electric charge storage layer is arranged between this control grid and this substrate;
Doped region is arranged in this substrate of first side of this control grid;
Select grid, be arranged on the sidewall of this first side of this control grid, and on this substrate between this control grid and this doped region; With
Auxiliary grid is arranged on the sidewall of second side of this control grid, and when applying voltage on this auxiliary grid, forms inversion layer in this substrate of this auxiliary grid below.
2. multi-level non-volatile memory body as claimed in claim 1 also comprises:
First dielectric layer is arranged between this electric charge storage layer and this substrate;
Second dielectric layer is arranged between this electric charge storage layer and this control grid;
The 3rd dielectric layer is arranged between this auxiliary grid and this control grid, this electric charge storage layer, and between this auxiliary grid and this substrate; With
The 4th dielectric layer is arranged between this selection grid and this control grid, this electric charge storage layer, and should select between grid and this substrate.
3. multi-level non-volatile memory body as claimed in claim 2 wherein is formed with clearance wall between the 3rd dielectric layer and this control grid, this electric charge storage layer.
4. multi-level non-volatile memory body as claimed in claim 2 wherein is formed with clearance wall between the 4th dielectric layer and this control grid.
5. multi-level non-volatile memory body as claimed in claim 2, wherein the material of this first dielectric layer comprises silica.
6. multi-level non-volatile memory body as claimed in claim 2, wherein the material of this second dielectric layer comprises silicon oxide/silicon nitride/silicon oxide.
7. multi-level non-volatile memory body as claimed in claim 2, wherein the 3rd dielectric layer and the 4th dielectric layer are thermal oxide.
8. multi-level non-volatile memory body as claimed in claim 2, wherein the thickness of the thickness of the 3rd dielectric layer and the 4th dielectric layer is between 100 dust to 200 dusts.
9. multi-level non-volatile memory body as claimed in claim 1, also comprise second memory cell, this second memory cell has identical structure with this first memory cell, and this second memory cell and this first memory cell with the mirror image symmetrical manner in abutting connection with setting.
10. multi-level non-volatile memory body as claimed in claim 9, wherein this second memory cell is arranged on this first side of this first memory cell, and shares this doped region with this first memory cell.
11. multi-level non-volatile memory body as claimed in claim 9, wherein this second memory cell is arranged on this second side of this first memory cell, and shares this auxiliary electrode with this first memory cell.
12. multi-level non-volatile memory body as claimed in claim 1 also comprises cap layer, is arranged on this control grid.
13. multi-level non-volatile memory body as claimed in claim 12 wherein protrudes in to this electric charge storage layer part of horizontal this control grid, and has corner in abutting connection with the position of this selection grid.
14. a multi-level non-volatile memory body comprises:
A plurality of memory cell are arranged to delegation/column array on substrate, respectively this memory cell comprises:
The control grid is arranged on this substrate;
Electric charge storage layer is arranged between this control grid and this substrate;
Doped region is arranged in this substrate of first side of this control grid;
Select grid, be arranged on the sidewall of this first side of this control grid, and on this substrate between this control grid and this doped region; With
Auxiliary grid is arranged in the sidewall of second side of this control grid, wherein with those memory cell in the delegation with the mirror image symmetrical manner in abutting connection with setting;
Multiple bit lines is arranged in parallel on line direction, connects this doped region with this memory cell of delegation;
Many control gate line are arranged in parallel on column direction, connect this control grid of this memory cell of same row;
Select gate line for many, on column direction, be arranged in parallel, connect this selection grid of this memory cell of same row;
Many supplementary gate polar curves are arranged in parallel on column direction, connect this auxiliary grid of this memory cell of same row; With
A plurality of transistors, this transistor drain connect this substrate of this supplementary gate polar curve below respectively.
15. multi-level non-volatile memory body as claimed in claim 14 also comprises:
First dielectric layer is arranged between this electric charge storage layer and this substrate;
Second dielectric layer is arranged between this electric charge storage layer and this control grid;
The 3rd dielectric layer is arranged between this auxiliary grid and this control grid, this electric charge storage layer, and between this auxiliary grid and this substrate; With
The 4th dielectric layer is arranged between this selection grid and this control grid, this electric charge storage layer, and should select between grid and this substrate.
16. multi-level non-volatile memory body as claimed in claim 15 wherein is formed with clearance wall between the 3rd dielectric layer and this control grid, this electric charge storage layer.
17. multi-level non-volatile memory body as claimed in claim 15 wherein is formed with clearance wall between the 4th dielectric layer and this control grid.
18. multi-level non-volatile memory body as claimed in claim 15, wherein the material of this first dielectric layer comprises silica.
19. multi-level non-volatile memory body as claimed in claim 15, wherein the material of this second dielectric layer comprises silicon oxide/silicon nitride/silicon oxide.
20. multi-level non-volatile memory body as claimed in claim 15, wherein the 3rd dielectric layer and the 4th dielectric layer are thermal oxide.
21. multi-level non-volatile memory body as claimed in claim 14 wherein protrudes in to this electric charge storage layer part of horizontal this control grid, and has corner in abutting connection with the position of this selection grid.
22. multi-level non-volatile memory body as claimed in claim 14, wherein adjacent two memory cell of mirror images of each other symmetry are shared this drain region.
23. multi-level non-volatile memory body as claimed in claim 14, wherein adjacent two memory cell of mirror images of each other symmetry are shared this auxiliary grid.
24. the manufacture method of a multi-level non-volatile memory body comprises:
On substrate, form tunneling dielectric layer, electric charge storage layer successively;
Form at least two stack layers on this electric charge storage layer, wherein respectively this two stack layer comprises dielectric layer between door, control grid and cap layer successively;
Remove this electric charge storage layer between this two stack layer, to form first groove;
In this two stack layers sidewall and this first trenched side-wall, form clearance wall;
Remove this electric charge storage layer in this two stack layers outside as mask with this clearance wall;
On this substrate, form dielectric layer;
Between this two stack layer, form auxiliary grid, and in the sidewall in this two stack layers outside, form the selection grid respectively; And
In this substrate in this two stack layers outside, form doped region respectively, and should select grid between this stack layer and this doped region.
25. the manufacture method of multi-level non-volatile memory body as claimed in claim 24, wherein this dielectric layer comprises thermal oxide.
26. the manufacture method of non-volatility memorizer as claimed in claim 24, wherein the thickness of this dielectric layer is between 100 dust to 200 dusts.
27. the manufacture method of non-volatility memorizer as claimed in claim 24 wherein forms this auxiliary grid between this two stack layer, and the method that forms this selection grid in the sidewall in this two stack layers outside respectively comprises:
Form conductor material layer on this substrate, this conductor material layer fills up this first groove; And
Carry out etch back process, remove this conductor material layer of part, up to exposing this cap layer.
28. the manufacture method of multi-level non-volatile memory body as claimed in claim 24, wherein the material of this tunneling dielectric layer comprises silica.
29. the manufacture method of multi-level non-volatile memory body as claimed in claim 24, wherein the formation method of this tunneling dielectric layer comprises thermal oxidation method.
30. the manufacture method of multi-level non-volatile memory body as claimed in claim 24, wherein the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between this door.
31. the manufacture method of multi-level non-volatile memory body as claimed in claim 24, wherein the material of this electric charge storage layer comprises doped polycrystalline silicon.
32. the method for operation of a multi-level non-volatile memory body is applicable to memory cell, this memory cell comprises: the control grid is arranged on the substrate; Electric charge storage layer is arranged between this control grid and this substrate; The drain region is arranged in this substrate of first side of this control grid; Select grid, be arranged on the sidewall of this first side of this control grid, and on this substrate between this control grid and this doped region; And auxiliary grid, being arranged in the sidewall of second side of this control grid, this method comprises:
When carrying out programming operations, on this auxiliary grid, apply first voltage in advance, forming inversion layer in this substrate below this auxiliary grid, and on this inversion layer, apply second voltage; And
On this control grid, apply tertiary voltage, on this selection grid, apply the 4th voltage, on this drain region, apply the 5th voltage, wherein this first voltage is greater than the start voltage of this auxiliary grid, this tertiary voltage is greater than this first voltage, the 4th voltage is more than or equal to this start voltage of selecting grid, and this second voltage is greater than the 5th voltage, to utilize this memory cell of source side injection effect sequencing.
33. the method for operation of multi-level non-volatile memory body as claimed in claim 32, wherein this first voltage is about 8 volts; This second voltage is about 5 volts; This tertiary voltage is about 10 volts; The 4th voltage is about 1.5 volts; The 5th voltage is about 0 volt.
34. the method for operation of multi-level non-volatile memory body as claimed in claim 32, also be included in when carrying out erase operation for use, on this selection grid, apply the 6th voltage, so that the electronics that is stored in this electric charge storage layer is drawn out and removes via this selection grid, wherein the voltage difference between the 6th voltage and this substrate can cause the FN tunneling effect.
35. the method for operation of multi-level non-volatile memory body as claimed in claim 34, wherein the 6th voltage is about 11 to 15 volts.
36. the method for operation of multi-level non-volatile memory body as claimed in claim 32, also be included in when carrying out read operation, on this auxiliary grid, apply the 7th voltage, on this control grid, apply the 8th voltage, on this selection grid, apply the 9th voltage, apply the tenth voltage on this drain region, to read this memory cell, the 9th voltage is selected the start voltage of grid greater than this.
37. the method for operation of non-volatility memorizer as claimed in claim 36, wherein the 7th voltage is Vcc (supply voltage), and the 8th voltage is about 1.4 volts, and the 9th voltage is Vcc (supply voltage), and the tenth voltage is about 1.5 volts.
38. the method for operation of a multi-level non-volatile memory body is applicable to the memory cell array that is made of a plurality of memory cell, respectively this memory cell comprises: the control grid is arranged on the substrate; Electric charge storage layer is arranged between this control grid and this substrate; The drain region is arranged in this substrate of first side of this control grid; Select grid, be arranged on the sidewall of this first side of this control grid, and on this substrate between this control grid and this doped region; And auxiliary grid, be arranged in the sidewall of second side of this control grid, wherein with this memory cell in the delegation with the mirror image symmetrical manner in abutting connection with setting; Multiple bit lines is arranged in parallel on line direction, connects this drain region with this memory cell of delegation; Many control gate line are arranged in parallel on column direction, connect this control grid of this memory cell of same row; Select gate line for many, on column direction, be arranged in parallel, connect this selection grid of this memory cell of same row; Many supplementary gate polar curves are arranged in parallel on column direction, connect this auxiliary grid of this memory cell of same row; With a plurality of transistors, this transistor drain connects this substrate of this supplementary gate polar curve below, and this method comprises:
When carrying out programming operations, on this transistorized grid, apply first voltage in advance, on this transistorized source electrode, apply second voltage, on this supplementary gate polar curve, apply tertiary voltage, to form inversion layer in this substrate below this supplementary gate polar curve, and make this inversion layer conducting that this second voltage be arranged, close this transistorized passage afterwards, make this inversion layer be in pre-charge state; And
On this selected control gate line, apply the 4th voltage, on this selected selection gate line, apply the 5th voltage, on this selected bit line, apply the 6th voltage, wherein this tertiary voltage is greater than the start voltage of this auxiliary grid, the 4th voltage is greater than this tertiary voltage, the 5th voltage is more than or equal to this start voltage of selecting grid, and this second voltage is greater than the 6th voltage, to utilize source side injection effect sequencing selected memory cell.
39. the method for operation of multi-level non-volatile memory body as claimed in claim 38, wherein this first voltage is Vcc (supply voltage); This second voltage is Vcc (supply voltage)-Vth (those transistorized starting voltages); This tertiary voltage is Vcc (supply voltage); The 4th voltage is about 10 volts; The 5th voltage is about 1.5 volts; The 6th voltage is about 0 volt.
40. the method for operation of multi-level non-volatile memory body as claimed in claim 38 is wherein closed after this transistorized passage, auxiliary grid voltage is drawn high to about 8 volts, with about the voltage to 5 of this inversion layer that is coupled volt.
41. the method for operation of multi-level non-volatile memory body as claimed in claim 38, also be included in when carrying out erase operation for use, on this selection grid, apply the 7th voltage, so that the electronics that is stored in this electric charge storage layer is drawn out and removes via this selection gate line, wherein the voltage difference between the 7th voltage and this substrate can cause the FN tunneling effect.
42. the method for operation of multi-level non-volatile memory body as claimed in claim 41, wherein the 7th voltage is about 11 to 15 volts.
43. the method for operation of multi-level non-volatile memory body as claimed in claim 38, also be included in when carrying out read operation, on this selected supplementary gate polar curve, apply the 8th voltage, on selected this control gate line, apply the 9th voltage, on this selected selection gate line, apply the tenth voltage, apply the 11 voltage on this selected bit line, to read this memory cell, the tenth voltage is selected the start voltage of grid greater than this.
44. the method for operation of non-volatility memorizer as claimed in claim 43, wherein the 8th voltage is Vcc (supply voltage), and the 9th voltage is about 1.4 volts, and the tenth voltage is Vcc (supply voltage), and the 11 voltage is about 1.5 volts.
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