KR100660022B1 - 2-bit non-volatile memory device and method of manufacturing the same - Google Patents

Abstract

In a 2-bit nonvolatile memory device, a first impurity region and a second impurity region are formed which are separated by a recess formed in a surface portion of a substrate and function as bit lines extending along a first direction, respectively. The first insulating film pattern is formed on the first and second impurity regions separated by the recesses. A second insulating film is formed on the side surfaces and the bottom surface of the recess. First charge trapping spacers and second charge trapping spacers are formed on side surfaces of the second insulating layer adjacent to the first and second impurity regions, respectively. A third insulating film is formed on the first and second charge trapping spacers. A gate electrode is formed on the first and third insulating layers so as to be electrically insulated from the first and second impurity regions, and serves as a word line extending in a second direction perpendicular to the first direction. As such, the charge trapping spacers have respective charge storage regions, and thus may serve as storage nodes for storing 2-bit information.

Description

2-bit non-volatile memory device and method of manufacturing the same

1 is a schematic cross-sectional view for describing a 2-bit nonvolatile memory device according to a first embodiment of the present invention.

2 is a schematic cross-sectional view for describing a 2-bit nonvolatile memory device according to a second embodiment of the present invention.

3 is an electrical equivalent circuit diagram of the 2-bit nonvolatile memory device illustrated in FIGS. 1 and 2.

FIG. 4 is a plan view illustrating the 2-bit nonvolatile memory device illustrated in FIGS. 1 and 2.

5 through 9 are cross-sectional views and plan views illustrating a process of manufacturing a 2-bit nonvolatile memory device according to a first embodiment of the present invention.

10 is a cross-sectional view for describing a step of manufacturing a 2-bit nonvolatile memory device according to the second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: semiconductor substrate 20: recess

30: channel 100, 200: 2-bit nonvolatile memory device

104: gate electrode 106: word line

107, 108, 109: bit line 110: composite insulating film

112: second insulating film 114a, 114b: first and second charge trapping spacers

116: third insulating film 118: fourth insulating film

120 impurity layer 122 first impurity region

124: second impurity region 132: first insulating film

134: first insulating film pattern A: first charge storage region

B: second charge storage region T: unit transistor

The present invention relates to a non-volatile memory device. More specifically, it relates to a 2-bit nonvolatile memory device.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), have relatively fast data input and output, while volatile memory devices lose data over time, and ROM Although data input and output is relatively slow, such as read only memory, it can be classified as a non-volatile memory device that can store data permanently. In the case of the nonvolatile memory device, there is an increasing demand for an electrically erasable programmable read only memory (EEPROM) or a flash EEPROM memory capable of electrically inputting / outputting data. The flash EEPROM memory device electrically performs programming and erasing of data using F-N tunneling or channel hot electron injection. The flash memory device may be classified into a floating gate type nonvolatile memory device and a SONOS type nonvolatile memory device.

Recently, various attempts have been made in response to the demand for improving the integration density of semiconductor devices. For example, US Patent No. 5,834,808 (issued to Tsukiji) has a nonvolatile device having one control gate and two floating gates. A memory device is disclosed, and US Pat. No. 6,649,972 (issued to Eitan) includes a two-bit nonvolatile semiconductor memory comprising two diffusion regions formed in a substrate, a channel formed between them, and an oxide-nitride-oxide (ONO) film. A cell is disclosed. According to US Pat. No. 6,649,972, the ONO film includes a first oxide film, a nitride film, and a second oxide film, the nitride film having a thickness of less than 100 GPa and two charge storage regions.

However, despite such attempts, there is still a need for improving the integration density of semiconductor devices, and in the case of the above patents, non-volatile by improving the structure of the floating gate or the method of using the nitride film used as the data storage film Although the storage density of data of the memory device is improved, the size reduction of the nonvolatile memory device is very limited since the floating gate and the nitride film are formed in the horizontal direction.

SUMMARY OF THE INVENTION A first object of the present invention for solving the above problems is to provide a 2-bit nonvolatile memory device having improved data density and capable of reducing cell size.

A second object of the present invention is to provide a method of manufacturing the nonvolatile memory device as described above.

A 2-bit nonvolatile memory device according to a first embodiment of the present invention for achieving the first object is separated by a recess formed in a surface portion of a substrate and extends in a first direction crossing the semiconductor substrate. A first impurity region and a second impurity region each functioning as a bit line, a first insulating layer pattern provided on the first and second impurity regions separated by the recess, side surfaces of the recess, and A second insulating film formed on the bottom surface, a first charge trapping spacer and a second charge trapping spacer formed on side surfaces of the second insulating film adjacent to the first and second impurity regions, respectively, and the first And a third insulating film formed on the second charge trapping spacer, and filling the recess on the first and third insulating films so as to be electrically insulated from the first and second impurity regions. And a gate electrode functioning as a word line extending in a second direction substantially perpendicular to the second direction.

A 2-bit nonvolatile memory device according to a second embodiment of the present invention for achieving the first object is separated by a recess formed in a surface portion of a substrate and extends along a first direction across the semiconductor substrate. A first impurity region and a second impurity region respectively functioning as bit lines, a first insulating layer pattern provided on the first and second impurity regions separated by the recess, and side surfaces of the recess; A first charge trapping spacer and a second charge trapping spacer formed adjacent to each other, a side surface and a bottom of the recess, a second insulating film formed between the first and second charge trapping spacers, and the first and the A third insulating film formed on a second charge trapping spacer, a fourth insulating film formed on a bottom surface of the recess between the first and second charge trapping spacers, and the first and second impurity regions And electrically so that embedding the recesses on the first and the third insulating film, and insulated from the gate electrode serving as a word line extending in a second direction substantially perpendicular to the first direction.

The first and second charge trapping spacers may be silicon nitride (SiN), amorphous silicon (amorphous-Si), polysilicon (poly-Si), nano-crystal material, or high-K dielectric. The first and second charge trapping spacers may be formed of a material, or the like, and have a thickness of about 30 μs to about 200 μs. The second insulating film and the third insulating film are preferably formed of silicon oxide, a high dielectric film, or the like.

In addition, a channel is formed along the surface of the recess between the first impurity region and the second impurity region.

Thus, the charge trapping spacers each function as a storage node for storing 1-bit information, so that the nonvolatile memory device can store 2-bit information. Therefore, the data density of the nonvolatile memory device can be improved.

In the manufacturing method of the 2-bit nonvolatile memory device according to the first embodiment of the present invention for achieving the second object, first, an impurity layer in the form of a blanket is formed on the surface of the substrate. Next, a recess is formed in a surface portion of the substrate, and is separated from the impurity layer into first impurity regions and second impurity regions respectively functioning as bit lines extending along a first direction across the semiconductor substrate. . Subsequently, a first insulating layer pattern is formed on the first and second impurity regions separated by the recesses. A second insulating film is formed on the side surfaces and the bottom surface of the recess. A first charge trapping spacer and a second charge trapping spacer are formed on the side surfaces of the second insulating layer adjacent to the first and second impurity regions, respectively. A third insulating film is formed on the first and second charge trapping spacers and the second insulating film. Finally, the recess is formed on the first and third insulating layers to be electrically insulated from the first and second impurity regions, and extends in a second direction substantially perpendicular to the first direction. A gate electrode that functions as a word line is formed to complete a 2-bit nonvolatile memory device.

A method of manufacturing a 2-bit nonvolatile memory device in accordance with a second embodiment of the present invention for achieving the second object includes: presenting between the first and second charge trapping spacers after forming the second insulating layer. The second and third insulating layers on the bottom of the recess are anisotropically etched to partially expose the bottom of the recess. Subsequently, the method may further include forming a fourth insulating layer on the bottom of the exposed recess.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic cross-sectional view illustrating a 2-bit nonvolatile memory device according to a first embodiment of the present invention, and FIG. 2 illustrates a 2-bit nonvolatile memory device according to a second embodiment of the present invention. 3 is an electrical equivalent circuit diagram of a unit transistor in the 2-bit nonvolatile memory device shown in FIGS. 1 and 2, and FIG. 4 is a 2-bit nonvolatile memory shown in FIGS. 1 and 2. It is a top view for demonstrating an apparatus.

1, 3, and 4, the unit transistor T of the 2-bit nonvolatile memory device 100 according to the embodiment may be perpendicular to a surface portion of the semiconductor substrate 10 such as a silicon wafer. The gate electrode 104 is buried in the recess 20 and the word line 106 is connected to the gate electrode 104. The composite insulating layer 110 is formed between the gate electrode 104 and the sidewalls of the recess 20, and the first and second portions separated by the recess 20 are formed at side portions of the recess 20. Impurity regions 122 and 124 and a first insulating film pattern 134 are formed, respectively. The first and second impurity regions 122 and 124 function as bit lines 107 and 108, respectively. The first insulating layer pattern 134 may be formed of silicon nitride (SiN), and electrically insulates the word line 106 and the bit lines 107 and 108. A pad oxide layer 130 may be formed between the impurity regions 122 and 124 and the first insulating layer pattern 134. The gate electrode 104 is formed in the recess 20 and may be made of doped poly-Si or metal containing N type or P type impurities.

The composite insulating layer 110 may include a second insulating layer 112 serving as a tunnel oxide layer, first and second charge trapping spacers 114a and 114b and a blocking oxide layer for trapping charges, respectively. and a third insulating film 116 functioning as a layer. The second insulating layer 112 is formed on the bottom and side surfaces of the recess 20, and the respective charge trapping spacers 114a and 114b face the sides of the gate electrode 104. And a third insulating layer 116 formed on the charge trapping spacers 114a and 114b, the second insulating layer 112 on the bottom surface of the recess 20, and the first insulating layer pattern 134. Is formed. A channel 30 is formed along the surface of the recess 20 between the first impurity region 122 and the second impurity region 124.

As described above, when the charge trapping spacer 114 is interposed between the second and third insulating layers 112 and 116, the charge trapping spacer 114 is formed to have a thickness of 30 μm to 200 μm using silicon nitride. The second and third insulating films 112 and 116 may be formed of silicon oxide or a high dielectric insulating film. Alternatively, the charge trapping spacer 114 is formed as a floating gate made of amorphous silicon, polysilicon, metal, nanocrystal, high dielectric material, and the like, so that a storage node such as the oxide-nitride-oxide film (ONO) is formed. You can also perform the function of.

FIG. 2 is a cross-sectional view illustrating a 2-bit nonvolatile memory device 200 according to a second embodiment of the present invention, which is the same as the 2-bit nonvolatile memory device 100 according to the first embodiment shown in FIG. 1. Since the members have a structure similar to that described above with reference to FIG. 1, detailed descriptions thereof will be omitted.

2, a first charge trapping spacer 114a and a second charge trapping spacer 114b are provided adjacent to side surfaces of the recess 20. A second insulating layer 112 is provided between the side surfaces and the bottom surface of the recess 20 and the first and second charge trapping spacers 114a and 114b. A third insulating layer 116 is provided on the first charge trapping spacer 114a and the second charge trapping spacer 114b. A fourth insulating layer 118 is provided on the bottom surface of the recess 20 between the first charge trapping spacer 114a and the second charge trapping spacer 114b. The fourth insulating layer 118 may be formed of an oxide film, and may be formed using a thermal oxidation process or the like. Accordingly, a fourth insulating layer 118 is provided between the channel 30 region under the recess 20 and the gate electrode 104. The gate electrode 104 formed to fill the recess 20 is provided on the third insulating layer 116 and the fourth insulating layer 118.

Although not shown, before forming the third insulating layer 114, the second insulating layer 112 existing on the bottom surface of the recess 20 between the first and second trapping spacers 114a and 114b. It may be removed using an anisotropic etching process to expose the substrate 10. Then, only the third insulating layer 116 is provided between the channel 30 region below the recess 20 and the gate electrode 104.

Therefore, the threshold voltage may be adjusted by varying the thickness of the insulating layer provided between the channel 30 region and the gate electrode 104.

The unit transistors T of the 2-bit nonvolatile memory devices 100 and 200 as illustrated in FIGS. 1 and 2 may be represented by an electrical equivalent circuit as illustrated in FIG. 3. Here, equivalent elements shown in FIG. 3 are represented by the same reference numerals as in FIG. 1. The gate electrode 104 is connected to the word line 106 and is capacitively coupled with the charge trapping spacer 114. The first and second impurity regions 122 and 124 are spaced apart from each other by the recess 20. Specifically, the first and second impurity regions 122 and 124 are positioned to face each other with respect to the recess 20, and the recess is formed between the first impurity region 122 and the second impurity region 124. A channel 30 is formed along the surface of 20. The second insulating layer 112 or the fourth insulating layer 118 is positioned between the channel 30 and the charge trapping spacers 114a and 114b, and the gate electrode 104 and the charge trapping spacers 114a and 114b are disposed. Are each insulated from each other by the third insulating film 116.

The first and second impurity regions 122 and 124 may be formed by implanting impurities into the upper surface portion of the semiconductor substrate 10 through an ion implantation process, or may be formed by doped silicon epitaxial growth. have. If the semiconductor substrate 10 is a P-type substrate, impurities implanted into the first and second impurity regions 122 and 124 may be formed in an N type to form a junction. On the contrary, if the substrate 10 is an N type substrate, impurities implanted into the first and second impurity regions 122 and 124 may be formed in a P type to form a junction.

A cell array of the 2-bit nonvolatile memory devices 100 and 200 as illustrated in FIGS. 1 and 2 may be briefly represented as shown in FIG. 4.

Referring to FIG. 4, the impurity regions 122, 124, and 126, that is, the bit lines 107, 108, and 109, extend along a first direction across the semiconductor substrate 10, and the gate electrode 104 may be formed. It is connected to a word line 106 extending in a second direction substantially perpendicular to the first direction. Here, since the impurity regions 122, 124, and 126 are themselves bit lines 107, 108, and 109, there is no need to form separate bit lines and contact plugs connecting the bit lines and the impurity regions. That is, as is well known, since the formation of the bit line and the contact plug is a barrier against the improvement of the degree of integration of the semiconductor device, the semiconductor device according to an embodiment of the present invention can easily improve the degree of integration.

Each of the impurity regions 122 and 124 functions as a source or a drain depending on voltages applied to the word line 106 and the bit lines 107 and 108. When programming voltages for programming (or writing) are applied to the gate electrode 104 and one of the impurity regions 122 and 124, the first impurity region 122 and the second impurity region 124 may be used. Channels are formed along the sides and bottom of the recess 20. For example, when programming voltages are applied to the gate electrode 104 and the first impurity region 122, and the second impurity region 124 is grounded, The first impurity region 122 functions as a drain, and a channel 30 is formed from the first impurity region 122 to the second impurity region 124 along the sides and the bottom of the recess 20. Electrons move from the second impurity region 124 along the channel 30 to the first impurity region 122.

As shown, the charge trapping spacer 114 functions as a data storage node of the nonvolatile memory device 100 and is formed on the second insulating layer 112 on the side of the recess 20. have. The first charge storage region A is in the first charge trapping spacer 114a adjacent to the channel 30 and the second charge storage region B is in the second charge trapping spacer 114b adjacent to the channel 30. Has Specifically, the charge storage regions A and B are represented by circles indicated by dashed lines in FIG. 1.

Meanwhile, while electrons move along the channel 30, some of the electrons acquire sufficient energy to overcome the potential barrier of the second insulating layer 112, and the charge trapping spacer 114 Trap site). For example, when programming voltages are applied to the gate electrode 104 and the second impurity region 124, and the first impurity region 122 is grounded, electrons are transported along the channel 30 to the first impurity region 122. ), And some of the electrons are injected into the first charge storage region A adjacent to the second impurity region 124. Therefore, the threshold voltage of the portion of the channel 30 adjacent to the first charge storage region A increases between the first impurity region 122 and the second impurity region 124.

Since the charge storage regions A and B may store 1-bit information, the nonvolatile memory device 100 may store 2-bit information. In detail, logic states (or binary values '0' or '1') of '0' or '1' may be stored in the charge storage regions A and B, respectively. If each charge storage region (A, B) is programmed (e.g. a logic state of '0'), the channel current must be very low, on the contrary, each charge storage region (A, B) is not programmed. In this case (eg a logic state of '1'), the channel current should be relatively high. In particular, it is desirable to maximize the channel current difference between the logic states of '0' and '1' to distinguish between the logic states of '0' and '1'.

Thus, when the program is performed in the first forward storage area A in the first forward direction, it is preferable that reading is performed in the first reverse direction. This is because the threshold voltage of the entire channel 30 is determined by the programmed region when reading in the first reverse direction. On the contrary, when the first forward read is performed, the programmed region exists in the pinch-off region, and thus the influence on the threshold voltage of the channel 30 is minimal. The first forward direction refers to a direction of movement of electrons through the channel 30 while the first charge storage region A is programmed. The first reverse direction means a direction opposite to the first forward direction.

Specifically, read voltages are applied to the gate electrode 104 and the second impurity region 124 to read the information stored in the first charge storage region A in the first forward direction, and the first impurity region 122 Is grounded, the threshold voltage of the channel is relatively low because the electric fields formed by the read voltages are strongest in the vicinity of the second impurity region 124. However, in order to read information stored in the first charge storage region A in the first reverse direction, read voltages are applied to the gate electrode 104 and the first impurity region 122, and the second impurity region 124 is grounded. In this case, the threshold voltage of the channel is relatively high because the electric fields formed by the read voltages are relatively weak in the vicinity of the second impurity region 124. For example, in the first reverse read, the threshold voltage of the channel 30 is 4V or more, but in the first forward read, the threshold voltage of the channel 30 is kept below 1V. Therefore, in order to easily detect the current difference between the logic states of '0' and '1', it is preferable to apply reverse read. As an example, US Pat. No. 6,649,972 describes in detail the forward read and reverse read.

5 through 9 are cross-sectional views and plan views illustrating a process of manufacturing a 2-bit nonvolatile memory device according to a first embodiment of the present invention.

Referring to FIG. 5, an impurity layer 120 is formed on a semiconductor substrate 10 such as a silicon wafer in the form of a blanket. Subsequently, a first insulating layer 132 is formed on the impurity layer 120. The pad oxide layer 130 may be interposed between the impurity layer 120 and the first insulating layer 132. Specifically, the N type impurity layer 120 is formed on the semiconductor substrate 10 by ion implantation. Subsequently, the impurity layer 120 is completed by diffusing impurities implanted into the substrate through an annealing process. The annealing treatment may be carried out at a temperature of about 600 ℃ or more. Alternatively, the impurity layer 120 may be formed through doped silicon epitaxial growth. The first insulating layer 132 is preferably formed of silicon nitride (SiN).

6 and 7, a recess 20 is formed on the surface of the substrate 10 to separate the impurity layer 120 into a first impurity region 122 and a second impurity region 124. do. In detail, a first photoresist pattern (not shown) is formed on the first insulating layer 132. The first photoresist pattern is formed to expose a portion of the upper portion of the first insulating layer 132 in a first direction crossing the semiconductor substrate 10. Subsequently, the recess 20 is formed by anisotropically etching the exposed portions of the first insulating layer 132 and the substrate 10 using the first photoresist pattern as an etching mask. The anisotropic etching process uses a conventional dry etching method. The impurity layer 120 formed on the surface of the substrate 10 by the recess 20 is separated into first and second impurity regions 122 and 124, and a first insulating layer is formed from the first insulating layer 132. Pattern 134 is formed.

On the other hand, the silicon etching amount of the substrate 10 serves to adjust the distance between the storage node (not shown) and the first or second impurity (122, 124) region formed subsequently. It can be operated in 2-bit form only when the device stays in the pinch off region.

8 and 9, a second insulating film 112 is formed on the side surfaces and the bottom surface of the recess 20 to function as a tunnel oxide film. The second insulating layer 112 may be formed of silicon oxide or a high dielectric insulating layer, and may be formed through a low pressure CVD process or an ALD process.

The silicon nitride film 113 for charge trapping (SiN) is continuously formed along the recess 20 on the substrate on which the resultant is formed. Subsequently, the charge trapping silicon nitride layer 113 is partially etched to form charge trapping spacers 114a and 114b at side portions of the recess 20.

Specifically, the silicon nitride film 113 is etched using an anisotropic dry etching process or an etch back process. In this case, the first and second charge trapping spacers 114a and 114b formed from the silicon nitride film 113 may be adjacent to the second impurity region 124 and the first impurity region 122, respectively. To form on the sides. Since the charge trapping spacers 114a and 114b serve as storage nodes that respectively trap charges, the charge trapping spacers 114a and 114b are preferably formed to have a thickness of 30 μs to 200 μs.

Each of the charge trapping spacers 114a and 114b respectively stores 1-bit information, and the transistor having the above structure can be used to configure a 2-bit nonvolatile memory device.

Alternatively, the charge trapping spacer 114 is formed as a floating gate made of amorphous silicon, polysilicon, metal, nanocrystal, high dielectric material, and the like, so that a storage node such as the oxide-nitride-oxide film (ONO) is formed. You can also perform the function of.

Although not shown, in order to prevent damage to the semiconductor substrate 10 when performing an etch back process for forming the charge trapping spacer 114, a second pad oxide layer is formed before the silicon nitride layer is formed. can do.

Subsequently, a third insulating layer 116 is formed on the resultant including the charge trapping spacer 114 to function as a blocking oxide. The third insulating layer 116 may be formed of silicon oxide or a high dielectric insulating layer, and may be formed through a low pressure CVD process or an ALD process.

Referring back to FIGS. 1 to 3, a conductive layer (not shown) filling a recess 20 sufficiently on the third insulating layer 116 is formed, and the conductive layer is patterned to form a gate in the recess 20. A word line 106 extending in the second direction with the electrode 104 is formed.

Specifically, the conductive layer may be made of an impurity doped polysilicon or metal, LPCVD process, ALD process, physical vapor deposition (PVD) process, metal organic chemical vapor deposition (MOCVD) ) May be formed through a process or the like. Finally, by forming a second photoresist pattern (not shown) extending along the second direction on the conductive layer, and performing an anisotropic etching process using the second photoresist pattern as an etching mask. And word line 106. The second photoresist pattern forms a gate electrode 104 and a word line 106, and the second photoresist pattern is removed by stripping and ashing to remove the second photoresist pattern. The nonvolatile memory device 100 is completed.

10 is a cross-sectional view for describing a step of manufacturing a 2-bit nonvolatile memory device according to the second embodiment of the present invention.

Referring to FIG. 10, first, an impurity layer 120, a pad oxide layer 130, a first insulating layer 132, a recess 20, and impurity regions 122, 124, and 126 are formed on a semiconductor substrate 10. The first insulating layer pattern 134, the second insulating layer 112, the charge trapping silicon nitride layer 113, the charge trapping spacers 114a and 114b, and the third insulating layer 116 are formed. The elements as described above may be formed in the same manner as the parts previously described with reference to FIGS. 5 to 9, and thus, further detailed description thereof will be omitted.

After the third insulating layer 114 is formed as described above, the second and third insulating layers 112 existing on the bottom surface of the recess 20 between the first and second charge trapping spacers 114a and 114b are formed. 114 may be removed using an anisotropic etching process to partially expose the bottom of the recess 20, and to form a fourth insulating layer 118 made of an oxide film or the like on the exposed bottom of the recess 20. have. The fourth insulating layer 118 is preferably an oxide film, and may be formed using a thermal oxidation process or the like. Accordingly, a fourth insulating layer 118 is provided between the channel 30 region under the recess 20 and the gate electrode 104.

On the other hand, although not shown, unlike the method described above, the second insulating film 112 existing on the bottom surface of the recess 20 between the first and second trapping spacers 114a and 114b is formed on the substrate. It may be removed using an anisotropic etching process to expose (10), and to form a third insulating film 114 on the resultant. Then, only the third insulating layer 116 is provided between the channel 30 region below the recess 20 and the gate electrode 104. The threshold voltage may be adjusted by differently forming the thickness of the insulating layer provided between the channel 30 region and the gate electrode 104 using the above methods.

Referring back to FIG. 2, a conductive layer (not shown) filling the recess 20 sufficiently is formed on the resultant, and the patterned conductive layer is used to form the gate electrode 104 and the second in the recess 20. A word line 106 is formed extending along the direction. Specifically, the gate electrode 104 is formed by forming a third photoresist pattern (not shown) extending along the second direction on the conductive layer and performing an anisotropic etching process using the third photoresist pattern as an etching mask. And word line 106. The third photoresist pattern is formed by forming a gate electrode 104 and a word line 106, and then removing the third photoresist pattern through a strip process and an ashing process to form the 2-bit nonvolatile memory device 200 according to the second embodiment of the present invention. To complete.

According to the present invention as described above, the nonvolatile memory device forms a recess for separating the impurity layer formed on the surface portion of the semiconductor substrate, the two-bit storage node formed in the form of a spacer on both sides of the recess Has In addition, since the separated impurity regions may be used as bit lines, data density of the 2-bit nonvolatile memory device may be greatly improved.

In addition, the intensity of the threshold voltage can be easily adjusted by changing the thickness of the insulating film between the channel region and the gate electrode.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (12)

A first impurity region and a second impurity region separated by a recess formed in a surface portion of the substrate and respectively functioning as bit lines extending along a first direction across the semiconductor substrate; A first insulating film pattern provided on the first and second impurity regions separated by the recesses; A second insulating film formed on side surfaces and a bottom surface of the recess; First and second charge trapping spacers formed on side surfaces of the second insulating layer adjacent to the first and second impurity regions, respectively; A third insulating film formed on the first and second charge trapping spacers; And Filling the recess on the first and third insulating layers so as to be electrically insulated from the first and second impurity regions, and functioning as a word line extending in a second direction substantially perpendicular to the first direction. A 2-bit nonvolatile memory device comprising a gate electrode. The method of claim 1, wherein the first and second charge trapping spacers are silicon nitride (SiN), amorphous silicon (amorphos-Si), polysilicon (poly-Si), nano-crystal material or high dielectric 2-bit nonvolatile memory device, characterized in that it is formed of a (high-K dielectric) material. The 2-bit nonvolatile memory device of claim 2, wherein the first and second charge trapping spacers have a thickness of about 30 μs to about 200 μs. The 2-bit nonvolatile memory device of claim 1, wherein the second insulating film and the third insulating film are formed of silicon oxide or a high dielectric film. 2. The 2-bit nonvolatile memory device of claim 1, wherein a channel is formed along the surface of the recess between the first impurity region and the second impurity region. A first impurity region and a second impurity region separated by a recess formed in a surface portion of the substrate and respectively functioning bit lines extending in a first direction across the semiconductor substrate; A first insulating film pattern provided on the first and second impurity regions separated by the recesses; A first charge trapping spacer and a second charge trapping spacer formed adjacent to side surfaces of the recess; A second insulating film formed between side surfaces and a bottom surface of the recess and the first and second charge trapping spacers; A third insulating film formed on the first and second charge trapping spacers; A fourth insulating film formed on a bottom surface of the recess between the first and second charge trapping spacers; And Filling the recess on the first and third insulating layers so as to be electrically insulated from the first and second impurity regions, and functioning as a word line extending in a second direction substantially perpendicular to the first direction. A 2-bit nonvolatile memory device comprising a gate electrode. Forming a blanket-type impurity layer on a surface portion of the substrate; Forming a recess in a surface portion of the substrate, separating the impurity layer into a first impurity region and a second impurity region respectively functioning as bit lines extending along a first direction across the semiconductor substrate; Forming a first insulating film pattern on the first and second impurity regions separated by the recesses; Forming a second insulating film on side surfaces and a bottom surface of the recess; Forming a first charge trapping spacer and a second charge trapping spacer on the side surfaces of the second insulating layer adjacent to the first and second impurity regions, respectively; Forming a third insulating film on the first and second charge trapping spacers and the second insulating film; And A word line formed to fill the recess on the first and third insulating layers so as to be electrically insulated from the first and second impurity regions, and extending in a second direction substantially perpendicular to the first direction. A method of manufacturing a 2-bit nonvolatile memory device comprising forming a functioning gate electrode. 8. The method of claim 7, wherein after forming the third insulating film, the bottom surface of the recess is partially anisotropically etched by anisotropically etching the second and third insulating films on the bottom surface of the recess existing between the first and second charge trapping spacers. Exposing to; And And forming a fourth insulating film on the bottom surface of the exposed recess. 8. The 2-bit nonvolatile memory device of claim 7, wherein the first and second charge trapping spacers are formed of silicon nitride (SiN), amorphous silicon, polysilicon, nanocrystal material, or high dielectric material. Manufacturing method. The method of claim 7, wherein the first and second charge trapping spacers are formed to have a thickness of about 30 μs to about 200 μs. 10. The method of claim 7, wherein the second insulating film and the third insulating film are formed of silicon oxide or a high dielectric film. 8. The method of claim 7, wherein a channel is formed along the surface of the recess between the first impurity region and the second impurity region.

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