KR100877002B1 - Non volatile memory device having a silicon oxide nitride oxide silicon structure and method for manufacturing the same - Google Patents

Abstract

The present invention is to provide a non-volatile memory device having a sonos structure that can improve the degree of integration, and a method of manufacturing the same. To this end, the present invention provides a substrate on which a recess is formed and an exposed active region including the recess. A lower dielectric layer formed along the substrate surface step, first and second charge storage layers respectively formed on inner wall portions of the recesses to be electrically separated from each other in the recesses, and the first and second charge storage layers; A nonvolatile memory device having a sono structure having an upper dielectric layer formed along a surface step inside a recess in which a layer is formed, and a gate electrode formed on the upper dielectric layer to fill the recess is provided.

Sonos, charge storage layers, recesses, fins, nonvolatile memory devices

Description

Non-volatile memory device having a sonos structure and a method of manufacturing the same {NON VOLATILE MEMORY DEVICE HAVING A SILICON OXIDE NITRIDE OXIDE SILICON STRUCTURE AND METHOD FOR MANUFACTURING THE SAME}

1A and 1B are cross-sectional views illustrating a method of manufacturing a general Sonos device.

Figure 2 (a) is a perspective view showing a sonos element according to an embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along the line II ′ of FIG. 2A.

FIG. 2C is a cross-sectional view taken along the line II-II ′ of FIG. 2A.

3A to 3F are perspective views illustrating a method of manufacturing a sonoth device according to an embodiment of the present invention shown in FIGS. 2A to 2C.

4A-4C are cross-sectional views taken along the line II ′ shown in FIGS. 3C, 3E, and 3F, respectively.

<Explanation of symbols for main parts of the drawings>

20: substrate

21: device isolation film

23: recess

24: lower dielectric film

25: charge storage layer

25A, 25B: first and second charge storage layers

20A: Saddle Pin

28: upper dielectric film

29: gate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a nonvolatile memory device and a method for manufacturing the same, and more particularly, to a nonvolatile memory device having a silicon oxide-nitride oxide (SONOS) structure and a method for manufacturing the same. It is about.

Currently, attention has been focused on a nonvolatile memory device (hereinafter referred to as a sonos device) having a structure of a silicon oxide-nitride oxide (SONOS) structure as a nonvolatile memory device. Unlike conventional stack gate type nonvolatile memory devices which introduce a floating gate, the sonos device introduces a nitride film as a charge trapping layer in place of the floating gate. It constitutes a cell.

Hereinafter, a method of manufacturing a general Sonos device will be described with reference to FIGS. 1A and 1B.

First, as shown in FIG. 1A, an oxide film 11 as a lower dielectric film and a nitride film as a charge storage layer are formed on a substrate 10 on which various elements for forming semiconductor devices such as an isolation layer and a well are formed. 12), the oxide film 13 is sequentially deposited on the upper dielectric film, and the gate electrode 14 is formed on the laminated structure.

Subsequently, as shown in FIG. 1B, after forming a mask pattern (not shown) for forming a gate pattern, the gate electrode 14, the oxide film 13, and the nitride film are formed through an etching process using the mask pattern as an etching mask. Etch 12 in sequence. As a result, a sonosed gate pattern having a laminated structure of the oxide film 11, the nitride film 12, the oxide film 13, and the gate electrode 14 is formed. Thereafter, the mask pattern is removed, followed by a cleaning and reoxidation process.

However, according to the related art, when manufacturing the sonos device in the form of a general stack gate, there is a limit in reducing the area of the sonos device. In particular, in recent years, as the design rule of devices decreases, there is a need to reduce the formation area of the sonos device itself. There is a limit to the integration.

Accordingly, an object of the present invention is to provide a non-volatile memory device having a sonos structure and a method of manufacturing the same, which have been proposed to solve the above problems of the related art.

According to an aspect of the present invention, there is provided a substrate including a recess, a lower dielectric layer formed along the substrate surface step of an exposed active region including the recess, and a recess in the recess. First and second charge storage layers respectively formed on inner wall portions of the recesses so as to be electrically separated from each other, an upper dielectric layer formed along a surface step inside the recesses in which the first and second charge storage layers are formed; And a non-volatile memory device having a sono structure having a gate electrode formed on the upper dielectric layer to fill the recess.

According to another aspect of the present invention, there is provided a method including providing a substrate on which a recess is formed, and forming a lower dielectric layer along a top surface step of the substrate in an active region including the recess; Forming first and second charge storage layers spaced apart from each other so as to be electrically separated from each other in the recess in which the lower dielectric layer is formed, and the first and second charge storage layers being separated from each other. A method of manufacturing a non-volatile memory device having a sono structure comprising: forming an upper dielectric layer along a stepped upper surface of the front surface of the substrate; and forming a gate electrode on the upper dielectric layer to fill the recess. to provide.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

2 is a diagram illustrating a sonos device according to an exemplary embodiment of the present invention. Specifically, (a) of FIG. 2 is a perspective view of the Sonos device according to an embodiment of the present invention, Figure 2 (b) is a cross-sectional view taken along the line II 'shown in (a) of FIG. FIG. 2C is a cross-sectional view taken along the line II-II ′ of FIG. 2A. Here, for example, a sonos device having a saddle-like structure will be described. In this case, the saddle structure refers to a structure in which the fin and the recess structure formed on the upper portion are mixed.

Referring to FIGS. 2A to 2C, a sonos device according to an exemplary embodiment of the present invention may include a substrate 20 having a saddle-like structure and a recess 23 formed on a saddle-shaped fin (not shown). 3A) and the inner wall of the recess 23 so as to be electrically separated from each other in the recess 23 and the lower dielectric film 24 formed along the surface step of the substrate 20 of the exposed active region. The first and second charge storage layers 25A and 25B formed in the portions, the upper dielectric film 28 formed along the surface steps of the first and second charge storage layers 25A and 25B, and the recess 23, respectively. ) Is provided with a gate electrode 29 formed on the upper dielectric film 28. In this case, the first and second charge storage layers 25A and 25B are spaced apart from each other in the recess 23 so as to function as floating gates that operate independently of each other in the nonvolatile memory device. sapcer).

That is, in the sonos device according to the exemplary embodiment of the present invention, two charge storage layers 25A and 25B, which are separated from each other, formed in a spacer form in the recess 23, share one gate electrode 29 with each other. That is, since two cells have a structure in which one gate electrode 29 is shared with each other, two cells may be implemented within an area capable of implementing one cell. Therefore, the degree of integration of the sonos element can be improved.

For reference, in the conventional Sonos device, one cell in which one gate electrode is stacked on one charge storage layer is spaced apart from each other by a predetermined distance to form a memory cell array. On the other hand, in the sonos device according to the embodiment of the present invention, the heights of the first and second charge storage layers 25A and 25B are formed on the inner wall of the recess 23 by adjusting the depth of the recess 23. Since it can be easily adjusted, there is an advantage that can change the amount of charge as appropriate.

Further, the first and second charge storage layers 25A and 25B are formed of a nitride film, and the upper dielectric film 28 is formed of an oxide film or an insulating film having a dielectric constant higher than that of SiO ₂ (for example, 3.9). In addition, the lower dielectric film 24 is preferably made of an oxide film.

On the other hand, the operation of the sonos device according to the embodiment of the present invention is performed as follows. Herein, an operation of the sonos element applied to a NOR type flash memory element will be described as an example. Preferably, the sonos element according to the embodiment of the present invention suitably operates in the same manner as the NOR flash memory element.

The Sonos device according to the embodiment of the present invention performs a program operation by a hot carrier electron injection method in the same manner as a NOR flash memory device, and erases the same by a FN tunneling method. (erase) action is taken. For example, in a program operation for programming the first charge storage layer 25A, a voltage of about 9V is applied to the gate electrode 29 and a voltage of about 5V is applied to a junction region adjacent to the first charge storage layer 25A. In addition, a ground (0V) is applied to a junction region (not shown, impurity ion implantation region) adjacent to the second charge storage layer 25B. Then, electrons are generated in the channel region, and the generated electrons are attracted to the high voltage applied to the gate electrode 29 and injected into the first charge storage layer 25A, thereby performing a program operation of the first charge storage layer 25A. . In the program operation for programming the second charge storage layer 25B, a voltage of about 9V is applied to the gate electrode 29 and a voltage of about 5V is applied to the junction region adjacent to the second charge storage layer 25B. 0V is applied to the junction region adjacent to the first charge storage layer 25A. Then, an electric charge occurs in the channel region, and the generated electrons are attracted to the high voltage applied to the gate electrode 29 and injected into the second charge storage layer 25B, thereby causing a program operation to be performed in the second charge storage layer 25B. Is done.

In addition, during an erase operation, when a voltage of about -7.5V is applied to the gate electrode 29 and a voltage of about 9V is applied to the substrate 20, the substrate is simultaneously removed from the first and second charge storage layers 25A and 25B. At 20, electrons are emitted by FN tunneling.

Hereinafter, a method of manufacturing a sonoth device according to an embodiment of the present invention shown in FIG. 2 will be described in detail with reference to FIGS. 3A to 3F and FIGS. 4A to 4C.

3A to 3F are perspective views illustrating a method of manufacturing a sonos device according to an exemplary embodiment of the present invention, and FIGS. 4A to 4C are taken along the line II ′ of FIG. 3C, 3E, and 3F, respectively. It is sectional drawing.

First, as shown in FIG. 3A, the device isolation layer 21 is formed in the substrate 20 and a well process is performed. As a result, the active region and the isolation region are defined in the substrate 20. For example, the device isolation layer 21 is formed by performing a shallow trench isolation (STI) process. At this time, the STI process is performed in the following manner. First, a pad oxide film and a pad nitride film (not shown) are sequentially stacked on the substrate 20 (the oxidation process and the deposition process are performed), and then an etching process using an STI mask is performed to trench the substrate 20. To form. Thereafter, an HDP (High Density Plasma) oxide film is deposited as a single layer to fill the trench, and then a chemical mechanical polishing (CMP) process is performed to form an isolation device 21 isolated inside the trench.

Subsequently, an etching process using a recess mask exposing a portion of the substrate 20 in the active region is performed to etch the substrate 20 in the active region to a certain depth. As a result, a recess 23 having a predetermined depth is formed in the substrate 20 of the active region. Preferably, the recess 23 is formed to a depth of 500 ~ 5000Å.

Subsequently, as shown in FIG. 3B, an oxidation process is performed to form the lower dielectric layer 24 on the exposed substrate 20 in the active region including the recess 23 (see FIG. 3A). . Here, the oxidation process may be performed by a wet oxidation method in which the substrate 20 is heated at a temperature of about 900 to 1000 ° C. in an oxidizing gas such as water vapor, or about 1200 ° C. using pure oxygen as the oxidizing gas. It may be carried out by a dry oxidation method heated at a temperature, or by a radical oxidation method. Preferably, the lower dielectric film 24 is formed of an oxide film with a thickness of 10 to 100 microseconds.

Subsequently, as shown in FIGS. 3C and 4A, the charge storage layer 25 is formed on the entire surface of the substrate 20 including the lower dielectric layer 24. Preferably, the charge storage layer 25 is formed by depositing a nitride film with a thickness of 20 to 500 kPa.

Subsequently, as shown in FIG. 3D, the charge storage layer 25 is etched such that the charge storage layer 25 remains only on the inner wall of the recess 23 (see FIG. 3A). For example, the entire surface etching process is performed without a mask to etch the charge storage layer 25 exposed on the substrate 20.

3E and 4B, through the etching process using a separate mask pattern, the charge storage layers 25 and 3D that are connected together are surrounded by the inner wall of the recess 23 (see FIG. 3A). ) Is electrically isolated. For example, the charge storage layer 25 formed on the interface between the active region and the isolation region is etched. As a result, first and second charge storage layers 25A and 25B are formed in the inner wall of the recess 23 of the active region to be electrically separated from each other.

Subsequently, an etching process using a fin mask (not shown) is performed to form the saddle-shaped fin 20A. For example, the device isolation layer 21 is etched deeper than the recess 23 to form the saddle-shaped fin 20A. The etching process for forming the saddle-shaped fin 20A is preferably performed under conditions having a high selectivity between the device isolation layer 21 and the silicon substrate 20.

3F and 4C, the upper dielectric film 28 is formed along the step of the top surface of the entire structure in which the saddle-shaped fins 20A are formed. The upper dielectric film 28 is formed by depositing an oxide film or a high-k dielectric film. Here, the high dielectric constant insulating film refers to a dielectric film having a higher dielectric constant than the silicon oxide film (SiO ₂ ). For reference, the dielectric constant of SiO ₂ is 3.9.

Subsequently, a gate electrode 29 is formed on the upper dielectric film 28. In this case, the gate electrode 29 is formed to protrude above the substrate 20.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described implementation is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention. In particular, the embodiment of the present invention has been described as an example of a sonos device having a saddle structure, the present invention can be applied to all non-volatile memory devices having a sonos form.

As described above, according to the present invention, two charge storage layers, which are separated from each other and formed in a spacer form in a recess, share one gate electrode with each other, that is, two cells share one gate electrode with each other. Since it has a structure that is, it is possible to implement two cells in the area that can implement one cell. Therefore, the degree of integration of the sonos element can be improved.

In addition, according to the present invention, the height of the charge storage layer formed on the inner wall of the recess may be freely adjusted by adjusting the depth of the recess formed when the sonos element is formed. Therefore, the amount of charge stored in the charge storage layer can be appropriately changed as necessary.

Claims (12)

A substrate having a recess and a saddle pin formed under the recess; A lower dielectric layer formed along the substrate surface step of the exposed active region including the recess; First and second charge storage layers respectively formed on inner wall portions of the recesses to be electrically separated from each other in the recesses; An upper dielectric layer formed along a surface step inside the recess in which the first and second charge storage layers are formed; And A gate electrode formed on the upper dielectric layer to fill the recess Nonvolatile memory device having a sono structure having a. delete The method of claim 1, And the first and second charge storage layers have a spacer shape. The method of claim 1, The first and second charge storage layer is a non-volatile memory device having a sono structure consisting of a nitride film. The method of claim 1, And the upper dielectric layer is formed of an oxide film or a high dielectric film having a dielectric constant higher than at least SiO ₂ . The method of claim 1, The lower dielectric layer is a nonvolatile memory device having a sono structure made of an oxide film. Providing a substrate having an active region and an isolation region, wherein the substrate is recessed; Forming a lower dielectric film along the step top surface of the substrate in the active region including the recess; Forming first and second charge storage layers spaced apart from each other so as to be electrically separated from each other in the recess in which the lower dielectric layer is formed; Etching a device isolation layer formed in the device isolation region to form a saddle fin at the bottom of the recess of the active region; Forming an upper dielectric film along a step surface of an upper surface of the front surface of the substrate on which the first and second charge storage layers are formed; And Forming a gate electrode on the upper dielectric layer to fill the recess Method of manufacturing a nonvolatile memory device having a sono structure comprising a. The method of claim 7, wherein Forming the first and second charge storage layers separated from each other, Depositing a charge storage layer along an upper surface step of the front surface of the substrate including the lower dielectric layer; Etching the charge storage layer exposed over the substrate such that the charge storage layer surrounds an inner wall portion of the recess; And Etching the charge storage layer formed at an interface between the device isolation region and the active region so that the first and second charge storage layers separated from each other remain only in the inner wall portion of the recess corresponding to the active region. Method of manufacturing a nonvolatile memory device having a sono structure comprising a. delete The method according to claim 7 or 8, And the first and second charge storage layers are formed of a nitride film. The method of claim 10, And the upper dielectric film is formed of an oxide film or a high dielectric film having a dielectric constant of at least higher than SiO ₂ . The method of claim 11, And the lower dielectric layer is formed of an oxide film.

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