TWI700819B - Non-volatile memory and manufacturing method thereof - Google Patents

Abstract

A non-volatile memory having memory cells is provided. A stacked gate structure includes source region, drain region, select gate, virtual select gate, floating gate, erase gate and control gate. The select gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed on the substrate between the source region virtual select gate and the select gate, the height of the floating gate that adjacent to the select gate is higher than the height of the select gate and virtual select gate, and the floating gate has two opposite corners at the top portion. The erase gate is disposed on the source region and covers the source side corner portion. The control gate is disposed on the erase gate and the floating gate.

Description

Non-volatile memory and manufacturing method thereof

The present invention relates to a semiconductor element and its manufacturing method, and more particularly to a non-volatile memory and its manufacturing method.

Non-volatile memory has the advantages that data can be stored, read, and erased multiple times, and the stored data will not disappear after power failure, so it has been widely used in personal computers and electronic devices.

A typical non-volatile memory is designed to have a stacked gate (Stack-Gate) structure, which includes a tunnel oxide layer, a floating gate, and an inter-gate dielectric layer sequentially arranged on the substrate And control gate (Control Gate). When programming or erasing this non-volatile memory device, appropriate voltages are applied to the source region, drain region, and control gate respectively, so that electrons are injected into the polysilicon floating gate, or electrons are removed from the polysilicon floating gate. The polysilicon floating gate is pulled out.

In the operation of non-volatile memory, usually the greater the gate-coupling ratio (GCR) between the floating gate and the control gate, the lower the operating voltage required for its operation. The operating speed and efficiency of volatile memory will be greater Big improvement. The methods to increase the gate coupling ratio include increasing the overlap area between the floating gate and the control gate, reducing the thickness of the dielectric layer between the floating gate and the control gate, and increasing the floating The dielectric constant (k) of the inter-gate dielectric layer between the gate and the control gate.

In the operation of non-volatile memory, generally the smaller the gate resistance, the operating speed of non-volatile memory will be greatly improved. One method to reduce the gate resistance includes the use of metal silicide.

However, as integrated circuits are developing toward smaller devices with higher integration, the size of the memory cell of the non-volatile memory must be reduced to increase the integration. Among them, reducing the size of the memory cell can be achieved by reducing the gate length of the memory cell and the bit line interval. However, the reduced gate length will shorten the channel length (Channel Length) under the tunnel oxide layer, which is likely to cause abnormal electrical penetration between the drain and the source (Punch Through), which will seriously affect the memory cell Electrical performance. Moreover, when programming and/or erasing the memory cell, electrons repeatedly traverse the tunnel oxide layer, which will deplete the tunnel oxide layer, resulting in reduced reliability of the memory device.

The invention provides a non-volatile memory and a manufacturing method thereof, which can be operated at a low operating voltage, thereby increasing the reliability of the semiconductor element.

The invention provides a non-volatile memory and a manufacturing method thereof, which can reduce the gate resistance, thereby increasing the operating speed of a semiconductor element.

The invention provides a non-volatile memory and a manufacturing method thereof, which can improve the integration degree of components.

The present invention provides a non-volatile memory, which has a first memory cell, and the first memory cell is disposed on a substrate. The first memory cell includes source region and drain region, select gate, virtual select gate, floating gate, erase gate, control gate, tunnel dielectric layer, erase gate dielectric layer, select Gate dielectric layer, insulating layer and inter-gate dielectric layer. The source region and the drain region are respectively arranged in the substrate. The selection gate is arranged on the substrate between the source region and the drain region. The dummy selection gate is arranged on the substrate of the source region. The floating gate is arranged on the substrate between the selection gate and the source region, the height of the floating gate is higher than the height of the selection gate and the dummy selection gate, and the top of the floating gate has two symmetrical corners . The erasing gate is arranged on the virtual selection gate, and the erasing gate covers one of the corners of the floating gate. The control gate is arranged on the erase gate and the floating gate. The tunneling dielectric layer is arranged between the floating gate and the substrate. The erase gate dielectric layer is arranged between the erase gate and the floating gate. The select gate dielectric layer is disposed between the select gate and the substrate. The insulating layer is arranged between the selection gate and the floating gate. The inter-gate dielectric layer is arranged between the control gate and the floating gate and between the control gate and the erasing gate.

In an embodiment of the present invention, the erase gate replaces all of the virtual selection gates above the source region, and the erase gate covers the corners.

In an embodiment of the present invention, the aforementioned non-volatile memory further includes a second memory cell. The second memory cell is arranged on the substrate. The structure of the second memory cell is the same as the structure of the first memory cell, and the second memory cell and the first memory cell are arranged in a mirror image. Use source region or drain region.

In an embodiment of the present invention, the first memory cell and the second memory cell share an erase gate, and the erase gate fills the opening between the first memory cell and the second memory cell.

In an embodiment of the present invention, the first memory cell and the second memory cell share a control gate, and the control gate covers the erase gate.

In an embodiment of the present invention, the material of the control gate includes polysilicon and metal silicide.

In an embodiment of the present invention, the material of the selection gate includes polysilicon and metal silicide.

In an embodiment of the present invention, the erasing gate further includes a cap layer.

In an embodiment of the present invention, the floating gate has a notch.

In an embodiment of the present invention, the angle of the corner portion is less than or equal to 90 degrees.

In an embodiment of the present invention, the thickness of the selective gate dielectric layer is less than or equal to the thickness of the tunneling dielectric layer.

The present invention provides a method for manufacturing a non-volatile memory. First, a substrate is provided, in which an active region has been formed. A first stacked structure and a second stacked structure are formed on the substrate. The first stacked structure and the second stacked structure include a select gate dielectric layer, a select gate, and a sacrificial layer in order from the substrate. The second stacked structure is located at the source District. A tunneling dielectric layer is formed on the substrate between the first stack structure and the second stack structure. Self-pairing is formed on the substrate between the first stack structure and the second stack structure Quasi-floating gate, wherein the top of the floating gate has two symmetrical corners adjacent to the first stacked structure and the second stacked structure. The sacrificial layer is removed to expose the corners of the floating gate. An erase gate dielectric layer is formed on the floating gate including the corner portion. An erase gate is formed on the second stack structure; or after removing the select gate of the second stack structure (ie, the dummy select gate), an erase gate is formed on the substrate. The erasing gate covers the corner part of the floating gate close to the source region side. An inter-gate dielectric layer is formed on the floating gate and the erased gate. A control gate is formed on the floating gate.

In an embodiment of the present invention, the step of forming a floating gate on the substrate between the first stack structure and the second stack structure includes: forming a conductor spacer between the first stack structure and the second stack structure, Then the conductor spacer is patterned to form a floating gate.

In an embodiment of the present invention, the manufacturing method of the non-volatile memory further includes: forming a drain region in the substrate on the opposite side of the first stack structure adjacent to the floating gate.

In an embodiment of the present invention, the manufacturing method of the non-volatile memory further includes: forming a metal silicide layer on the selective gate, control gate and drain regions.

In an embodiment of the present invention, after removing the second stack structure, it further includes forming an erase gate dielectric layer and a spacer on the sidewall of the floating gate.

In an embodiment of the present invention, the step of forming a control gate on the floating gate includes: forming a conductive material layer on a substrate, and then patterning the conductive material layer to form a layer covering the floating gate and the erase gate Control the gate.

In an embodiment of the present invention, the step of forming a control gate on a floating gate includes: forming a conductive material layer on the substrate, and performing a planarization process to remove part of the conductive material layer, and then patterning The conductive material layer is formed to form a control gate on the side where the gate is erased and above the floating gate.

In an embodiment of the present invention, a cap layer is further formed on the erase gate, and the planarization process is to remove part of the conductive material layer until the cap layer is exposed.

In the non-volatile memory and the manufacturing method thereof of the present invention, the floating gate has a notch, which increases the area between the control gate and the floating gate, and improves the coupling rate of the memory device.

In the non-volatile memory and the manufacturing method thereof of the present invention, since the floating gate is provided with a corner portion, the erasing gate covers the corner portion. The angle of the corner part is less than or equal to 90 degrees. By concentrating the electric field at the corner part, the erasing voltage can be reduced, and the electrons can be efficiently pulled out of the floating gate to increase the data erasing speed.

In the non-volatile memory and the manufacturing method thereof of the present invention, since the thickness of the selective gate dielectric layer under the formed selective gate can be made thinner according to usage requirements, a smaller voltage can be used when operating the memory cell Opening/closing the channel area under the auxiliary gate, which can reduce the operating voltage.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

100, 200: base

101: Isolation structure

103: active area

102, 202: source region

104, 232: Drain region

106: select gate

106a: Virtual selection gate

108, 216: floating gate

110, 110a, 224a: erase gate

112, 112a, 112b, 230a, 230b: control gate

114, 212: Tunneling dielectric layer

116, 116a: Erase the gate dielectric layer

118: Select gate dielectric layer

120: insulating layer

122, 228: Dielectric layer between gates

124, 236: Metal silicide layer

126, 218: corner

128, 234, 238: gap wall

130, 226: top cover layer

140, 142, 144, 146, MC: memory cell

204, 220, 222: Dielectric layer

206, 214, 224, 230: conductor layer

207: Sacrifice Layer

208a, 208b: stacked structure

210: insulating layer

FIG. 1A is a top view of a non-volatile memory according to an embodiment of the invention.

FIG. 1B is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention.

FIG. 1C is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention.

FIG. 1D is a top view of a non-volatile memory according to an embodiment of the invention.

FIG. 1E is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention.

FIG. 1F is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention.

2A to 2H are schematic cross-sectional views illustrating a manufacturing process of a non-volatile memory according to an embodiment of the invention.

3 is a schematic cross-sectional view of a manufacturing process of a non-volatile memory according to an embodiment of the present invention.

4A to 4C are cross-sectional schematic diagrams of a manufacturing process of a non-volatile memory after removing the second stack structure (ie, the virtual selection gate) according to an embodiment of the present invention.

Fig. 1A is a non-volatile diagram according to an embodiment of the present invention Top view of the memory. FIG. 1B is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention. Fig. 1B is a cross-sectional view taken along the line AA' in Fig. 1A. FIG. 1C is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention. FIG. 1D is a top view of a non-volatile memory according to an embodiment of the invention. FIG. 1E is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention. Fig. 1E is a cross-sectional view taken along the line BB' in Fig. 1D. FIG. 1F is a schematic cross-sectional view of a non-volatile memory according to an embodiment of the invention. In FIGS. 1B to 1F, the same components are given the same symbols and their descriptions are omitted.

1A and 1B, the non-volatile memory includes a plurality of memory cells MC. These memory cells MC are arranged in a row/column array. The non-volatile memory is disposed on the substrate 100. For example, a plurality of isolation structures 101 arranged regularly are arranged in the substrate 100 to define an active area 103 having a lattice shape. The isolation structure 101 is, for example, a shallow trench isolation structure.

Each memory cell MC includes a source region 102 and a drain region 104, a selection gate 106, a floating gate 108, an erase gate 110, a control gate 112, a tunneling dielectric layer 114, and an erase gate dielectric layer 116. Select the gate dielectric layer 118, the insulating layer 120, and the inter-gate dielectric layer 122.

The source region 102 and the drain region 104 are respectively disposed in the substrate 100. The source region 102 and the drain region 104 are, for example, doped regions containing N-type or P-type dopants, depending on the design of the device.

The selection gate 106 is disposed on the substrate 100 between the source region 102 and the drain region 104, for example. The selection gate 106 extends in the Y direction, for example. The material of the selected gate 106 includes conductive materials such as doped polysilicon. In one embodiment, the material of the selection gate 106 includes polysilicon and metal silicide.

The floating gate 108 is, for example, disposed on the substrate 100 between the select gate 106 and the source region 102. The height of the floating gate 108 adjacent to the selection gate 106 is higher than the height of the selection gate 106, and the top of the floating gate 108 has at least a corner portion 126. The floating gate 108 has a recess, that is, the height of the floating gate gradually increases from the center, and the corner portion 126 at the top is exposed. The material of the floating gate 108 is, for example, a conductive material such as doped polysilicon. The floating gate 108 may be composed of one or more conductor layers.

The erasing gate 110 is, for example, disposed on the source region 102, and the erasing gate 110 covers the corner portion 126. The erasing gate 110 extends in the Y direction, for example. The material of the erase gate 110 is, for example, a conductive material such as doped polysilicon. The control gate 112 is, for example, disposed on the erase gate 110 and the floating gate 108. The material of the control gate 112 is, for example, a conductive material such as doped polysilicon. The erasing gate 110 further includes a cap layer 130. The material of the cap layer 130 is, for example, silicon oxide or silicon nitride.

The tunneling dielectric layer 114 is, for example, disposed between the floating gate 108 and the substrate 100. The material of the tunneling dielectric layer 114 is silicon oxide, for example. The thickness of the tunneling dielectric layer 114 is between 60 angstroms and 200 angstroms. The erasing gate dielectric layer 116 is disposed between the erasing gate 110 and the floating gate 108, for example. The material of the wiper dielectric layer 116 is for example It is silicon oxide. The thickness of the erase gate dielectric layer 116 is, for example, between 60 angstroms and 180 angstroms.

The select gate dielectric layer 118 is, for example, disposed between the select gate 106 and the substrate 100. The material of the selective gate dielectric layer 118 is, for example, silicon oxide, and the thickness of the selective gate dielectric layer is less than or equal to the thickness of the tunneling dielectric layer. The insulating layer 120 is, for example, disposed between the selection gate 106 and the floating gate 108. The inter-gate dielectric layer 122 is, for example, disposed between the control gate 112 and the floating gate 108 and between the control gate 112 and the erase gate 110. The material of the inter-gate dielectric layer 122 is, for example, silicon oxide/silicon nitride/silicon oxide or silicon nitride/silicon oxide or other high dielectric constant materials (k>4).

In this embodiment, the non-volatile memory further includes a virtual select gate 106a. The dummy selection gate 106a is disposed between the substrate 100 and the erase gate 110, for example. An insulating layer 120 is also provided between the dummy selection gate 106a and the floating gate 108, for example.

In the X direction (row direction), a plurality of memory cells MC are connected in series via the source region 102 or the drain region 104. For example, the structure of the memory cell 140 is the same as that of the memory cell 142, and the memory cell 140 and the memory cell 142 are arranged in a mirror image and share the source region 102 or the drain region 104; the structure of the memory cell 144 is the same as that of the memory cell 146 The structure is the same, and the memory cell 144 and the memory cell 146 are in a mirror image configuration, sharing the source region 102 or the drain region 104. At the same time, the memory cell 140, the memory cell 142, the memory cell 144, and the memory cell 146 share the erasing gate 110 and the control gate 112, and the control gate 112 covers the erasing gate 110.

In the Y direction (column direction), a plurality of memory cells MC are connected in series by the source region 102, the selection gate 106, the erase gate 110, and the control gate 112. That is, in the column direction, a plurality of memory cells MC share the same source region 102, select gate 106, erase gate 110, and control gate 112. For example, the structure of the memory cell 140 is the same as the structure of the memory cell 144, the structure of the memory cell 142 is the same as the structure of the memory cell 146, and the control gate 112 fills the memory cell 140 and the memory cell 144 and the structure of the memory cell 142 and Between memory cells 146. The memory cell 140 and the memory cell 144 in the same row share the same source region 102, selection gate 106, erase gate 110, and control gate 112.

In this embodiment, a metal silicide layer 124 is further formed on the control gate 112, the select gate 106, and the drain region 104.

In another embodiment, as shown in FIG. 1C, the dummy selection gate 106a shown in FIGS. 1A and 1B is removed. The erase gate 110a fills the opening between the memory cell 140 and the memory cell 142. An insulating layer formed by the erase gate dielectric layer 116a and the spacer 128 is provided between the erase gate 110a and the floating gate 108.

In another embodiment, as shown in FIG. 1D and FIG. 1E, the memory cell 140 and the memory cell 142 share the erasing gate 110. However, the memory cell 140 and the memory cell 142 respectively have a control gate 112a and a control gate 112b, that is, in the X direction, adjacent memory cells MC do not share a control gate. The erasing gate 110 further includes a cap layer 130. The material of the cap layer 130 is, for example, silicon oxide or silicon nitride.

In another embodiment, as shown in FIG. 1F, the memory cell 140 and the memory cell 142 shares erase gate 110. However, the memory cell 140 and the memory cell 142 respectively have a control gate 112a and a control gate 112b, that is, in the X direction, adjacent memory cells MC do not share a control gate. The erasing gate 110 further includes a cap layer 130. The material of the cap layer 130 is, for example, silicon oxide or silicon nitride. Moreover, the dummy selection gate 106a shown in FIGS. 1A and 1B is removed. The erase gate 110a fills the opening between the memory cell 140 and the memory cell 142. An insulating layer formed by the erase gate dielectric layer 116a and the spacer 128 is provided between the erase gate 110a and the floating gate 108.

In the above-mentioned non-volatile memory, the thickness of the select gate dielectric layer 118 is relatively thin. When the memory cell is operated, a smaller voltage can be used to open/close the channel area under the select gate 106, that is, the operation can be reduced. Voltage. The floating gate 108 has a notch, which increases the area sandwiched between the control gate 112 and the floating gate 108 and improves the coupling rate of the memory device. Because the floating gate 108 has a corner portion 126. The erasing gate 110 (110a) covers the corner portion 126, and the angle of the corner portion 126 is less than or equal to 90 degrees. The corner portion 126 concentrates the electric field, which can reduce the erasing voltage and effectively remove electrons from the floating gate. The pole 108 is pulled out to increase the speed of erasing data.

2A to 2H are schematic cross-sectional views illustrating a manufacturing process of a non-volatile memory according to an embodiment of the invention.

Referring to FIG. 2A, a substrate 200 is provided first. The active region 202 has been formed in the substrate 200. The method for forming the source region 202 is, for example, an ion implantation process. The implanted dopants can be N-type or P-type dopants, depending on the design of the device.

Then, a dielectric layer 204, a conductive layer 206, and a sacrificial layer 207 are sequentially formed on the substrate 200. The material of the dielectric layer 204 is, for example, silicon oxide, and the forming method thereof is, for example, a thermal oxidation method. The material of the conductive layer 206 is, for example, doped polysilicon or polysilicon metal. When the material of the conductor layer 206 is doped polysilicon, the formation method is, for example, a chemical vapor deposition method is used to form an undoped polysilicon layer, followed by an ion implantation step to form it; or in-situ can also be used. The method of implanting dopants is formed by chemical vapor deposition. The material of the sacrificial layer 207 includes a material having a different etching selectivity from the material of the dielectric layer 204, such as silicon nitride, and its formation method is, for example, a chemical vapor deposition method.

Next, the sacrificial layer 207, the conductive layer 206, and the dielectric layer 204 are patterned to form at least the stacked structure 208a and the stacked structure 208b. The stack structure 208b is located on the source region 202. The method for forming the stacked structure 208a and the stacked structure 208b is, for example, to form a patterned photoresist layer (not shown) on the substrate 200 first, and the method for forming the patterned photoresist layer is, for example, to form a layer of photoresist on the entire substrate 200. The material layer is then exposed and developed to form it. Then, using the patterned photoresist layer as a mask, the sacrificial layer 207, the conductive layer 206, and the dielectric layer 204 are removed to form at least the stacked structure 208a and the stacked structure 208b. Then, the patterned photoresist layer is removed. The method of removing the patterned photoresist layer is, for example, a wet photoresist method or a dry photoresist method. Among them, the dielectric layer 204 serves as a selective gate dielectric layer. The conductor layer 206 serves as a selective gate.

2B, an insulating layer 210 is formed on the sidewalls of the stacked structure 208a and the stacked structure 208b. The material of the insulating layer 210 is, for example, silicon oxide/silicon nitride /Silicon oxide or silicon nitride/Silicon oxide or silicon oxide. The insulating layer 210 is formed by, for example, first forming a dielectric layer covering each of the stacked structures 208a and 208b in sequence on the substrate 200, and then removing part of the dielectric layer to form insulation on the sidewalls of the stacked structures 208a and 208b.层210. The method for forming the dielectric layer is, for example, a chemical vapor deposition method. The method of removing part of the dielectric layer is, for example, an anisotropic etching method.

Next, a tunneling dielectric layer 212 is formed on the substrate 200 between the stacked structure 208a and the stacked structure 208b. The material of the tunneling dielectric layer 212 is, for example, silicon oxide, and the formation method thereof is, for example, a thermal oxidation method.

Then, a conductive layer 214 is formed on the substrate 200. The material of the conductive layer 214 is, for example, doped polysilicon. When the material of the conductor layer is doped polysilicon, its formation method is, for example, using chemical vapor deposition to form an undoped polysilicon layer and then performing an ion implantation step to form it; or in-situ implantation can also be used. The method of doping is formed by chemical vapor deposition. Then, remove part of the conductor layer. The method of removing part of the conductor layer is, for example, an anisotropic etching method or an etch-back method.

2C, a part of the conductive layer 214 is removed, and a conductive spacer is formed between the stacked structure 208a and the stacked structure 208b. The method of removing part of the conductor layer is, for example, an anisotropic etching method or an etch-back method. The height of the portion of the conductor spacer adjacent to the stack structure 208a (stack structure 208b) is higher than the height of the conductor layer 206 in the stack structure 208a (stack structure 208b).

Next, the conductor spacer is patterned to form a floating gate 216. The method of patterning the conductor spacer is as follows. A patterned photoresist layer is formed on the substrate 200 (Not shown). The method for forming the patterned photoresist layer is, for example, forming a layer of photoresist material on the entire substrate 200, and then performing exposure and development to form it. Taking the patterned photoresist layer as a mask, a part of the conductor spacer is removed to make it into a block shape, leaving the conductor spacer between the stacked structure 208a and the stacked structure 208b. The bulk conductor spacer between the stack structure 208a and the stack structure 208b serves as the floating gate 216. The floating gate 216 has a notch and has a corner portion 218 adjacent to the top of the stack structure 208a and the stack structure 208b.

Then, a part of the insulating layer 210 is removed to expose at least the corner portion 218 of the floating gate 216. The method of removing part of the insulating layer 210 is, for example, a wet etching method or a dry etching method.

2D, a dielectric layer 220 is formed on the floating gate 216. The material of the dielectric layer 220 is silicon oxide, for example. The method of forming the dielectric layer 220 is, for example, a thermal oxidation method. Then, the sacrificial layer 207 is removed, so that the corner portion 218 of the floating gate 216 protrudes from the top surface of the conductive layer 206. The method of removing the sacrificial layer 207 is, for example, a wet etching method or a dry etching method.

2E, after the dielectric layer 220 is removed, a dielectric layer 222 is formed on the substrate 200. The method of removing the dielectric layer 220 is, for example, a wet etching method or a dry etching method. The material of the dielectric layer 222 is silicon oxide, for example. Then, a conductive layer 224 and a cap layer 226 are sequentially formed on the substrate 200. The material of the conductive layer 224 is, for example, doped polysilicon or polysilicon metal. When the material of the conductor layer 224 is doped polysilicon, its formation method is, for example, using chemical vapor deposition to form a layer of undoped polysilicon. After the silicon layer, an ion implantation step is performed to form it; or an in-situ method of implanting dopants can also be used to form it by chemical vapor deposition. The material of the cap layer 226 includes a material having a different etching selectivity from the material of the dielectric layer 222, such as silicon nitride, and the formation method thereof is, for example, a chemical vapor deposition method.

Referring to FIG. 2F, the cap layer 226 and the conductive layer 224 are patterned to form the cap layer 226 and the erase gate 224a. The erase gate 224a is located on the source region 202. The method of patterning the cap layer 226 and the conductor layer 224 is, for example, to form a patterned photoresist layer (not shown) on the substrate 200 first, and the method for forming the patterned photoresist layer is, for example, to form a layer on the entire substrate 200. The photoresist material layer is then exposed and developed to form it. Then, using the patterned photoresist layer as a mask, the cap layer 226 and the conductor layer 224 are removed to form at least the cap layer 226 and the erase gate 224a. Then, the patterned photoresist layer is removed. The method of removing the patterned photoresist layer is, for example, a wet photoresist method or a dry photoresist method. In this step, the dielectric layer 222 that is not covered by the erase gate 224a can also be removed. The dielectric layer 222 between the erase gate 224a and the floating gate 216 serves as the erase gate dielectric layer.

Then, an inter-gate dielectric layer 228 is formed on the substrate 200. The inter-gate dielectric layer 228 at least covers the floating gate 216 and erases the gate 224a. The material of the inter-gate dielectric layer 228 includes silicon oxide/silicon nitride/silicon oxide. The method for forming the inter-gate dielectric layer 228 is, for example, using a chemical vapor deposition method to sequentially form a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer. The material of the inter-gate dielectric layer 228 can also be silicon nitride/silicon oxide or other high dielectric constant materials (k>4).

A conductive layer 230 is formed on the substrate 200. The material of the conductive layer 230 is, for example, doped polysilicon or polysilicon metal. When the material of the conductor layer 230 is doped polysilicon, the formation method is, for example, a chemical vapor deposition method is used to form an undoped polysilicon layer and then an ion implantation step is performed to form it; or in-situ can also be used. The method of implanting dopants is formed by chemical vapor deposition.

2G, a planarization process is performed on the conductive layer 230, for example, chemical mechanical polishing is performed to remove a part of the conductive layer 230 until the inter-gate dielectric layer 228 or the cap layer 226 is exposed. Then the conductive layer 230 is patterned to form the control gate 230a. That is, the control gate 230a is formed on the side of the erase gate 224a and above the floating gate 216.

Next, a drain region 232 is formed in the substrate 200 on the side of the selection gate (conductor layer 206) opposite to the floating gate 216. The formation method of the drain region 232 is, for example, an ion implantation process. The implanted dopants can be N-type or P-type dopants, depending on the design of the device. The dopants and dopant concentrations of the source region 202 and the drain region 232 may be the same or different.

Then, a spacer 234 is formed on the sidewalls of the control gate 230a and the selection gate (conductor layer 206). The material of the spacer 234 is silicon nitride, for example. The formation method of the spacer 234 is, for example, forming an insulating layer on the substrate 200, and removing part of the insulating layer by an anisotropic etching method or an etch back method. When the spacer 234 is formed, the inter-gate dielectric layer 228 that is not covered by the spacer 234 is also removed, and a part of the selective gate (conductor layer 206) and the drain region 232 are exposed. Next, proceed to self-align the metal silicon In a Salicide process, a metal silicide layer 236 is formed on the control gate 230a, the selection gate (conductor layer 206), and the drain region 232.

In another embodiment, FIG. 3 is continued after FIG. 2F, and the conductive layer 230 is directly patterned to form a control gate 230b covering the erase gate 224a. Then, the drain region 232, the spacer 234, and the metal silicide layer 236 are formed to produce the non-volatile memory as shown in FIG. 1B.

In another embodiment, in order to fabricate the non-volatile memory shown in FIG. 1C and FIG. 1F, following FIG. 2D, the manufacturing process of FIGS. 4A to 4C is performed.

4A, the conductor layer 206 of the stack structure 208b is removed, and the dielectric layer 220 and the dielectric layer 204 of the stack structure 208b are removed. A notch is formed between adjacent floating gates. The method of removing the conductor layer 206 of the stack structure 208b is as follows. A patterned photoresist layer (not shown) is formed on the substrate 200, and the patterned photoresist layer at least exposes the stacked structure 208b. The method for forming the patterned photoresist layer is, for example, forming a layer of photoresist material on the entire substrate 200, and then performing exposure and development to form it. Using the patterned photoresist layer as a mask, the conductor layer 206 of the stacked structure 208b is removed. After that, the patterned photoresist layer is removed. The method of removing the dielectric layer 220 and the dielectric layer 204 of the stacked structure 208b is, for example, a wet etching method.

Referring to FIG. 4B, a dielectric layer 222 is formed on the substrate 200. The material of the dielectric layer 222 is silicon oxide, for example. Then, a spacer 238 is formed on the side wall of the floating gate 216. The material of the spacer 238 is silicon oxide, for example. The method of forming the spacer 238 is, for example, forming an insulating layer on the substrate 200, using an anisotropic etching method Or etch back method to remove part of the insulating layer.

Referring to FIG. 4C, a conductive layer 224 and a cap layer 226 are sequentially formed on the substrate 200. The conductor layer 224 fills the notch. The material of the conductive layer 224 is, for example, doped polysilicon or polysilicon metal. When the material of the conductor layer 224 is doped polysilicon, the formation method thereof is, for example, a chemical vapor deposition method is used to form an undoped polysilicon layer, followed by an ion implantation step to form it; or in-situ can also be used. The method of implanting dopants is formed by chemical vapor deposition. The material of the cap layer 226 includes a material having a different etching selectivity from the material of the dielectric layer 222, such as silicon nitride, and the formation method thereof is, for example, a chemical vapor deposition method.

The subsequent manufacturing process can follow the above description of FIG. 2F to FIG. 2G, after forming the erasing gate filled with the notch, the inter-gate dielectric layer 228, the control gate 230a, the drain region 232, and the spacer are sequentially formed. 234 and the metal silicide layer 236 to produce the non-volatile memory shown in FIG. 1F.

In another embodiment, the subsequent process may follow the above description of FIG. 2F and FIG. 3 to sequentially form the inter-gate dielectric layer 228, the control gate 230b, the drain region 232, the spacer 234, and the metal silicide layer. 236 to manufacture the non-volatile memory shown in FIG. 1C.

In the above-mentioned non-volatile memory manufacturing method, the formed control gate covers the side and upper surface of the floating gate, which can increase the area between the control gate and the floating gate, thereby improving the memory The coupling rate of the body component. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any related technical field Those with ordinary knowledge in the domain can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent scope.

100: base

102: source region

104: Drain region

106: select gate

108: floating gate

110: Erase the gate

112: control gate

114: Tunneling Dielectric Layer

116: Erase the gate dielectric layer

118: Select gate dielectric layer

120: insulating layer

122: Dielectric layer between gates

124: metal silicide layer

126: Corner

128: Clearance Wall

130: top cover

140, 142: memory cell

Claims (20)

A non-volatile memory includes: a first memory cell, which is arranged on a substrate, and the first memory cell includes: a source region and a drain region, which are respectively arranged in the substrate; and a gate is selected and arranged on the substrate. On the substrate between the source region and the drain region; A virtual selection gate is arranged on the substrate of the source region; A floating gate is arranged on the selection gate and the substrate On the substrate between the virtual selection gates, the height of the floating gate is higher than the heights of the selection gate and the virtual selection gate, and the top of the floating gate has two symmetry The corner portion of the wiper; the wiper gate is arranged on the virtual selection gate, and the wiper gate covers one of the corners of the floating gate; the control gate is arranged on the wiper In addition to the gate and the floating gate; the tunneling dielectric layer is disposed between the floating gate and the substrate; the erasing gate dielectric layer is disposed on the erasing gate and the substrate Between the floating gates; The selective gate dielectric layer is arranged between the selective gate and the substrate; The insulating layer is arranged between the selective gate and the floating gate; and Between the gates The dielectric layer is arranged between the control gate and the floating gate and between the control gate and the erasing gate. The non-volatile memory as described in claim 1, wherein the erase gate replaces all of the virtual select gate above the source region, and the erase gate covers all述角部。 Said corner. The non-volatile memory described in item 1 of the scope of patent application further includes: a second memory cell disposed on the substrate, the structure of the second memory cell is the same as that of the first memory cell, And the second memory cell and the first memory cell are in a mirror configuration, sharing the source region or the drain region. The non-volatile memory according to claim 2, wherein the first memory cell and the second memory cell share the erase gate, and the erase gate fills the first memory cell An opening between a memory cell and the second memory cell. The non-volatile memory according to claim 3, wherein the first memory cell and the second memory cell share the control gate, and the control gate covers the erase gate . In the non-volatile memory described in the first item of the patent application, the material of the control gate includes polysilicon and metal silicide. In the non-volatile memory described in the first item of the scope of patent application, the material of the select gate includes polysilicon and metal silicide. The non-volatile memory according to the first item of the scope of patent application, wherein the erase gate further includes a cap layer. The non-volatile memory according to the first item of the scope of patent application, wherein the floating gate has a notch. The non-volatile memory according to the first item of the scope of patent application, wherein the angle of the corner portion is less than or equal to 90 degrees. The non-volatile memory as described in claim 1, wherein the thickness of the selective gate dielectric layer is less than or equal to the thickness of the tunneling dielectric layer. A method of manufacturing a non-volatile memory includes: providing a substrate in which a source region has been formed; forming a first stack structure and a second stack structure on the substrate, the first stack structure and the The second stacked structure includes a select gate dielectric layer, a select gate, and a sacrificial layer in order from the substrate, wherein the second stacked structure is located on the source region; between the first stacked structure and the A tunneling dielectric layer is formed on the substrate between the second stack structure; a floating gate is formed on the substrate between the first stack structure and the second stack structure, wherein the floating gate The top of the gate has a corner part; removing the sacrificial layer to expose at least the corner part of the floating gate; at least forming an erase gate dielectric layer on the corner part of the floating gate; Forming an erasing gate on the substrate, wherein the erasing gate covers the corner portion of the floating gate close to the source region side; on the floating gate and the Forming an inter-gate dielectric layer on the wiper; and forming a control gate on the floating gate. The method for manufacturing a non-volatile memory as described in claim 12, wherein the step of forming a floating gate on the substrate between the first stack structure and the second stack structure includes: Forming a conductor spacer between the first stack structure and the second stack structure; and patterning the conductor spacer to form the floating gate. The manufacturing method of the non-volatile memory as described in claim 12, further includes: forming a drain in the substrate on the opposite side of the first stack structure adjacent to the floating gate Area. The manufacturing method of the non-volatile memory as described in item 12 of the scope of patent application further includes: forming a metal silicide layer on the select gate, the control gate and the drain region. According to the manufacturing method of non-volatile memory described in claim 12, after the step of removing the sacrificial layer, it further includes removing the second stacked structure. The method for manufacturing a non-volatile memory according to claim 16, wherein after removing the second stack structure, it further includes forming the erase gate dielectric layer on the sidewall of the floating gate With the clearance wall. The method for manufacturing a non-volatile memory according to claim 12, wherein the step of forming the control gate on the floating gate includes: forming a conductive material layer on the substrate; and patterning The conductive material layer forms the control gate covering the floating gate and the erase gate. The method for manufacturing a non-volatile memory as described in claim 12, wherein the step of forming the control gate on the floating gate includes: forming a conductive material layer on the substrate; and performing planarization A process of removing part of the conductive material layer; and patterning the conductive material layer to form the control gate on one side of the erase gate and above the floating gate. According to the manufacturing method of non-volatile memory described in claim 19, wherein a cap layer is further formed on the erase gate, and the planarization process is to remove part of the conductive material layer until exposed Out of the top cover layer.

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