KR101111917B1 - Non-volatile memory cell using state of three kinds and method of manufacturing the same - Google Patents

Abstract

The present invention discloses a nonvolatile memory having three data states and a method of manufacturing the same. The disclosed nonvolatile memory of the present invention includes a silicon substrate; A floating gate formed on the silicon substrate; A tunnel oxide layer interposed below both ends of the floating gate between the silicon substrate and the floating gate; A ferroelectric interposed between the silicon substrate inside the tunnel oxide film and the floating gate; A diffusion barrier film surrounding the ferroelectric material; A control gate formed on the substrate including the floating gate; A gate insulating film formed under the control gate; A spacer formed on both sidewalls of the floating gate and the control gate including the tunnel oxide layer and the gate insulating layer; A P-type junction region formed in the drain predetermined region of the substrate; And source / drain regions formed in the surface of the substrate on both sides of the control gate including the spacers.

Description

Non-volatile memory having three states and manufacturing method thereof {NON-VOLATILE MEMORY CELL USING STATE OF THREE KINDS AND METHOD OF MANUFACTURING THE SAME}

1 is a cross-sectional view showing a conventional flash memory cell.

2 is a cross-sectional view illustrating a nonvolatile memory according to the present invention.

3A to 3K are cross-sectional views of processes for describing a method of manufacturing a nonvolatile memory according to the present invention.

4A to 4C are cross-sectional views for explaining the operation of the nonvolatile memory according to the present invention;

Explanation of symbols on the main parts of the drawings

200,300 silicon substrate 202,302 device isolation film

204,304: First TiN film 206,306: PZT film

208,308: 2nd TiN film 210,310: 3rd TiN film

212,312 Silicon oxide film 314 Floating gate conductive film

216,316 insulating film for control gate 218,318 conductive film for control gate

220,320: tungsten silicide film 222,322: hard mask film

224,324: Control gate 226,326: Floating gate

228,328 oxide film for spacer 230,330 P-type junction region

232,332 Nitride film for spacer 234,334 Spacer

236,336 source / drain regions

The present invention relates to a memory, and more particularly, to a nonvolatile memory having three data states and a manufacturing method thereof.

As is well known, conventional volatile memory such as DRAM and SRAM and nonvolatile memory such as flash have one cell having two state values, that is, a state of "0" or "1".

In other words, the DRAM is based on the presence or absence of charge stored in the capacitor of each cell, and the SRAM is "0" or not, depending on the two states that each cell is a latch (latch) or It has two data states of "1".

1 is a cross-sectional view of a conventional flash memory cell. As shown in the drawing, "0" or "1" indicates whether each cell has data at two threshold voltages depending on whether electrons are injected into the floating gate 3a. Has two data states.

Therefore, it can be understood that existing volatile and nonvolatile memories have the same capacity as the total number of memory cells.

In Fig. 1, reference numeral 100 denotes a silicon substrate, 102 an isolation layer, 112 a tunnel oxide film made of a silicon oxide film, 126 a floating gate made of a polysilicon film, 116 an insulating film for a control gate, 124 a control gate, 118 and 120 Are the conductive film for the control gate and the tungsten silicide film, 122 are the hard mask film, 134 are the spacer, 128 and 132 are the spacer oxide film and the nitride film, and 136 are the source / drain regions, respectively.

However, it is well known that a large amount of memory is required as the information to be processed with the development of technology increases, while the high integration of the memory reaches technically many limitations.

Accordingly, new structures and processes are strongly required to realize satisfactory high capacity memories.

Accordingly, the present invention provides a nonvolatile memory in which sufficient capacity is ensured.

In addition, the present invention provides a nonvolatile memory having improved density while ensuring sufficient capacity.

Nonvolatile memory of the present invention, the silicon substrate; A floating gate formed on the silicon substrate; A tunnel oxide layer interposed below both ends of the floating gate between the silicon substrate and the floating gate; A ferroelectric interposed between the silicon substrate inside the tunnel oxide film and the floating gate; A diffusion barrier film surrounding the ferroelectric material; A control gate formed on the substrate including the floating gate; A gate insulating film formed under the control gate; A spacer formed on both sidewalls of the floating gate and the control gate including the tunnel oxide layer and the gate insulating layer; A P-type junction region formed in the drain predetermined region of the substrate; And source / drain regions formed in the surface of the substrate on both sides of the control gate including the spacers.

Here, the ferroelectric is characterized in that formed of a PZT film.

The diffusion barrier film is formed of a TiN film or an Al ₂ O ₃ film.

The floating gate is characterized in that each of the two sides is formed so as to extend 1 ~ 50nm outward from the ferroelectric.

The P-type junction region is formed through hollow ion implantation using B or BF ₂ .

In addition, the manufacturing method of the nonvolatile memory of the present invention comprises the steps of sequentially forming a first diffusion barrier film, a ferroelectric and a second diffusion barrier film on a silicon substrate; Patterning the second diffusion barrier film, the ferroelectric, and the first diffusion barrier film to a size smaller than a desired floating gate; Forming a third diffusion barrier film on the substrate to surround sidewalls of the patterned second diffusion barrier film, the ferroelectric material, and the first diffusion barrier film; Selectively growing a silicon oxide film on the substrate surface; Forming a conductive film for a floating gate on the silicon oxide film and the third diffusion barrier film; Patterning the conductive film for silicon and the silicon oxide film in a line shape extending in one direction; Sequentially forming a control gate insulating film, a control gate conductive film, and a hard mask film on an entire surface of the substrate including the patterned floating gate conductive film; Etching the hard mask layer, the conductive layer for the control gate, and the insulating layer for the control gate to form a line-shaped control gate extending in a direction perpendicular to one direction and a gate insulating layer disposed under the control gate; Etching the floating gate conductive film and the silicon oxide film to form a floating gate including the floating gate conductive film, and forming a tunnel oxide film disposed under both ends of the floating gate; Forming an oxide film for a spacer on both of the stacked gates and the control gates; Selectively inclining ion implantation of P-type impurities into a region to be drained of the substrate resultant on which the oxide film for the spacer is formed; Forming a spacer nitride film on the spacer oxide film to form a spacer including a laminated film of an oxide film and a nitride film; And forming a source / drain region in the surface of the substrate on both sides of the control gate including the spacer.

The ferroelectric may be formed of a PZT film.

The ferroelectric is characterized in that formed to a thickness of 30 ~ 1000 ～.

The first, second and third diffusion barrier films may be formed of a TiN film or an Al ₂ O ₃ film.

The first, second and third diffusion barrier film is characterized in that formed to a thickness of 20 ~ 500 ～.

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Each of the floating gates may be formed to extend 1 to 50 nm outward from the ferroelectric.

Gradient ion implantation of the P-type impurity is performed using energy of 1 to 50 keV and dose of 1.0 × 10 ¹² to 1.0 × 10 ¹⁵ ions / cm ² using B or BF ₂ . .

Inclined ion implantation of the P-type impurity, characterized in that performed by giving an incident angle of 1 ~ 30 °.

And performing a cleaning process using an HF solution on the substrate resulting from the gradient ion implantation of the P-type impurity and prior to forming the spacer. It is characterized by.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a nonvolatile memory according to the present invention.

Referring to FIG. 2, a memory of the present invention has a basic structure of a flash memory, and in particular, a tunnel oxide film including an oxide film interposed between a silicon substrate 200 and a floating gate 226, that is, a silicon oxide film 212. Is disposed only below both ends of the floating gate 226, and inside the ferroelectric material, for example, a PZT [Pb (Zr, Ti) O ₃ ] film 206, which is applied as a dielectric material of a ferroelectric capacitor, is disposed. .

In this case, the memory according to the present invention is not a memory having only two data states through a combination of an electric field in the PZT film 206 and electrons injected as a hot carrier into the floating gate 226. This results in a memory with three data states.

In this case, the hot carrier injection into the floating gate 226 may be performed through the silicon oxide film 212 at a portion that meets the drain terminal, and the data deletion operation may be performed by electrons in the floating gate 226 at the silicon oxide film 212 of the source terminal. Tunneling is done.

This means that the movement of electrons in the writing and erasing operation is made through the normal silicon oxide film 212 instead of the PZT film 206, so that the writing and erasing operation in the memory according to the present invention can be made stable. have.

The memory of the present invention can operate as a nonvolatile memory because the electrical polarity of the ferroelectric and the electrons injected into the floating gate 226 are maintained even when the power is turned off.

Meanwhile, in the nonvolatile memory of the present invention, when the PZT film 206 is in direct contact with the silicon substrate 200, the lead (Pb) component among the components may easily react with the substrate silicon (Si). As a result, the properties of the ferroelectric may be lost.

Accordingly, in the present invention, the PZT film 206 is surrounded by a diffusion barrier made up of the first, second and third TiN films 204, 208, and 210 so that the lead (Pb) component and the substrate 200 are formed by the TiN films 204, 208, and 210. By blocking the inter-silicon reaction, the phenomenon in which the PZT film 206 loses the properties of the ferroelectric can be suppressed.

Therefore, since the nonvolatile memory according to the present invention can represent three data states instead of two data states, it can have a larger capacity compared to a conventional memory showing only two states, and also has the same capacity. In comparison, more cells can be integrated in the same area, and the integration can be improved very easily.

In addition, according to the present invention, a P-type junction region 230 is formed in a portion of the substrate 200 corresponding to the drain region, and a hollow ion implantation for forming the P-type junction region 230 may be performed. A thin spacer film 228 is formed on the sidewalls.

Accordingly, the present invention selectively forms the P-type junction region 230 in the drain region and, accordingly, forms a thin spacer oxide film 228, so that hot carriers are easily generated without increasing the threshold voltage. The electric field of the drain region can be increased.

In FIG. 2, reference numeral 202 denotes a device isolation film, 216 an insulating film for a control gate, 218 and 220 a conductive film for a control gate and a tungsten silicide film, 224 a control gate, and 222 a hard mask film made of a nitride film, 234 Are spacers, 232 are nitride films for spacers, and 236 are source / drain regions, respectively.

4A to 4C are cross-sectional views for describing the operation of the nonvolatile memory according to the present invention.

First, when the cell transistor is operated by applying a voltage to the control gate, the nonvolatile memory of the present invention has three states of threshold voltages depending on the state of the ferroelectric and the amount of electrons injected into the floating gate. The data of the three states stored in the memory cell are read from the measurement of the current flowing by applying the gate voltage between the threshold voltages of the "threshold voltage intermediate state" and the "threshold voltage highest state".

FIG. 4A is a cross-sectional view for explaining a voltage application for erasing stored data that is a "threshold voltage minimum state" as a first state, and internal states of ferroelectrics and floating gates at that time.

As shown in the drawing, when -9V is applied to the control gate 424 and + 5V is applied to the source region S, the polarity of the ferroelectric is negative on the silicon substrate and the floating gate on the As a result, the threshold voltage becomes lower than the state before the ferroelectric has polarity (hereinafter, the neutral state) due to the help of the ferroelectric field.

Therefore, in the first state, when a voltage between the "threshold voltage intermediate state" and the "threshold voltage highest state" is applied to the gate, the operating current of the transistor flows a lot.

4B is a cross-sectional view for explaining a voltage application for data storage as a "threshold voltage intermediate state" as a second state and internal states of ferroelectrics and floating gates at that time.

As shown, when + 5V is applied to the control gate 424 and -5V is applied to the drain region D, the polarity of the ferroelectric is positive on the silicon substrate and positive on the floating gate. As a result, the ferroelectric field is reversed in the gate voltage application direction, and thus the threshold voltage is higher than the threshold voltage of the transistor in the neutral state.

Therefore, in the second state, a small amount of current flows when the gate voltage is applied between the "threshold voltage intermediate state" and the "threshold voltage highest state".

4C is a cross-sectional view for explaining a voltage application for data storage as the "threshold voltage highest state" as a third state and the internal states of the ferroelectric and the floating gate at that time.

As shown, when + 9V is applied to the control gate 424, the source region S is made to ground GND, and a voltage of + 5V is applied to the drain region D, the polarity of the ferroelectric is silicon. The substrate side becomes (+) and the floating gate side becomes (-). At this time, electrons are injected into the floating gate by hot carrier injection, and the ferroelectric field is opposite to the gate voltage application direction, and the voltage by the electrons is Because of the reduction effect, the threshold voltage becomes higher than in the case of FIG. 4B.

Therefore, in the third state, since a voltage lower than the threshold voltage is applied to the gate when the gate voltage is applied between the "threshold voltage intermediate state" and the "threshold voltage highest state", no current flows.

In addition, according to the present invention, a P-type junction region 430 is formed in the drain region D, and has a thickness thinner than the sidewall of the gate adjacent to the source region S on the sidewall of the gate adjacent to the drain region D. Since the spacer oxide film 428 is formed to have an asymmetrical structure, the electric field of the drain region D increases, and as a result, the generation of hot carriers for making the "threshold voltage peak state" is facilitated. The threshold voltage peak state "can be made easier.

Meanwhile, in the erasing operation of erasing all stored data, a voltage is applied as shown in FIG. 4A.

At this time, the electrons in the floating gate are tunneled out to the source region, and the polarity of the ferroelectric becomes the negative side of the silicon substrate and the positive side of the floating gate. This has the same device characteristics as the "lowest threshold voltage state".

As described above, the nonvolatile memory according to the present invention can represent three data states of "threshold voltage state", "threshold voltage state", and "threshold voltage state" through one memory cell. Compared with the conventional memory representing the state, more data can be stored, so that a larger capacity can be ensured in the same area and the degree of integration can be improved.

Hereinafter, a method of manufacturing a nonvolatile memory device according to the present invention as described above with reference to FIGS. 3A to 3K will be described in more detail.

Referring to FIG. 3A, a device isolation layer 302 defining an active region is formed according to a known shallow trench isolation (STI) process, and a silicon substrate 300 having a P-well (not shown) is formed. . Then, the first TiN film 304, the ferroelectric PZT film 306, and the second TiN film 308 are sequentially formed on the entire surface of the substrate 300 including the device isolation film 302.

Here, the first and second TiN films 304 and 308 are formed as barrier films to block the reaction between the lead (Pb) component of the ferroelectric PZT film 306 and the silicon of the substrate 300. The first and second TiN films 304 and 308 are each formed to a thickness of about 20 to 500 kPa, and the PZT film 306 is formed to a thickness of about 30 to 1000 kPa.

Referring to FIG. 3B, the second TiN film 308, the PZT film 306, and the first TiN film 304 are patterned by sequentially performing a mask process and an anisotropic etching process. At this time, the patterning of the second TiN film 308, the PZT film 306, and the first TiN film 304 is such that the remaining PZT film 306 is disposed only on the inner side except for both ends of the floating gate to be subsequently formed. It is desirable to carry out in position and size.

Referring to FIG. 3C, a third TiN film 310 is deposited on the entire surface of the substrate 300 including the patterned second TiN film 308, the PZT film 306, and the first TiN film 304. The third TiN film 310 is also deposited as a barrier film to block the reaction between the lead (Pb) component of the PZT film 306 and the silicon of the substrate 300.

Subsequently, a portion of the third TiN film 310 formed on the substrate 300 is removed through anisotropic etching.

At this time, a portion of the third TiN film deposited on the second TiN film 308 is also removed. As a result, the third TiN film 310 is patterned with the second TiN film 308, the PZT film 306, and the first TiN. The PZT film 306, which is a ferroelectric, remains to surround the sidewall of the film 304, and is surrounded by the first, second, and third TiN films 304, 308, and 310.

Referring to FIG. 3D, a gate oxidation process is performed on the resultant of the substrate 300 to selectively grow a silicon oxide film 312 on the exposed surface of the substrate 300.

Referring to FIG. 3E, a floating gate conductive layer 314 is formed on the silicon oxide layer 312 and the third TiN layer 310.

Subsequently, although not shown, the mask process and the anisotropic etching process are performed in sequence to pattern the floating gate conductive film 314 and the silicon oxide film 312 in a line shape extending in one direction, for example, X direction in the drawing. do.

Referring to FIG. 3F, a control gate insulating film 316 and a polysilicon film 318 and a tungsten silicide film are formed on the entire surface of the substrate 300 including the patterned floating gate conductive film 314. After sequentially forming 320, a hard mask film 322 made of, for example, a nitride film is deposited on the tungsten silicide film 320.

Referring to FIG. 3G, the hard mask layer 322 is patterned in the form of a control gate according to a known process.

Then, the tungsten silicide layer 320, the control gate conductive layer 318, and the control gate insulating layer 316 are etched using the patterned hard mask layer 322 as an etching mask. A control gate 324 having a line shape extending in the direction is formed, and then the first polysilicon film and the silicon oxide film 312 are etched to form a floating gate 326 made of the conductive film for floating gate.

In this case, the tunnel oxide film formed of the silicon oxide film 312 is disposed only below both ends of the floating gate 326, and the PZT film 306 is disposed inside the silicon oxide film 312. Preferably, the floating gate 326 is formed such that both sides thereof extend outwardly by 1 to 50 nm from the PZT film 306.

Referring to FIG. 3H, an oxide layer 328 for spacers is formed on the entire surface of the substrate 300 including the stacked floating gate 326 and the control gate 324.

Referring to FIG. 3I, hollow ion implantation is performed on the resultant of the substrate 300 on which the spacer oxide film 328 is formed to form the P-type junction region 330.

In this case, the hollow ion implantation is selectively performed on the portion of the substrate 300 corresponding to the drain predetermined region, and energy of 1 to 50 keV and 1.0 × 10 ¹² to 1.0 using P-type impurities such as B or BF _2. It is carried out with a dose of x10 ¹⁵ ions / cm ² . In addition, the hollow ion implantation is performed while giving an incident angle of about 1 to 30 degrees.

Subsequently, a cleaning process using an HF solution is performed on the resultant of the substrate 300 on which the P-type junction region 330 is formed. In the cleaning process, the spacer oxide film 328 formed in the drain predetermined region portion where the ion implantation is performed is etched at a higher speed than the spacer oxide film 328 formed in the source predetermined region portion where the ion implantation is not performed to have a thin thickness. do.

Here, in the present invention, the inclined ion implantation is selectively performed in the drain predetermined region to form the P-type junction region 330 and the spacer oxide film 328 having a thin thickness, so that only the electric field of the drain region is increased without increasing the threshold voltage. As a result, the generation of hot carriers is facilitated, making the above-mentioned "threshold peak state" easier.

Referring to FIG. 3J, after the spacer nitride layer 332 is deposited on the spacer oxide layer 328, the floating gate 326 and the control gate 324 stacked by blanket etching the spacer layers 328 and 332. Spacers 334 are formed on both side walls of the substrate.

Referring to FIG. 3K, a stacked floating gate 326 and a control gate 324 including the spacer 334 are formed by performing high concentration ion implantation of n-type impurities on the resultant of the substrate 300 on which the spacer 334 is formed. The source / drain regions 336 are formed in the active regions of the substrate 300 on both sides, and as a result, the manufacture of the nonvolatile memory cell having the three data states according to the present invention is completed.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention applies a tunnel oxide film made of a silicon oxide film only at both ends of a floating gate to a basic structure of a flash memory, and arranges a ferroelectric inside thereof, thereby providing hot carriers in the electric field direction and the floating gate in the ferroelectric. In combination with the electrons injected into the memory cell, a memory cell having three data states can be manufactured.

Therefore, since the present invention can create three data states with one memory cell, a high capacity memory can be manufactured in the same area, and conversely, higher integration can be realized at the same capacity.

In addition, since the memory device of the present invention functions as a nonvolatile memory in which data stored in a memory cell is not erased even when the power is turned off, it can be very advantageously applied to a portable device having a large amount of information to be processed.

In addition, the present invention forms a P-type junction region by selectively inclining ion implantation into the drain region portion, thereby increasing the electric field of the drain region to make the "threshold voltage peak state" of the three data states easier. Can be.

Claims (15)

Silicon substrates; A floating gate formed on the silicon substrate; A tunnel oxide layer interposed below both ends of the floating gate between the silicon substrate and the floating gate; A ferroelectric interposed between the silicon substrate inside the tunnel oxide film and the floating gate; A diffusion barrier film surrounding the ferroelectric material; A control gate formed on the substrate including the floating gate; A gate insulating film formed under the control gate; A spacer formed on both sidewalls of the floating gate and the control gate including the tunnel oxide layer and the gate insulating layer; A P-type junction region formed in the drain predetermined region of the substrate; And Source / drain regions formed in the substrate surface on both sides of the control gate including the spacers; Nonvolatile memory comprising a. Claim 2 has been abandoned due to the setting registration fee. Claim 2 has been abandoned due to the setting registration fee. And the ferroelectric is formed of a PZT film. Claim 3 has been abandoned due to the setting registration fee. Claim 3 has been abandoned due to the setting registration fee. And the first, second and third diffusion barrier films are formed of a TiN film or an Al ₂ O ₃ film. Claim 4 was abandoned when the registration fee was paid. Claim 4 was abandoned when the registration fee was paid. And the floating gate is formed such that both sides of the floating gate extend 1-50 nm outward from the ferroelectric. Claim 5 was abandoned upon payment of a set-up fee. Claim 5 was abandoned upon payment of a set-up fee. And the P-type junction region is formed through hollow ion implantation using B or BF ₂ . Sequentially forming a first diffusion barrier film, a ferroelectric material, and a second diffusion barrier film on the silicon substrate; Patterning the second diffusion barrier film, the ferroelectric, and the first diffusion barrier film to a size smaller than a desired floating gate; Forming a third diffusion barrier film on the substrate to surround the patterned second diffusion barrier film, the ferroelectric material, and the first diffusion barrier film; Selectively growing a silicon oxide film on the substrate surface; Forming a conductive film for a floating gate on the silicon oxide film and the third diffusion barrier film; Patterning the conductive film for silicon and the silicon oxide film in a line shape extending in one direction; Sequentially forming a control gate insulating film, a control gate conductive film, and a hard mask film on an entire surface of the substrate including the patterned floating gate conductive film; Etching the hard mask layer, the conductive layer for the control gate, and the insulating layer for the control gate to form a line-shaped control gate extending in a direction perpendicular to one direction and a gate insulating layer disposed under the control gate; Etching the floating gate conductive film and the silicon oxide film to form a floating gate including the floating gate conductive film, and forming a tunnel oxide film disposed under both ends of the floating gate; Forming an oxide film for a spacer on both sidewalls of the stacked floating gate and the control gate; Selectively inclining ion implantation of P-type impurities into a region to be drained of the substrate resultant on which the oxide film for the spacer is formed; Forming a spacer nitride film on the spacer oxide film to form a spacer including a laminated film of an oxide film and a nitride film; And Forming a source / drain region in the substrate surface on both sides of the control gate including the spacer; Nonvolatile memory manufacturing method comprising a. Claim 7 was abandoned upon payment of a set-up fee. Claim 7 was abandoned upon payment of a set-up fee. And the ferroelectric material is formed of a PZT film. Claim 8 was abandoned when the registration fee was paid. Claim 8 was abandoned when the registration fee was paid. The ferroelectric is a nonvolatile memory manufacturing method, characterized in that formed to a thickness of 30 ~ 1000Å. Claim 9 has been abandoned due to the setting registration fee. Claim 9 has been abandoned due to the setting registration fee. The first, second and third diffusion barrier films are formed of a TiN film or an Al ₂ O ₃ film. Claim 10 has been abandoned due to the setting registration fee. Claim 10 has been abandoned due to the setting registration fee. And the first, second and third diffusion barrier films are formed to a thickness of 20 to 500 kHz. delete Claim 12 is abandoned in setting registration fee. Claim 12 is abandoned in setting registration fee. And the floating gate is formed such that both sides thereof extend from 1 to 50 nm outward from the ferroelectric material. Claim 13 was abandoned upon payment of a registration fee. Claim 13 was abandoned upon payment of a registration fee. Gradient ion implantation of the P-type impurity is performed using energy of 1 to 50 keV and dose of 1.0 × 10 ¹² to 1.0 × 10 ¹⁵ ions / cm ² using B or BF ₂ . Non-volatile memory manufacturing method. Claim 14 has been abandoned due to the setting registration fee. Claim 14 has been abandoned due to the setting registration fee. And inclining ion implantation of the P-type impurity is performed while giving an angle of incidence of 1 to 30 °. Claim 15 is abandoned in the setting registration fee payment. Claim 15 is abandoned in the setting registration fee payment.

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