CN102117814B - Grid-sharing flash memory unit and preparation method thereof - Google Patents
Grid-sharing flash memory unit and preparation method thereof Download PDFInfo
- Publication number
- CN102117814B CN102117814B CN201110009217.5A CN201110009217A CN102117814B CN 102117814 B CN102117814 B CN 102117814B CN 201110009217 A CN201110009217 A CN 201110009217A CN 102117814 B CN102117814 B CN 102117814B
- Authority
- CN
- China
- Prior art keywords
- semiconductor substrate
- grid
- flash memory
- erase gate
- polysilicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 230000005641 tunneling Effects 0.000 claims abstract description 15
- 238000009413 insulation Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 128
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 61
- 229920005591 polysilicon Polymers 0.000 claims description 61
- 238000000034 method Methods 0.000 claims description 42
- 239000011229 interlayer Substances 0.000 claims description 25
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 230000008569 process Effects 0.000 claims description 11
- 238000003860 storage Methods 0.000 claims description 11
- -1 floating boom Substances 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000000126 substance Substances 0.000 description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 7
- 238000001947 vapour-phase growth Methods 0.000 description 7
- 239000002800 charge carrier Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000002784 hot electron Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A kind of grid-sharing flash memory unit and preparation method thereof, described grid-sharing flash memory unit comprises: Semiconductor substrate; Be positioned at two memory transistors in Semiconductor substrate; And between two memory transistors, and embedding the erase gate in Semiconductor substrate, two described memory transistors share an erase gate, carry out electric isolution between described erase gate and memory transistor by tunneling insulation layer.Described grid-sharing flash memory unit and preparation method thereof, by described erase gate is slipped in Semiconductor substrate, can when same light scale, the channel length of effective increase device, thus avoid the short-channel effect of device, improve the interference free performance of memory device array under programming state; The programming of device can be realized simultaneously under lower control-grid voltage, improve the programming efficiency of device.Excellent interference free performance and lower programming Control voltage, for future, the micro of memory device provides possibility.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly a kind of grid-sharing flash memory unit and preparation method thereof.
Background technology
In current semiconductor industry, integrated circuit (IC) products mainly can be divided into three major types type: analog circuit, digital circuit and DA combination circuit, and wherein memory device is an important kind in digital circuit.And in memory device, the development of flash memory (flash memory is called for short flash memory) is particularly rapid in recent years.The main feature of flash memory is the information that can keep for a long time when not powering up storing; And have that integrated level is high, access speed is fast, be easy to the advantages such as erasing and rewriting, be thus widely used in the multinomial field such as microcomputer, Automated condtrol.
The standard physical structure of flash memory is called memory cell (bit).The structure of memory cell is different from conventional MOS transistor.Separated by gate insulator between the grid (gate) of conventional MOS transistor and conducting channel, be generally oxide layer (oxide); And flash memory layer of substance more than between control gate (CG:control gate is equivalent to the grid of conventional MOS transistor) and conducting channel, be referred to as floating boom (FG:floating gate).Due to the existence of floating boom, make flash memory can complete three kinds of basic manipulation modes: i.e. reading and writing, erasing.Even if when not having power supply to supply, the existence of floating boom can keep the integrality storing data.Fig. 1 gives the structural representation of a grid-sharing flash memory unit.Each grid-sharing flash memory unit comprises two memory transistors 110 and erase gate 120 (EG:erasing gate) adjacent with it, and two memory transistors share an erase gate 120, described memory transistor comprises floating boom 101, control gate 105, has interlayer insulating film 102 between described floating boom 101 and control gate 105; Be formed with side wall 104 at control gate 105 and interlayer insulating film 102 both sides simultaneously, between described erase gate 120 and floating boom 101, there is tunneling insulation layer 103.
Due to physical characteristic and the structure of described floating boom 101, it can store electric charge, according to the situation storing electric charge, can be divided into two states, thus can store a bit binary data.The corresponding relation stored in floating boom 101 between the state of electric charge and the binary data (0 or 1) representated by it can have different definition, generally speaking, when floating boom 101 is injected into negatron, this position is just written to " 0 " by numeral " 1 ", this process is write, also can be described as programming mode; Relative, after negatron is removed from floating boom 101, this position is just become " 1 " by digital " 0 ", and this process is called erasing.Technology about electron injection or erasing in the industry cycle has many discussions, wherein usually adopts channel hot electron tunneling injection (channel hotelectron injection) mechanism during programming.When programming, source ground, channel electrons is accelerated to become hot electron under the effect of drain bias, under the electric field action that control-grid bias is formed, hot electron direction changes, and crosses oxide layer potential barrier between floating boom 101 and conducting channel, be injected into floating boom 101, thus complete programming.For existing grid-sharing flash memory unit, just can effectively programme due to high voltage must be applied on control gate and drain electrode during programming, and the cross-interference issue of these high voltages when storage array not only can be caused to programme, be also unfavorable for the further micro of memory device size simultaneously.
Summary of the invention
The problem that the present invention solves is to provide a kind of grid-sharing flash memory unit and preparation method thereof, to improve storage array density and the programming efficiency of grid-sharing flash memory unit, and effectively reduces the operating voltage of grid-sharing flash memory unit.
For solving the problem, the invention provides a kind of grid-sharing flash memory unit, comprising: Semiconductor substrate; Be positioned at two memory transistors in Semiconductor substrate; And between two memory transistors, and embedding the erase gate in Semiconductor substrate, two described memory transistors share an erase gate, carry out electric isolution between described erase gate and memory transistor by tunneling insulation layer.
Optionally, erase gate embeds the part in Semiconductor substrate is arc or semicircle or inverted trapezoidal.
Optionally, the minimum dimension that the degree of depth in erase gate embedding Semiconductor substrate is exempted from needed for programming interference by photolithographic process dimension and storage array determined.
Optionally, described memory transistor comprises the gate dielectric layer be positioned at successively on semiconductor, floating boom, interlayer insulating film, control gate and dielectric layer, and is positioned at the side wall of interlayer insulating film, control gate and dielectric layer side, is positioned at the sacrifice layer outside side wall.
The present invention also provides a kind of formation method of grid-sharing flash memory unit unit, comprising:
Semiconductor substrate is provided, forms two memory transistors on the semiconductor substrate;
Etch the Semiconductor substrate between two memory transistors, form groove;
Form the tunneling insulation layer covering described groove and memory transistor;
Deposition of polysilicon layer, described polysilicon layer fills the space between described groove and adjacent memory transistor;
Polysilicon layer described in planarization, form erase gate, two described memory transistors share an erase gate, and carry out electric isolution by tunneling insulation layer between erase gate and memory transistor.
Further, the manufacture method of two described storage crystal pipe units comprises:
Semiconductor substrate is provided, described Semiconductor substrate is formed with successively gate dielectric layer, the first polysilicon layer, interlayer insulating film, the second polysilicon layer and dielectric layer;
Etch described dielectric layer, the second polysilicon layer and interlayer insulating film, the second polysilicon layer forms two control gates be separated;
Form side wall at described dielectric layer, the second polysilicon layer with the relative sidewall of interlayer insulating film, outside side wall, form a sacrifice layer;
Etch described first polysilicon layer and gate dielectric layer, the first polysilicon layer forms two floating booms be separated.
Described groove shape is such as arc or semicircle or inverted trapezoidal.
The minimum dimension that the degree of depth in described erase gate embedding Semiconductor substrate is exempted from needed for programming interference by photolithographic process dimension and storage array determined.
Adopt grid-sharing flash memory unit described in the present embodiment and preparation method thereof, by described erase gate is slipped in Semiconductor substrate, can when same light scale, the channel length of effective increase device, thus avoid the short-channel effect of device, improve the interference free performance of memory device array under programming state; Simultaneously because device channel is perpendicular to memory transistor floating boom, in raceway groove, hot electron traffic direction is orthogonal with floating boom, thus can realize the programming of device under lower control-grid voltage, improves the programming efficiency of device.Further, under the ever-reduced main trend of device size, the grid-sharing flash memory unit structure described in the present embodiment can reduce the area of single flash cell, improves the effect of the density of device.Further, the operating voltage of device can also be reduced, improve the device performance of grid-sharing flash memory unit.
Accompanying drawing explanation
Fig. 1 is the structural representation of the grid-sharing flash memory unit unit of prior art;
Fig. 2 be embodiment of the present invention the structural representation of grid-sharing flash memory unit unit;
Fig. 3 is the schematic flow sheet of the formation method of the grid-sharing flash memory unit of embodiment of the present invention;
Fig. 4 to Figure 11 is the cross-sectional view of the grid-sharing flash memory unit formation method of the embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here to implement with multiple, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention.Therefore the present invention is not by the restriction of following public concrete enforcement.
Method provided by the invention is not only applicable to grid-sharing flash memory unit unit, is applicable to the general memory device with grid dividing structure yet, is specially adapted to characteristic size at 180nm and following memory device.
The present embodiment provides a kind of grid-sharing flash memory unit, and the structure of described grid-sharing flash memory unit as shown in Figure 2, comprising: Semiconductor substrate 200; Be positioned at two memory transistors 210 in Semiconductor substrate 200; And between two memory transistors 210, and the erase gate 240 in embedding Semiconductor substrate, described two memory transistors 210 share an erase gate 240, carry out electric isolution between described erase gate 240 and memory transistor 210 by tunneling insulation layer 230.
The erase gate part embedded in Semiconductor substrate is arc or semicircle or inverted trapezoidal or other rule or irregular shape, and erase gate embeds the minimum dimension that the degree of depth in Semiconductor substrate exempted from needed for programming interference by photolithographic process dimension and storage array and determined.
Described memory transistor comprises the gate dielectric layer be positioned at successively on semiconductor, floating boom, interlayer insulating film, control gate and dielectric layer, and is positioned at the side wall of interlayer insulating film, control gate and dielectric layer side, is positioned at the sacrifice layer outside side wall.
Adopt the grid-sharing flash memory unit described in the present embodiment, by described erase gate is slipped in Semiconductor substrate, can when same light scale, the channel length of effective increase device, thus avoid the short-channel effect of device, improve the interference free performance of memory device array under programming state; Simultaneously because device channel is perpendicular to memory transistor floating boom, in raceway groove, hot electron traffic direction is orthogonal with floating boom, thus can realize the programming of device under lower control-grid voltage, improves the programming efficiency of device.Further, under the ever-reduced main trend of device size, the grid-sharing flash memory unit structure described in the present embodiment can reduce the area of single flash cell, improves the effect of the density of device.Further, the operating voltage of device can also be reduced, improve the device performance of grid-sharing flash memory unit.
Fig. 3 gives the schematic flow sheet of the formation method of the grid-sharing flash memory unit of embodiment of the present invention.As shown in Figure 3, perform step S102, Semiconductor substrate is provided, form two memory transistors on the semiconductor substrate; Perform step S103, etch the Semiconductor substrate between two memory transistors, form groove; Perform step S104, form the tunneling insulation layer covering described groove and memory transistor; Perform step S105, deposition of polysilicon layer, described polysilicon layer fills the space between described groove and adjacent memory transistor; Perform step S106, polysilicon layer described in planarization, form erase gate, two described memory transistors share an erase gate, and carry out electric isolution by tunneling insulation layer between erase gate and memory transistor.
Below in conjunction with drawings and Examples, embodiment of the present invention is described in detail.Fig. 4 to Figure 10 is the cross-sectional view of the formation method of grid-sharing flash memory unit according to the first embodiment of the present invention, and described schematic diagram is example, excessively should not limit the scope of protection of the invention at this.
With reference to Fig. 3 and Fig. 4, perform step S102, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 forms two memory transistors 210.Described Semiconductor substrate 200 can be silicon or the SiGe of monocrystalline, polycrystalline or non crystalline structure; Also can be silicon-on-insulator (SOI); Or other material can also be comprised, the III-V such as such as GaAs.Described Semiconductor substrate 200 has certain isolation structure, can be that shallow trench isolation is from (STI).
The tunnelling charge carrier of grid-sharing flash memory unit can be electronics, also can be hole, and when tunnelling charge carrier is electronics, Semiconductor substrate 200 part of grid-sharing flash memory unit to be formed is P type, realizes by injecting boron ion.When tunnelling charge carrier is hole, Semiconductor substrate 200 part of grid-sharing flash memory unit to be formed is N-type, realizes by injecting phosphonium ion.The memory device of the present embodiment adopts electronics as charge carrier.
The method forming two memory transistors 210 can be any prior art well known to those skilled in the art, clear complete in order to specification, provide the specific embodiment that forms two memory transistors 210 below, but do not show to limit the method that other form two memory transistors 210.
The manufacture method of two described storage crystal pipe units comprises:
Semiconductor substrate is provided, described Semiconductor substrate is formed with successively gate dielectric layer, the first polysilicon layer, interlayer insulating film, the second polysilicon layer and dielectric layer;
Etch described dielectric layer, the second polysilicon layer and interlayer insulating film, the second polysilicon layer forms two control gates be separated;
Form side wall at described dielectric layer, the second polysilicon layer with the relative sidewall of interlayer insulating film, outside side wall, form a sacrifice layer;
Etch described first polysilicon layer and gate dielectric layer, the first polysilicon layer forms two floating booms be separated.
With reference to shown in accompanying drawing 5, form gate dielectric layer 310, first polysilicon layer 320 successively on the semiconductor substrate, interlayer insulating film 330 and the second polysilicon layer 340.Described gate dielectric layer 310 can be silica, silicon nitride, silicon oxynitride or other high-g value, selects silica at this.Its formation method can be boiler tube thermal oxidation, the technique such as ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and the present embodiment adopts boiler tube thermal oxidation technology.
Gate dielectric layer 310 is formed the first polysilicon layer 320, is used as to form floating boom (floating gate).The formation method of polysilicon can be chemical vapor deposition (CVD), low-pressure chemical vapor phase deposition (LPCVD) technique, and the present embodiment adopts low-pressure chemical vapor phase deposition technique.Adulterate to the first polysilicon layer 320, in the present embodiment, tunnelling charge carrier is electronics, therefore carries out N-type doping, and Doped ions can be the pentads such as phosphorus, antimony, arsenic.
After formation first polysilicon layer 320, form interlayer insulating film 330 thereon, described interlayer insulating film 330 can be silica or ONO three-decker or silicon nitride or silicon oxynitride or other high-g value, ONO three-decker is selected in the present embodiment, i.e. oxide-nitride-oxide, as the insulating barrier between the first polysilicon layer 320 and the second polysilicon layer formed afterwards, this structure has the advantage of little, low defect of leaking electricity.The formation method of silica can be the techniques such as ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), the vapor deposition of the present embodiment using plasma enhanced chemical.The formation method of silicon nitride can be plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD) technique.The present embodiment adopts low-pressure chemical vapor phase deposition.
Then on interlayer insulating film 330, the second polysilicon layer 340 is formed, as formation control grid (controlgate).The formation method of formation method reference first polysilicon layer of described second polysilicon layer 340, the present embodiment adopts low-pressure chemical vapor phase deposition technique.Because tunnelling charge carrier in the present embodiment is electronics, carry out N-type doping to described second polysilicon layer 340, Doped ions can be the pentads such as phosphorus, antimony, arsenic.
Afterwards, the second described polysilicon layer 340 forms dielectric layer 350, for the protection of the second polysilicon layer 340.Described dielectric layer is as the double-decker formed for oxide layer and silicon nitride layer.
With reference to Fig. 6, described dielectric layer 350, second polysilicon layer 340, interlayer insulating film 330 are etched.First on described dielectric layer 350, form photoresist layer, afterwards patterned photo glue-line, the shape of formation control grid, this technology is conventionally known to one of skill in the art.Lithographic line width is determined by technological requirement.After photoetching completes, be that mask carries out dry etching to each rete with photoresist, carved by each layer film of disposable etching by the first polysilicon layer more than 320.Relevant rete after etching is followed successively by gate dielectric layer 310, the first polysilicon layer 320, interlayer insulating film 330 ', the second polysilicon layer 340 ', dielectric layer 350 '.Through above-mentioned etching, the second polysilicon layer 340 ' forms the control gate of memory transistor of grid-sharing flash memory unit, and two described control gates are separated, between for follow-up formation erase gate.
With reference to Fig. 7, form side wall 360 in the relative side of described interlayer insulating film 330 ', the second polysilicon layer 340 ', dielectric layer 350 ', described side wall 360 is such as oxide layer, silicon nitride double-decker.Afterwards, a sacrifice layer (Sacrificial Spacer) 370 is formed in the outside of side wall 360.With reference to Fig. 8, with side wall 360, sacrifice layer 370 and dielectric layer 350 ' for mask, etch the first polysilicon layer 320 and gate dielectric layer 310, relevant rete after etching is followed successively by gate dielectric layer 310 ', first polysilicon layer 320 ', interlayer insulating film 330 ', the second polysilicon layer 340 ', dielectric layer 350 ', wherein, the first polysilicon layer 320 ' is as floating boom, and the second polysilicon layer 340 ' is as control gate.
Described floating boom be separated, between for follow-up formation erase gate.
Optionally, described gate dielectric layer 310 also can not etch, and that is, with side wall 360, sacrifice layer 370 and the second polysilicon layer 340 ' for mask, only etches the first polysilicon layer 320 to gate dielectric layer 310.Gate dielectric layer 310 is left in lower step process and etches.
By the processing step corresponding to accompanying drawing 5-7, form two memory transistors 210.
With reference to Fig. 3 and Fig. 9, perform step S103, etch the Semiconductor substrate between two memory transistors 210, form groove 220; The processing step forming described groove 220 is any known prior art, such as wet method or dry etching.Described groove shape is such as semicircle or inverted trapezoidal or other rule or irregular shape.The minimum dimension that the degree of depth of described groove is exempted from needed for programming interference by photolithographic process dimension and storage array determined.For embedding control gate wherein, to increase channel length, reducing the device density of memory cell, improving the performance of grid-sharing flash memory unit.
With reference to Fig. 3 and Figure 10, perform step S104, form the tunneling insulation layer 230 covering described groove and memory transistor; The present embodiment is preferably oxide layer (tunnel oxide), and the generation type of described tunneling insulation layer 230 can be plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD).The present embodiment selects low-pressure chemical vapor phase deposition.
With reference to Fig. 3 and Figure 11, perform step S105, deposit spathic silicon, described polysilicon fills the space between described groove and adjacent memory transistor 210; The technique forming described polysilicon is such as chemical vapor deposition method.Described polysilicon fills up the space between described groove and adjacent memory transistor, for the formation of erase gate 240.
Afterwards, perform step S106, polysilicon described in planarization, form erase gate 240, described two memory transistors 210 share an erase gate 240, and carry out electric isolution by tunneling insulation layer 230 between erase gate and memory transistor 210.Described flatening process is such as CMP (Chemical Mechanical Polishing) process.
Adopt the grid-sharing flash memory unit that the method described in the present embodiment is formed, by described erase gate is embedded in Semiconductor substrate, when same light scale, the effective channel length increasing device.。Further, under the ever-reduced main trend of device size, the grid-sharing flash memory unit structure described in the present embodiment can reduce the area of single flash cell, improves the effect of the density of device.Further, the operating voltage of device can also be reduced, improve the device performance of grid-sharing flash memory unit.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (6)
1. a grid-sharing flash memory unit, comprising:
Semiconductor substrate;
Be positioned at two memory transistors in Semiconductor substrate, described memory transistor comprises the gate dielectric layer be positioned at successively on semiconductor, floating boom, interlayer insulating film, control gate and dielectric layer, and be positioned at the side wall of interlayer insulating film, control gate and dielectric layer side, be positioned at the sacrifice layer outside side wall;
And between two memory transistors, and embedding the erase gate in Semiconductor substrate, two described memory transistors share an erase gate, carry out electric isolution between described erase gate and memory transistor by tunneling insulation layer.
2. grid-sharing flash memory unit according to claim 1, is characterized in that, the part that erase gate embeds in Semiconductor substrate is arc or inverted trapezoidal.
3. grid-sharing flash memory unit according to claim 1, is characterized in that, the minimum dimension that the degree of depth in erase gate embedding Semiconductor substrate is exempted from needed for programming interference by photolithographic process dimension and storage array determined.
4. a formation method for grid-sharing flash memory unit, is characterized in that, comprising:
Semiconductor substrate is provided, forms two memory transistors on the semiconductor substrate;
Etch the Semiconductor substrate between two memory transistors, form groove;
Form the tunneling insulation layer covering described groove and memory transistor;
Deposition of polysilicon layer, described polysilicon layer fills the space between described groove and adjacent memory transistor;
Polysilicon layer described in planarization, form erase gate, two described memory transistors share an erase gate, and carry out electric isolution by tunneling insulation layer between erase gate and memory transistor;
Wherein, the manufacture method of two described storage crystal pipe units comprises:
Semiconductor substrate is provided, described Semiconductor substrate is formed with successively gate dielectric layer, the first polysilicon layer, interlayer insulating film, the second polysilicon layer and dielectric layer;
Etch described dielectric layer, the second polysilicon layer and interlayer insulating film, the second polysilicon layer forms two control gates be separated;
Form side wall at described dielectric layer, the second polysilicon layer with the relative sidewall of interlayer insulating film, outside side wall, form a sacrifice layer;
Etch described first polysilicon layer and gate dielectric layer, the first polysilicon layer forms two floating booms be separated.
5. the formation method of grid-sharing flash memory unit according to claim 4, is characterized in that, described groove shape is arc or inverted trapezoidal.
6. the formation method of grid-sharing flash memory unit according to claim 5, is characterized in that, the minimum dimension that the degree of depth in erase gate embedding Semiconductor substrate is exempted from needed for programming interference by photolithographic process dimension and storage array determined.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110009217.5A CN102117814B (en) | 2011-01-17 | 2011-01-17 | Grid-sharing flash memory unit and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110009217.5A CN102117814B (en) | 2011-01-17 | 2011-01-17 | Grid-sharing flash memory unit and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102117814A CN102117814A (en) | 2011-07-06 |
| CN102117814B true CN102117814B (en) | 2015-08-26 |
Family
ID=44216494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110009217.5A Active CN102117814B (en) | 2011-01-17 | 2011-01-17 | Grid-sharing flash memory unit and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102117814B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151458B (en) * | 2013-03-22 | 2015-04-29 | 厦门博佳琴电子科技有限公司 | Embedded phase change memory array and manufacturing method |
| CN103839850B (en) * | 2014-03-17 | 2016-08-17 | 上海华虹宏力半导体制造有限公司 | Programming row crosstalk online test method |
| CN104091803A (en) | 2014-07-24 | 2014-10-08 | 上海华虹宏力半导体制造有限公司 | Split gate memory, semiconductor device and method for making semiconductor device |
| CN104934328A (en) * | 2015-06-07 | 2015-09-23 | 上海华虹宏力半导体制造有限公司 | Method to reduce the amount of photomasks in flash memory manufacture process |
| CN108648777B (en) * | 2018-05-10 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Programming sequential circuit and method of double-separation gate flash memory |
| CN109830481A (en) * | 2019-03-20 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory and its manufacturing method |
| CN110148432B (en) * | 2019-05-23 | 2020-11-13 | 上海华虹宏力半导体制造有限公司 | NORD memory array, manufacturing method thereof and memory |
| CN111739892A (en) * | 2020-07-30 | 2020-10-02 | 上海华虹宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1534785A (en) * | 2003-04-01 | 2004-10-06 | ����뵼��ɷ�����˾ | Fast storage unit, manufacturing method of fast storage unit and its operation method |
| CN1545707A (en) * | 2001-08-25 | 2004-11-10 | Non-volatile semiconductor memory and method of operating the same | |
| CN1794458A (en) * | 2004-09-22 | 2006-06-28 | 三星电子株式会社 | Non-volatile memory and method of fabricating same |
| CN101604694A (en) * | 2008-02-20 | 2009-12-16 | 台湾积体电路制造股份有限公司 | Multi-transistor element and operation thereof and manufacture method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6885586B2 (en) * | 2002-09-19 | 2005-04-26 | Actrans System Inc. | Self-aligned split-gate NAND flash memory and fabrication process |
| US6855598B2 (en) * | 2003-03-13 | 2005-02-15 | Powerchip Semiconductor Corp. | Flash memory cell including two floating gates and an erasing gate |
| US7262096B2 (en) * | 2004-01-15 | 2007-08-28 | Powerchip Semiconductor Corp. | NAND flash memory cell row and manufacturing method thereof |
-
2011
- 2011-01-17 CN CN201110009217.5A patent/CN102117814B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1545707A (en) * | 2001-08-25 | 2004-11-10 | Non-volatile semiconductor memory and method of operating the same | |
| CN1534785A (en) * | 2003-04-01 | 2004-10-06 | ����뵼��ɷ�����˾ | Fast storage unit, manufacturing method of fast storage unit and its operation method |
| CN1794458A (en) * | 2004-09-22 | 2006-06-28 | 三星电子株式会社 | Non-volatile memory and method of fabricating same |
| CN101604694A (en) * | 2008-02-20 | 2009-12-16 | 台湾积体电路制造股份有限公司 | Multi-transistor element and operation thereof and manufacture method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102117814A (en) | 2011-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102117814B (en) | Grid-sharing flash memory unit and preparation method thereof | |
| KR101113767B1 (en) | 3d non-volatile memory device and method for operating and fabricating the same | |
| US7315057B2 (en) | Split gate non-volatile memory devices and methods of forming same | |
| JP5116987B2 (en) | Integrated semiconductor nonvolatile memory device | |
| KR101024336B1 (en) | Nonvolatile memory cell and fabrication method thereof | |
| TWI720350B (en) | Split-gate type non-volatile memory and manufacturing method thereof | |
| CN102347281B (en) | Split-gate flash memory unit and forming method thereof | |
| TWI433304B (en) | Eeprom cell | |
| CN102938406A (en) | Split gate type flash memory and forming method thereof | |
| JP2006253685A (en) | Split gate nonvolatile memory device and method of forming the same | |
| CN101807577B (en) | Split gate flash memory and manufacture method thereof | |
| CN102044545B (en) | Flash memory of discrete gate and manufacturing method thereof | |
| CN104617048A (en) | Flash memory and forming method thereof | |
| CN102593061B (en) | Flash memory of discrete gate and manufacture method thereof | |
| KR100752192B1 (en) | Single-poly structure of flash memory device and manufacturing method thereof | |
| CN104658978A (en) | Flash memory and method for manufacturing same | |
| CN103872059A (en) | P-type channel flash memory and manufacturing method thereof | |
| CN104425386A (en) | Flash memory and method for manufacturing same | |
| CN102693905B (en) | The formation method of flash cell and floating boom thereof | |
| CN102593059B (en) | Grid-sharing flash memory unit and preparation method thereof | |
| CN102201452B (en) | Nonvolatile memory and manufacture method thereof | |
| CN102163576A (en) | Split-gate flash memory unit and manufacturing method thereof | |
| KR100771418B1 (en) | Self Align type Flash Memory Device and Method of Forming the same | |
| CN102593060B (en) | Grid-sharing flash memory unit and manufacture method thereof | |
| CN103515391A (en) | Nonvolatile memory unit and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140505 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140505 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |