CN102117814A - Grid-sharing flash memory unit and manufacturing method thereof - Google Patents
Grid-sharing flash memory unit and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a grid-sharing flash memory unit and a manufacturing method thereof. The grid-sharing flash memory unit comprises a semiconductor substrate, two memory transistors positioned on the semiconductor substrate, and an erase grid positioned between the two memory transistors and embedded in the erase grid of the semiconductor substrate, wherein the two memory transistors share the erase grid, and the erase grid and the memory transistors are electrically separated through a tunneling insulating layer. According to the grid-sharing flash memory unit and the manufacturing method thereof, the erase grid is embedded in the semiconductor substrate, thereby effectively increasing channel length of the device, further avoiding short channeling effect of the device and improving the interference resistance of a memory array in a programming state in a condition of same photo-etching scale, simultaneously being capable of realizing programming under a lower control grid voltage, and improving the programming efficiency of the device. The excellent interference resistance and the lower programming control voltage enable micro shrinkage of the memory to be possible.
Description
Technical field
The present invention relates to field of semiconductor technology, particularly a kind of grid flash memory unit and preparation method thereof.
Background technology
In present semiconductor industry, integrated circuit (IC) products mainly can be divided into the three major types type: analog circuit, digital circuit and DA combination circuit, wherein memory device is an important kind in the digital circuit.And in memory device, the development of flash memory (flash memory is called for short flash memory) is particularly rapid in recent years.The main feature of flash memory is can keep canned data for a long time under situation about not powering up; And have integrated level height, access speed fast, be easy to wipe and advantage such as rewriting, thereby obtained using widely in multinomial fields such as microcomputer, automation controls.
The standard physical structure of flash memory is called memory cell (bit).The structure of memory cell is different with conventional MOS transistor.Separate by gate insulator between the grid (gate) of conventional MOS transistor and conducting channel, be generally oxide layer (oxide); And flash memory more than between control gate (CG:control gate is equivalent to the grid of conventional MOS transistor) and conducting channel layer of substance, be referred to as floating boom (FG:floating gate).Because the existence of floating boom makes flash memory can finish three kinds of basic manipulation modes: i.e. reading and writing, wipe.Even if under the situation that does not have power supply to supply with, the existence of floating boom can keep storing the integrality of data.Fig. 1 has provided the structural representation of a grid flash memory unit.Each grid flash memory unit comprises two memory transistors 110 and adjacent with it erase gate 120 (EG:erasing gate), and two shared erase gates 120 of memory transistor, described memory transistor comprises floating boom 101, control gate 105, and 105 of described floating boom 101 and control gates have interlayer insulating film 102; Simultaneously be formed with side wall 104, have tunneling insulation layer 103 between described erase gate 120 and the floating boom 101 at control gate 105 and interlayer insulating film 102 both sides.
Because the physical characteristic and the structure of described floating boom 101, it can store charge, according to the situation of store charge, it can be divided into two states, thereby can store a bit binary data.Corresponding relation between the binary data of the state of store charge and its representative in the floating boom 101 (0 or 1) can have different definition, generally speaking, when floating boom 101 was injected into negatron, " 0 " was just write as by numeral " 1 " in this position, this process also can be described as programming mode for writing; Relative, after negatron was removed from floating boom 101, this position just became " 1 " by digital " 0 ", and this process is called wipes.Inject or the technology of wiping in the industry cycle has many discussions about electronics, adopt the channel hot electron tunnelling to inject (channel hotelectron injection) mechanism when wherein programming usually.When programming, source ground, channel electrons quickens to become hot electron under the effect of drain bias, under the formed electric field action of control-grid bias, the hot electron direction changes, and crosses oxide layer potential barrier between floating boom 101 and conducting channel, be injected into floating boom 101, thereby finish programming.For existing grid flash memory unit, because must apply high voltage in control gate and drain electrode during programming just can effectively programme, and these high voltages not only can cause the cross-interference issue when storage array is programmed, and also are unfavorable for the further micro of memory device size simultaneously.
Summary of the invention
The problem that the present invention solves provides a kind of grid flash memory unit and preparation method thereof, improving the storage array density and the programming efficiency of grid flash memory unit, and effectively reduces the operating voltage of grid flash memory unit.
For addressing the above problem, the invention provides a kind of grid flash memory unit, comprising: Semiconductor substrate; Be positioned at two memory transistors on the Semiconductor substrate; And between two memory transistors, and the erase gate in the embedding Semiconductor substrate, the shared erase gate of described two memory transistors carries out electricity by tunneling insulation layer between described erase gate and the memory transistor and isolates.
Optionally, the part in the erase gate embedding Semiconductor substrate is an arc or semicircle or trapezoidal.
Optionally, erase gate embeds the degree of depth in the Semiconductor substrate and exempts from the required minimum dimension of programming interference by photoetching process size and storage array and determined.
Optionally, described memory transistor comprises gate dielectric layer, the floating boom that is positioned at successively on the semiconductor, and interlayer insulating film, control gate and dielectric layer, and the side wall that is positioned at interlayer insulating film, control gate and dielectric layer one side are positioned at the sacrifice layer in the side wall outside.
The present invention also provides the formation method of unit, a kind of grid flash memory unit, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, forms two memory transistors;
Semiconductor substrate between two memory transistors of etching forms groove;
Form the tunneling insulation layer that covers described groove and memory transistor;
Deposit spathic silicon layer, described polysilicon layer are filled the space between described groove and the adjacent memory transistor;
The described polysilicon layer of planarization forms erase gate, the shared erase gate of described two memory transistors, and carry out electricity by tunneling insulation layer between erase gate and the memory transistor and isolate.
Further, the manufacture method of described two storage crystal pipe units comprises:
Semiconductor substrate is provided, is formed with gate dielectric layer, first polysilicon layer on the described Semiconductor substrate successively, interlayer insulating film, second polysilicon layer and dielectric layer;
The described dielectric layer of etching, second polysilicon layer and interlayer insulating film, second polysilicon layer forms the control gate of two separation;
Relative sidewall at described dielectric layer, second polysilicon layer and interlayer insulating film forms side wall, forms a sacrifice layer in the side wall outside;
Described first polysilicon layer of etching and gate dielectric layer, first polysilicon layer forms the floating boom of two separation.
Described groove shape for example is an arc or semicircle or trapezoidal.
The degree of depth in the described erase gate embedding Semiconductor substrate is exempted from the required minimum dimension of programming interference by photoetching process size and storage array and is determined.
Adopt the described grid flash memory of present embodiment unit and preparation method thereof, by described erase gate is slipped in the Semiconductor substrate, can be under the situation of same light scale, effectively increase the channel length of device, thereby avoided the short-channel effect of device, improved the interference free performance of memory device array under programming state; Simultaneously since device channel perpendicular to the memory transistor floating boom, hot electron traffic direction and floating boom quadrature in the raceway groove, thus can under low control-grid voltage, realize the programming of device, the programming efficiency of raising device.And under the ever-reduced main trend of device size, the described grid flash memory cellular construction of present embodiment can reduce the area of single flash cell, improves the effect of the density of device.Further, can also reduce the operating voltage of device, improve the device performance of grid flash memory unit.
Description of drawings
Fig. 1 is the structural representation of the unit, grid flash memory unit of prior art;
Fig. 2 be embodiment of the present invention the structural representation of unit, grid flash memory unit;
Fig. 3 is the schematic flow sheet of formation method of the grid flash memory unit of embodiment of the present invention;
Fig. 4 to Figure 11 is the cross-sectional view of the grid flash memory unit formation method of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public concrete enforcement.
Method provided by the invention is not only applicable to unit, grid flash memory unit, is applicable to the general memory device with grid dividing structure yet, is specially adapted to characteristic size at 180nm and following memory device.
Present embodiment provides a kind of grid flash memory unit, and the structure of described grid flash memory unit comprises as shown in Figure 2: Semiconductor substrate 200; Be positioned at two memory transistors 210 on the Semiconductor substrate 200; And between two memory transistors 210, and the erase gate in the embedding Semiconductor substrate 240, described two memory transistors, 210 shared erase gates 240 carry out electricity by tunneling insulation layer 230 between described erase gate 240 and the memory transistor 210 and isolate.
The part that erase gate embeds in the Semiconductor substrate is arc or semicircle or falls trapezoidal or other regular or irregular shapes that the degree of depth in the erase gate embedding Semiconductor substrate is exempted from the required minimum dimension of programming interference by photoetching process size and storage array and determined.
Described memory transistor comprises gate dielectric layer, the floating boom that is positioned at successively on the semiconductor, and interlayer insulating film, control gate and dielectric layer, and the side wall that is positioned at interlayer insulating film, control gate and dielectric layer one side are positioned at the sacrifice layer in the side wall outside.
Adopt the described grid flash memory of present embodiment unit, by described erase gate is slipped in the Semiconductor substrate, can be under the situation of same light scale, effectively increase the channel length of device, thereby avoided the short-channel effect of device, improved the interference free performance of memory device array under programming state; Simultaneously since device channel perpendicular to the memory transistor floating boom, hot electron traffic direction and floating boom quadrature in the raceway groove, thus can under low control-grid voltage, realize the programming of device, the programming efficiency of raising device.And under the ever-reduced main trend of device size, the described grid flash memory cellular construction of present embodiment can reduce the area of single flash cell, improves the effect of the density of device.Further, can also reduce the operating voltage of device, improve the device performance of grid flash memory unit.
Fig. 3 has provided the schematic flow sheet of formation method of the grid flash memory unit of embodiment of the present invention.As shown in Figure 3, execution in step S102 provides Semiconductor substrate, forms two memory transistors on described Semiconductor substrate; Execution in step S103, the Semiconductor substrate between two memory transistors of etching forms groove; Execution in step S104 forms the tunneling insulation layer that covers described groove and memory transistor; Execution in step S105, deposit spathic silicon layer, described polysilicon layer fill the space between described groove and the adjacent memory transistor; Execution in step S106, the described polysilicon layer of planarization forms erase gate, the shared erase gate of described two memory transistors, and carry out electricity by tunneling insulation layer between erase gate and the memory transistor and isolate.
Below in conjunction with drawings and Examples embodiment of the present invention is elaborated.Fig. 4 to Figure 10 is the cross-sectional view according to the formation method of the grid flash memory unit of the first embodiment of the present invention, and described schematic diagram is an example, should excessively not limit the scope of protection of the invention at this.
With reference to Fig. 3 and Fig. 4, execution in step S102 provides Semiconductor substrate 200, forms two memory transistors 210 on described Semiconductor substrate 200.Silicon or SiGe that described Semiconductor substrate 200 can be monocrystalline, polycrystalline or non crystalline structure; It also can be silicon-on-insulator (SOI); The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.Have certain isolation structure on the described Semiconductor substrate 200, can for shallow trench isolation from (STI).
The tunnelling charge carrier of grid flash memory unit can be electronics, also can be the hole, and when the tunnelling charge carrier was electronics, Semiconductor substrate 200 parts of grid flash memory to be formed unit were the P type, can realize by injecting the boron ion.When the tunnelling charge carrier was the hole, Semiconductor substrate 200 parts of grid flash memory to be formed unit were the N type, can realize by injecting phosphonium ion.The memory device of present embodiment adopts electronics as charge carrier.
The method that forms two memory transistors 210 can be any prior art well known to those skilled in the art, clear complete for specification, provide a specific embodiment that forms two memory transistors 210 below, but do not show the method that other form two memory transistors 210 that limits.
The manufacture method of described two storage crystal pipe units comprises:
Semiconductor substrate is provided, is formed with gate dielectric layer, first polysilicon layer on the described Semiconductor substrate successively, interlayer insulating film, second polysilicon layer and dielectric layer;
The described dielectric layer of etching, second polysilicon layer and interlayer insulating film, second polysilicon layer forms the control gate of two separation;
Relative sidewall at described dielectric layer, second polysilicon layer and interlayer insulating film forms side wall, forms a sacrifice layer in the side wall outside;
Described first polysilicon layer of etching and gate dielectric layer, first polysilicon layer forms the floating boom of two separation.
Shown in 5, on described Semiconductor substrate, form gate dielectric layer 310, first polysilicon layer 320 successively with reference to the accompanying drawings, the interlayer insulating film 330 and second polysilicon layer 340.Described gate dielectric layer 310 can be selected silica for use at this for silica, silicon nitride, silicon oxynitride or other high k materials.Its formation method can be the boiler tube thermal oxidation, ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition technologies such as (PECVD), and present embodiment adopts the boiler tube thermal oxidation technology.
On gate dielectric layer 310, form first polysilicon layer 320, as forming floating boom (floating gate).The formation method of polysilicon can be chemical vapor deposition (CVD), low-pressure chemical vapor phase deposition (LPCVD) technology, and present embodiment adopts low-pressure chemical vapor phase deposition technology.First polysilicon layer 320 is mixed, and the tunnelling charge carrier is an electronics in the present embodiment, therefore carries out the N type and mixes, and dopant ion can be pentads such as phosphorus, antimony, arsenic.
After forming first polysilicon layer 320, form interlayer insulating film 330 thereon, described interlayer insulating film 330 can be silica or ONO three-decker or silicon nitride or silicon oxynitride or other high k materials, select the ONO three-decker in the present embodiment for use, it is silica-silicon-nitride and silicon oxide, as the insulating barrier between second polysilicon layer of first polysilicon layer 320 and formation afterwards, this structure has the advantage of little, the low defective of electric leakage.The formation method of silica can be ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition technologies such as (PECVD), the vapor deposition of present embodiment using plasma enhanced chemical.The formation method of silicon nitride can be plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD) technology.Present embodiment adopts low-pressure chemical vapor phase deposition.
Then on interlayer insulating film 330, form second polysilicon layer 340, as forming control gate (controlgate).The formation method of described second polysilicon layer 340 is with reference to the formation method of first polysilicon layer, and present embodiment adopts low-pressure chemical vapor phase deposition technology.Because the tunnelling charge carrier is an electronics in the present embodiment, described second polysilicon layer 340 is carried out the N type mix, dopant ion can be pentads such as phosphorus, antimony, arsenic.
Afterwards, on described second polysilicon layer 340, form dielectric layer 350, be used to protect second polysilicon layer 340.Described dielectric layer for example is the double-decker that oxide layer and silicon nitride layer constitute.
With reference to Fig. 6, described dielectric layer 350, second polysilicon layer 340, interlayer insulating film 330 are carried out etching.At first form photoresist layer on described dielectric layer 350, patterning photoresist layer afterwards forms the shape of control gate, and this technology is conventionally known to one of skill in the art.Lithographic line width is determined by technological requirement.After photoetching is finished, be that mask carries out dry etching to each rete, first polysilicon layer each layer film more than 320 carved by disposable etching with the photoresist.Relevant rete after the etching is followed successively by gate dielectric layer 310, the first polysilicon layers 320, interlayer insulating film 330 ', second polysilicon layer 340 ', dielectric layer 350 '.Through above-mentioned etching, second polysilicon layer 340 ' forms the control gate of the memory transistor of grid flash memory unit, and described two control gates separate, between be used for follow-up formation erase gate.
With reference to Fig. 7, at the relative side formation side wall 360 of described interlayer insulating film 330 ', second polysilicon layer 340 ', dielectric layer 350 ', described side wall 360 for example is oxide layer, silicon nitride double-decker.Afterwards, form a sacrifice layer (Sacrificial Spacer) 370 in the outside of side wall 360.With reference to Fig. 8, with side wall 360, sacrifice layer 370 and dielectric layer 350 ' is mask, etching first polysilicon layer 320 and gate dielectric layer 310, relevant rete after the etching is followed successively by gate dielectric layer 310 ', first polysilicon layer 320 ', interlayer insulating film 330 ', second polysilicon layer 340 ', dielectric layer 350 ', wherein, first polysilicon layer 320 ' is as floating boom, and second polysilicon layer 340 ' is as control gate.
Described floating boom is for separating, between be used for follow-up formation erase gate.
Optionally, described gate dielectric layer 310 also can not carry out etching, that is to say, and be mask with side wall 360, sacrifice layer 370 and second polysilicon layer 340 ', only etching first polysilicon layer 320 is to gate dielectric layer 310.Gate dielectric layer 310 is left to down and carries out etching in the step process.
By the pairing processing step of accompanying drawing 5-7, form two memory transistors 210.
With reference to Fig. 3 and Fig. 9, execution in step S103, the Semiconductor substrate between two memory transistors 210 of etching forms groove 220; The processing step that forms described groove 220 is any known prior art, for example wet method or dry etching.Described groove shape for example is semicircle or falls trapezoidal or other regular or irregular shapes.The degree of depth of described groove is exempted from the required minimum dimension of programming interference by photoetching process size and storage array and is determined.Be used for embedding therein control gate,, reduce the device density of memory cell, improve the performance of grid flash memory unit to increase channel length.
With reference to Fig. 3 and Figure 10, execution in step S104 forms the tunneling insulation layer 230 that covers described groove and memory transistor; Present embodiment is preferably oxide layer (tunnel oxide), and the generation type of described tunneling insulation layer 230 can be plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor phase deposition (LPCVD).Present embodiment is selected low-pressure chemical vapor phase deposition for use.
With reference to Fig. 3 and Figure 11, execution in step S105, deposit spathic silicon, described polysilicon fill the space between described groove and the adjacent memory transistor 210; The technology that forms described polysilicon for example is chemical vapor deposition method.Described polysilicon fills up the space between described groove and the adjacent memory transistor, is used to form erase gate 240.
Afterwards, execution in step S106, the described polysilicon of planarization forms erase gate 240, described two memory transistors, 210 shared erase gates 240, and carry out electricity by tunneling insulation layer 230 between erase gate and the memory transistor 210 and isolate.Described flatening process for example is a CMP (Chemical Mechanical Polishing) process.
The grid flash memory unit that adopts the described method of present embodiment to form by described erase gate is embedded in the Semiconductor substrate, under the situation of same light scale, effectively increases the channel length of device.。And under the ever-reduced main trend of device size, the described grid flash memory cellular construction of present embodiment can reduce the area of single flash cell, improves the effect of the density of device.Further, can also reduce the operating voltage of device, improve the device performance of grid flash memory unit.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (8)
1. grid flash memory unit comprises:
Semiconductor substrate;
Be positioned at two memory transistors on the Semiconductor substrate;
And between two memory transistors, and the erase gate in the embedding Semiconductor substrate, the shared erase gate of described two memory transistors carries out electricity by tunneling insulation layer between described erase gate and the memory transistor and isolates.
2. grid flash memory according to claim 1 unit is characterized in that, the part that erase gate embeds in the Semiconductor substrate is an arc or semicircle or trapezoidal.
3. grid flash memory according to claim 1 unit is characterized in that, the degree of depth in the erase gate embedding Semiconductor substrate is exempted from the required minimum dimension of programming interference by photoetching process size and storage array and determined.
4. grid flash memory according to claim 1 unit, it is characterized in that, described memory transistor comprises gate dielectric layer, the floating boom that is positioned at successively on the semiconductor, interlayer insulating film, control gate and dielectric layer, and the side wall that is positioned at interlayer insulating film, control gate and dielectric layer one side, be positioned at the sacrifice layer in the side wall outside.
5. the formation method of a grid flash memory unit is characterized in that, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, forms two memory transistors;
Semiconductor substrate between two memory transistors of etching forms groove;
Form the tunneling insulation layer that covers described groove and memory transistor;
Deposit spathic silicon layer, described polysilicon layer are filled the space between described groove and the adjacent memory transistor;
The described polysilicon layer of planarization forms erase gate, the shared erase gate of described two memory transistors, and carry out electricity by tunneling insulation layer between erase gate and the memory transistor and isolate.
6. the formation method of grid flash memory according to claim 5 unit is characterized in that, described groove shape for example is an arc or semicircle or trapezoidal.
7. the formation method of grid flash memory according to claim 5 unit is characterized in that, the degree of depth in the erase gate embedding Semiconductor substrate is exempted from the required minimum dimension of programming interference by photoetching process size and storage array and determined.
8. the formation method of grid flash memory according to claim 5 unit is characterized in that, the manufacture method of described two storage crystal pipe units comprises:
Semiconductor substrate is provided, is formed with gate dielectric layer, first polysilicon layer on the described Semiconductor substrate successively, interlayer insulating film, second polysilicon layer and dielectric layer;
The described dielectric layer of etching, second polysilicon layer and interlayer insulating film, second polysilicon layer forms the control gate of two separation;
Relative sidewall at described dielectric layer, second polysilicon layer and interlayer insulating film forms side wall, forms a sacrifice layer in the side wall outside;
Described first polysilicon layer of etching and gate dielectric layer, first polysilicon layer forms the floating boom of two separation.
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