CN103515391A - Nonvolatile memory unit and manufacturing method thereof - Google Patents
Nonvolatile memory unit and manufacturing method thereof Download PDFInfo
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- CN103515391A CN103515391A CN201210222508.7A CN201210222508A CN103515391A CN 103515391 A CN103515391 A CN 103515391A CN 201210222508 A CN201210222508 A CN 201210222508A CN 103515391 A CN103515391 A CN 103515391A
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Abstract
The invention provides a nonvolatile memory unit and a manufacturing method of the nonvolatile memory unit. The nonvolatile memory unit comprises a semiconductor substrate, a floating grid, a control grid, a tunneling oxidation layer and a polycrystalline silicon interlevel dielectric film. The floating grid is provided with a sharp end and a blunt end, the sharp end is embedded into the semiconductor substrate, the control grid is arranged on the floating grid, the tunneling oxidation layer is arranged between the floating grid and the semiconductor substrate, and the polycrystalline silicon interlevel dielectric film is arranged between the floating grid and the control grid. The nonvolatile memory unit can greatly improve the programmed operating speed of a memory under the condition of identical tunneling oxidation layer thickness, or the nonvolatile memory unit can achieve the programmed operation with small operating voltages, and the reliability of elements can be simultaneously achieved.
Description
Technical field
The present invention relates to a kind of Nonvolatile memery unit and manufacture method thereof, particularly fast Nonvolatile memery unit and the manufacture method thereof of a kind of service speed.
Background technology
Nonvolatile memory (Non-volatile memory, NVRAM) refers to after electric current is turned off, the computer memory that stored data can not disappear.In recent years, nonvolatile memory application is more and more extensive, especially at flash memory, has been widely used in various portable type electronic product.Nonvolatile memory main development direction comprises raising capacity density, speeds service speed and promote reliability at present.Yet, when continuing micro with raising memory span density along with component size, for example the thickness of the tunnel oxide of the nonvolatile memory of flash memory (tunneling oxide) also decreases, when tunnel oxide is less than 6nm, the data storage capability of known flash memory can seriously be lost, the storage electric charge that reason is attributed in electric charge storage layer can move horizontally (lateral migration), as long as therefore have a leakage path in tunnel oxide, can produce serious loss of charge.Therefore, how taking into account nonvolatile memory high capacity density, service speed and reliability, is the challenge that current nonvolatile memory faces.
Therefore, in this technical field, have and need a kind of Nonvolatile memery unit, to meet the demand and to overcome the shortcoming of known technology.
Summary of the invention
In view of this, the defect existing for solving prior art, one embodiment of the invention provides a kind of Nonvolatile memery unit, and above-mentioned Nonvolatile memery unit comprises semiconductor substrate; One floating grid, above-mentioned floating grid has a most advanced and sophisticated and blunt end, wherein above-mentioned most advanced and sophisticated embedding in above-mentioned semiconductor substrate; One controls grid, is arranged on above-mentioned floating grid; One tunnel oxide, is arranged between above-mentioned floating grid and above-mentioned semiconductor substrate; One inter polysilicon dielectric film, is arranged between above-mentioned floating grid and above-mentioned control grid.
Another embodiment of the present invention provides a kind of manufacture method of Nonvolatile memery unit, comprises semiconductor substrate is provided; In above-mentioned semiconductor substrate, form the isolated thing of a plurality of shallow trenchs that extend along a first direction; On above-mentioned semiconductor substrate, form a plurality of hard mask patterns that extend along a second direction that is different from above-mentioned first direction; Carry out an etch process, remove the above-mentioned semiconductor substrate of part not covered by the isolated thing of above-mentioned a plurality of shallow trenchs and above-mentioned a plurality of hard mask pattern, with in above-mentioned middle formation one groove; In above-mentioned groove, compliance forms a tunnel oxide; On above-mentioned tunnel oxide, form a floating grid, and insert in above-mentioned groove; On above-mentioned floating grid, sequentially form an inter polysilicon dielectric film and and control grid layer; The above-mentioned inter polysilicon dielectric film of patterning and above-mentioned control grid layer, an inter polysilicon dielectric film pattern and that covers above-mentioned floating grid to form is controlled gate pattern.
The Nonvolatile memery unit of the embodiment of the present invention can greatly promote the programming operations speed of memory under identical tunnel oxide thickness condition, or the Nonvolatile memery unit of the embodiment of the present invention can complete programming operations by less operating voltage, and can take into account the reliability of element simultaneously.
Accompanying drawing explanation
Fig. 1 a ~ 7a is the vertical view of the manufacture method of the Nonvolatile memery unit of demonstration one embodiment of the invention.
Fig. 1 b ~ 7b is respectively along the profile of the A-A ' tangent line of Fig. 1 a ~ 7a, the generalized section of manufacture method one position of the Nonvolatile memery unit of its demonstration one embodiment of the invention.
Fig. 1 c ~ 7c is respectively along the profile of the B-B ' tangent line of Fig. 1 a ~ 7a, the generalized section of the another location of the manufacture method of the Nonvolatile memery unit of its demonstration one embodiment of the invention.
Fig. 2 d ~ 7d is respectively along the profile of the C-C ' tangent line of Fig. 2 a ~ 7a, the generalized section of the another position of the manufacture method of the Nonvolatile memery unit of its demonstration one embodiment of the invention.
Fig. 8 a, Fig. 8 b show the generalized section of the Nonvolatile memery unit of one embodiment of the invention, and it shows respectively the Nonvolatile memery unit schematic diagram that electronics moves during programming operations and erase operation for use of one embodiment of the invention.
[main description of reference numerals]
500 ~ Nonvolatile memery unit;
200 ~ semiconductor substrate;
201 ~ end face;
202 ~ pad oxide layer;
202a ~ pad oxide layer pattern;
204 ~ pad silicon nitride layer;
205 ~ isolated groove;
206 ~ shallow trench completely cuts off thing;
212,236 ~ photoresistance pattern;
214 ~ floating grid groove;
215 ~ bottom;
216a, 216b ~ sidewall;
217 ~ opening;
218 ~ tunnel oxide;
220 ~ floating grid;
222 ~ blunt end;
230 ~ inter polysilicon dielectric material;
230a ~ inter polysilicon dielectric film;
232 ~ polycrystalline silicon material;
232a ~ control grid;
234 ~ silicon nitride layer;
234a ~ silicon nitride pattern;
240 ~ gate stack structure;
242 ~ oxide layer;
244 ~ nitration case;
246 ~ clearance wall;
248 ~ source/drain doping region;
250 ~ lightly-doped source/drain doping region;
262,264 ~ arrow;
270 ~ tip;
300,302 ~ direction;
H, H ~ degree of depth;
A1 ~ angle.
Embodiment
With each embodiment, describe and be accompanied by below the example of accompanying drawing explanation in detail, as reference frame of the present invention.In accompanying drawing or specification description, similar or identical part is all used identical Reference numeral.And in the accompanying drawings, the shape of embodiment or thickness can expand, and to simplify or convenient sign.Moreover in accompanying drawing, the part of each element will be it should be noted that the element that does not illustrate or describe in figure to describe respectively explanation, be form known to a person of ordinary skill in the art in affiliated technical field.
Fig. 1 a ~ 7a is the vertical view of the manufacture method of the Nonvolatile memery unit 500 of demonstration one embodiment of the invention.Fig. 1 b ~ 7b is respectively along the profile of the A-A ' tangent line of Fig. 1 a ~ 7a, it shows the generalized section of manufacture method one position (along the channel direction of nonvolatile memory, simultaneously along direction 302) of the Nonvolatile memery unit 500 of one embodiment of the invention.Fig. 1 c ~ 7c is respectively along the profile of the B-B ' tangent line of Fig. 1 a ~ 7a, the generalized section of the another location of the manufacture method of the Nonvolatile memery unit 500 of its demonstration one embodiment of the invention (along bit line (control grid) bearing of trend of nonvolatile memory, simultaneously along direction 300).Fig. 2 d ~ 7d is respectively along the profile of the C-C ' tangent line of Fig. 2 a ~ 7a, the generalized section of the another position of the manufacture method of the Nonvolatile memery unit 500 of its demonstration one embodiment of the invention.The Nonvolatile memery unit 500 of the embodiment of the present invention utilizes floating grid (floating gate), inter polysilicon dielectric film (inter-poly oxide film) and controls the stacking gate stack structure forming of grid (control gate), with floating grid, stores single bit (single bit) data.And, the floating grid of the Nonvolatile memery unit 500 of the embodiment of the present invention has a tip, embed in semiconductor substrate, during sequencing or erase operation for use, the tip of floating grid can have larger electric field density, thereby can promote programming operations and the erase operation for use speed of memory and take into account the reliability of element simultaneously.
Please refer to Fig. 1 a ~ 1c, first, provide semiconductor substrate 200.In an embodiment of the present invention, semiconductor substrate 200 can be silicon substrate.In other embodiments, can utilize SiGe (SiGe), bulk semiconductor (bulk semiconductor), strain semiconductor (strained semiconductor), compound semiconductor (compound semiconductor), silicon-on-insulator (silicon on insulator, or other conventional semiconductor substrates SOI).The implantable p-type of semiconductor substrate 200 or N-shaped admixture, need to change its conduction type for design.Afterwards, can utilize chemical vapour deposition technique (CVD) on semiconductor substrate 200, to cover a pad oxide layer 202 and a pad silicon nitride layer 204, pad oxide layer 202 and pad silicon nitride layer 204 are common as the follow-up etch hard mask (hard mask) that is formed at the isolated groove 205 in semiconductor substrate 200, in order to the damage of avoiding during groove etching process, semiconductor substrate 200 surfaces being caused.The stretching stress that above-mentioned pad oxide layer 202 causes in order to discharge pad silicon nitride layer 204, avoids stress to cause the defect of semiconductor substrate 200.
Then, refer again to Fig. 1 a ~ 1c, can utilize photoetching and etch process, patterning pad oxide layer 202 and pad silicon nitride layer 204, and define the formation position of isolated groove 205.Then, can carry out an anisotropic etch process, using the pad oxide layer 202 of patterning and pad silicon nitride layer 204 as etch hard mask, remove the part semiconductor substrate 200 that the pad oxide layer 202 that is not patterned and pad silicon nitride layer 204 cover, to form a plurality of isolated grooves 205 in semiconductor substrate 200.Then, can utilize thermal oxidation mode, form a ditch slot liner pad oxide (figure does not show) on the madial wall of isolated groove 205, it is in order to improve the interior side-wall surface of isolated groove 205.Afterwards, can utilize chemical vapour deposition technique (CVD) to form oxide (figure does not show), to fill above-mentioned isolated groove 205.The person of connecing, can utilize cmp planarization (CMP) technique with the above-mentioned oxide of etch-back, to form along direction 302, extends and the spaced isolated thing (STI) 206 of a plurality of shallow trenchs.Finally, can utilize wet process, remove pad oxide layer 202 and the pad silicon nitride layer 204 of residual patterning.
Below utilize the generation type of Fig. 2 a ~ 2d, Fig. 3 a ~ 3d explanation floating grid groove.Please refer to Fig. 2 a ~ 2d, then, can utilize physical vapour deposition (PVD) (PVD) method or chemical vapour deposition (CVD) (CVD) method, comprehensive covering one pad silicon nitride layer (figure do not show), above-mentioned pad silicon nitride layer is in order to as the follow-up etch hard mask that is formed at the floating grid groove in semiconductor substrate 200 of definition.Then, can utilize light blockage coating and photoetching process, on above-mentioned pad silicon nitride layer, form along direction 300 and extend and spaced a plurality of photoresistance patterns 212, to define the formation position of etch hard mask pattern.In an embodiment of the present invention, direction 300 and direction 302 are different directions, and for example direction 300 can be orthogonal with direction 302.Then, the photoresistance pattern 212 of usining carries out an anisotropic etch process as etching mask, remove the pad silicon nitride layer and the pad oxide layer 202 under it that by photoresistance pattern 212, are not covered, to form a plurality of pad silicon nitride patterns 210, and form pad oxide layer pattern 202a simultaneously.Pad silicon nitride pattern 210 defines the follow-up formation position that is formed at the floating grid groove in semiconductor substrate 200.
Please refer to Fig. 3 a ~ 3d, then, the pad silicon nitride pattern 210 of usining carries out an etch process as etch hard mask, remove by pad silicon nitride pattern 210, do not covered part semiconductor substrate 200, to form a plurality of floating grid grooves 214 in semiconductor substrate 200.As shown in Figure 3 b, in an embodiment of the present invention, can, by the time of controlling etch process, make floating grid groove 214 can there is a profile wide at the top and narrow at the bottom.Meaning is the area that the area of a bottom 215 of floating grid groove 214 can be less than an opening 217 of floating grid groove 214.In an embodiment of the present invention, floating grid groove 214 extends to bottom 215 sidewall 216a and the angle a1 scope between 216b for being greater than 0 degree and being less than 90 degree from opening 217.In an embodiment of the present invention, wherein a section shape (as shown in Figure 3 b) of floating grid groove 214 can be V-type.Height drop-out value through semiconductor substrate 200 as shown in Figure 3 c after etch process equals the depth H of floating grid groove 214 as shown in Figure 3 b.Therefore,, in profile as shown in Figure 3 c, the end face of the isolated thing 206 of shallow trench can be higher than the end face of semiconductor substrate 200.Then, can utilize photoresistance to divest (PR stripping) technique, remove the photoresistance pattern 212 photoresistance patterns as shown in Fig. 2 a ~ 2d.Recycling wet process, removes the pad silicon nitride pattern 210 as shown in Fig. 2 a ~ 2d.
Below utilize the generation type of Fig. 4 a ~ 4d explanation tunnel oxide and floating grid (floating gate, FG).Please refer to Fig. 4 a ~ 4d, then, can utilize thermal oxidation (thermal oxidation) mode, on the madial wall of floating grid groove 214, form a tunnel oxide 218.Then, can utilize chemical vapour deposition technique (CVD), comprehensive formation one polycrystalline silicon material, covers shallow trench isolated thing 206, pad oxide layer pattern 202a and tunnel oxide 218, and fills floating grid groove 214.Afterwards, can carry out for example flatening process of chemical mechanical milling method (CMP), with the surface of planarization polycrystalline silicon material until pad oxide layer pattern 202a come out.Through after flatening process, form a plurality of floating grids 220.In an embodiment of the present invention, floating grid 220 has most advanced and sophisticated 270 and one blunt end 222.As shown in Figure 4 b, the tip 270 of floating grid 220 embeds in semiconductor substrate 200, meaning is that the tip 270 of floating grid 220 is arranged in floating grid groove 214, and the blunt end 222 of floating grid 220 can protrude from because the flatening process of above-mentioned polycrystalline silicon material stops at pad oxide layer pattern 202a an end face 201 of semiconductor substrate 200.In an embodiment of the present invention, floating grid 220 comprises the first half 220a and the latter half 220b, because floating grid 220 forms in the floating grid groove 214 of tool profile wide at the top and narrow at the bottom, therefore the shape of floating grid 220 also can have profile wide at the top and narrow at the bottom, for instance, the shape of floating grid 220 can be wedge shape, trapezoidal or taper.Also therefore, in an embodiment of the present invention, the volume of the first half 220a of floating grid 220 can be greater than the volume of its latter half 220b.As shown in Fig. 4 a ~ 4d, floating grid 220 can be spaced by pad oxide layer pattern 202a and the isolated thing 206 of shallow trench.
Below utilize the generation type of Fig. 5 a ~ 5d, Fig. 6 a ~ 6d explanation inter polysilicon dielectric film and control grid.Please refer to Fig. 5 a ~ 5d, then, can utilize chemical vapour deposition (CVD) (CVD) method or ald (ALD) method, comprehensive formation one inter polysilicon dielectric material 230.In an embodiment of the present invention, inter polysilicon dielectric material 230 can be an oxide layer-nitride layer-oxide layer (ONO) stacked structure, sequentially comprises from below to up oxide layer 224, nitration case 226 and oxide layer 228.In the present invention, other are executed in example, inter polysilicon dielectric material 230 can be single layer structure or the multi-layer compound structure of other high-ks (high-k) dielectric material, in order to increase the coupling efficiency (coupling ratio) of follow-up control grid formed thereon and the floating grid 220 under it.Then, can utilize chemical vapour deposition technique (CVD), comprehensive formation one polycrystalline silicon material 232, covers inter polysilicon dielectric material 230.Polycrystalline silicon material 234 is in order to form follow-up control grid.Afterwards, can utilize physical vapour deposition (PVD) (PVD) method or chemical vapour deposition (CVD) (CVD) method, comprehensive covering one silicon nitride layer 234, above-mentioned silicon nitride layer 234 is in order to the etch hard mask of the inter polysilicon dielectric film as the follow-up formation of definition and control grid.
Please refer to Fig. 6 a ~ 6d, then, can utilize light blockage coating and photoetching process, on above-mentioned silicon nitride layer 234, form along direction 300 and extend and spaced a plurality of photoresistance patterns 236, to define the formation position of silicon nitride pattern 234a.Then, with photoresistance pattern 236, as etching mask, carry out an anisotropic etch process, remove the silicon nitride layer 234 not covered by photoresistance pattern 236, to form a plurality of silicon nitride pattern 234a.Silicon nitride pattern 234a defines the follow-up formation position that is formed at the inter polysilicon dielectric film on floating grid 220 and controls grid.
Refer again to Fig. 6 a ~ 6d, then, with photoresistance pattern 236 and silicon nitride pattern 234a as etch hard mask, carry out an anisotropic etch process, remove be not nitrided that silicon pattern 234a covers part polycrystalline silicon material 232 and inter polysilicon dielectric material 230, until expose pad oxide layer pattern 202a.Through after anisotropic etch process, form respectively the inter polysilicon dielectric film 230a being stacked on floating grid 220 and control grid 232a.As shown in Figure 6 b, inter polysilicon dielectric film 230a and control grid 232a extend and arrange along direction 300, therefore along direction 300, different floating grid 220 are set and share same control grid 232a.And inter polysilicon dielectric film 230a and control grid 232a are greater than the width of floating grid 220 along the width of direction 302.Therefore, inter polysilicon dielectric film 230a covers the part pad oxide layer pattern 202a adjacent with floating grid 220.In other words, inter polysilicon dielectric film 230a and control grid 232a are all greater than floating grid 220 along the projected area of semiconductor substrate 200 normal directions along the projected area of semiconductor substrate 200 normal directions.As shown in Figure 6 b, floating grid 220 with and on inter polysilicon dielectric film 230a and control grid 232a and can jointly form a gate stack structure 240.Then, can utilize photoresistance to divest (PR stripping) technique, remove photoresistance pattern 236.
Below utilize the generation type of Fig. 7 a ~ 7d explanation clearance wall and source doping region and a drain doping region.Please refer to Fig. 7 a ~ 7d, then, can utilize chemical vapour deposition (CVD) (CVD) method, ald (ALD) method, physical vapour deposition (PVD) (PVD) method or other applicable technique sequentially to form an oxide layer and mononitride layer (figure does not show).Afterwards, carry out an anisotropic etch process, remove the oxide layer and the nitride layer that are positioned at directly over semiconductor substrate 200, until expose silicon nitride pattern 234a.Now residue in a part of oxide layer 242 in the opposing sidewalls of gate stack structure 240 and nitration case 244 thereby form a pair of clearance wall 246.
Refer again to Fig. 7 a ~ 7d, then, take gate stack structure 240 and clearance wall 246 carries out a doping process, formation source/drain doping region 248 in not by the semiconductor substrate 200 of gate stack structure 240 and clearance wall 246 coverings for mask.Then, then carry out another doping process, in the semiconductor substrate 200 of the sidewall 216a close to floating grid groove 214 and 216b, form lightly-doped source/drain doping region 250, lightly-doped source/drain doping region 250 is overlapping with part source/drain doping region 248.In an embodiment of the present invention, the degree of depth h of source/drain doping region 248 and lightly-doped source/drain doping region 250 is less than the depth H of floating grid groove 214.Through after above-mentioned technique, complete the Nonvolatile memery unit 500 of one embodiment of the invention.The Nonvolatile memery unit 500 of one embodiment of the invention comprises semiconductor substrate 200; One floating grid 220, has most advanced and sophisticated 270 and one blunt end 222, wherein most advanced and sophisticated 270 embeds in semiconductor substrate 200; One controls grid 232a, is arranged on floating grid 220; One tunnel oxide 218, is arranged between floating grid 220 and semiconductor substrate 200; One inter polysilicon dielectric film 230a, is arranged at floating grid 220 and controls between grid 232a.
Fig. 8 a, Fig. 8 b show the generalized section of the Nonvolatile memery unit 500 of one embodiment of the invention, and it shows respectively Nonvolatile memery unit 500 schematic diagram that electronics moves during programming operations (programming operation) and erase operation for use (erasing operation) of one embodiment of the invention.The programming operations of Nonvolatile memery unit 500 and erase operation for use mode utilize Fu Le-Nuo De get Han to wear tunnel (Fowler-Nordheim tunneling, F-N tunneling) mode, by electronic injection floating grid (FG) with shift out floating grid (FG).
As shown in Figure 8 a, Nonvolatile memery unit 500 utilize Fu Le-Nuo Dehan to wear tunnel (F-Ntunneling) programming operations mode to comprise and apply a positive voltage to controlling grid 232a, semiconductor substrate 200 (base terminal) is applied to a negative voltage, and source/drain doping region 248 is electrical suspension joint (floating), so that utilizing Fu Le-Nuo get Han to wear tunnel mode, the electronics of semiconductor substrate 200 (base terminal) injects floating grid (FG) 220 through tunnel oxide 218, so that a bit is stored in floating grid 220, complete programming operations.Specifically, in tip 270 embedding semiconductor substrates 200 due to floating grid 220, during programming operations, the electric field density of most advanced and sophisticated 270 positions is larger, so electrons injects floating grid 220 from semiconductor substrate 200 (base terminal) through the minimum area portions of tunnel oxide 218 according to the position shown in arrow 262.Compared to known Nonvolatile memery unit (it is a plane that floating grid is stacked in Qie Qi bottom surface, semiconductor substrate top), the Nonvolatile memery unit of the embodiment of the present invention can greatly promote the programming operations speed of memory under identical tunnel oxide thickness condition, or the Nonvolatile memery unit of the embodiment of the present invention can be less operating voltage (controlling the voltage difference of grid and base terminal) complete programming operations, and can take into account the reliability of element simultaneously.
As shown in Figure 8 b, Nonvolatile memery unit 500 utilize Fu Le-Nuo get Han to wear tunnel (F-Ntunneling) erase operation for use mode to comprise semiconductor substrate 200 (base terminal) is applied to a positive voltage, and controlling grid 232a and source/drain doping region 248 is electrical suspension joint (floating), so that the electronics that floating grid (FG) stores utilizes Fu Le-Nuo get Han to wear tunnel mode via injecting semiconductor substrate 200 (base terminal) through tunnel oxide 218, the bit that is stored in floating grid (FG) to erase, completes erase operation for use.Similarly, in tip 270 embedding semiconductor substrates 200 due to floating grid 220, during erase operation for use, the electric field density of most advanced and sophisticated 270 positions is larger, so electrons injects semiconductor substrate 200 (base terminal) from floating grid 220 through the minimum area portions of tunnel oxide 218 according to the position shown in arrow 264.Compared to known Nonvolatile memery unit (it is a plane that floating grid is stacked in Qie Qi bottom surface, semiconductor substrate top), the Nonvolatile memery unit of the embodiment of the present invention can greatly promote the erase operation for use speed of memory under identical tunnel oxide thickness condition, or the Nonvolatile memery unit of the embodiment of the present invention can be less operating voltage (controlling the voltage difference of grid and base terminal) complete erase operation for use, and can take into account the reliability of element simultaneously.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is when defining and be as the criterion depending on accompanying claim.
Claims (14)
1. a Nonvolatile memery unit, comprising:
Semiconductor substrate;
One floating grid, this floating grid has a most advanced and sophisticated and blunt end, and wherein this tip embeds in this semiconductor substrate;
One controls grid, is arranged on this floating grid;
One tunnel oxide, is arranged between this floating grid and this semiconductor substrate; And
One inter polysilicon dielectric film, is arranged between this floating grid and this control grid.
2. Nonvolatile memery unit as claimed in claim 1, wherein this floating grid comprises a first half and a latter half, wherein the volume of this first half is greater than the volume of this latter half.
3. Nonvolatile memery unit as claimed in claim 1, wherein this floating grid is wedge shape, trapezoidal or taper.
4. Nonvolatile memery unit as claimed in claim 1, wherein this semiconductor substrate comprises a groove, this tip of this floating grid is arranged in this groove.
5. Nonvolatile memery unit as claimed in claim 4, wherein this blunt end of this floating grid protrudes from a surface of this semiconductor substrate.
6. Nonvolatile memery unit as claimed in claim 4, wherein the area of a bottom of this groove is less than the area of an opening of this groove.
7. Nonvolatile memery unit as claimed in claim 4, wherein a section shape of this groove is V-type.
8. Nonvolatile memery unit as claimed in claim 1, wherein this floating grid has an end face and pair of sidewalls respect to one another, and the angle of this oppose side wall and this end face is all greater than 0 degree and is less than 90 degree.
9. Nonvolatile memery unit as claimed in claim 1, wherein this floating grid, this inter polysilicon dielectric film and this control that grid is common forms a gate stack structure.
10. Nonvolatile memery unit as claimed in claim 9, also comprises:
A pair of clearance wall, is formed in the opposing sidewalls of this gate stack structure;
One source pole doped region and a drain doping region, be formed in this semiconductor substrate, and close to this floating grid, embed this part of this semiconductor substrate.
The manufacture method of 11. 1 kinds of Nonvolatile memery units, comprises the following steps:
Semiconductor substrate is provided;
In this semiconductor substrate, form the isolated thing of a plurality of shallow trenchs that extend along a first direction;
On this semiconductor substrate, form a plurality of hard mask patterns that extend along a second direction that is different from this first direction;
Carry out an etch process, remove not by this semiconductor substrate of part of the isolated thing of described a plurality of shallow trenchs and described a plurality of hard mask pattern coverings, to form a groove in this semiconductor substrate;
In this groove, compliance forms a tunnel oxide;
On this tunnel oxide, form a floating grid, and insert in this groove;
On this floating grid, sequentially form an inter polysilicon dielectric film and and control grid layer; And
This inter polysilicon dielectric film of patterning and this control grid layer, an inter polysilicon dielectric film pattern and that covers this floating grid to form is controlled gate pattern.
The manufacture method of 12. Nonvolatile memery units as claimed in claim 11, wherein the area of a bottom of this groove is less than the area of an opening of this groove.
The manufacture method of 13. Nonvolatile memery units as claimed in claim 11, wherein a section shape of this groove is V-type.
The manufacture method of 14. Nonvolatile memery units as claimed in claim 11, wherein this floating grid, this inter polysilicon dielectric film and this control grid form a gate stack structure jointly, and the manufacture method of this Nonvolatile memery unit, also comprises:
In the opposing sidewalls of this gate stack structure, form a pair of clearance wall;
Carry out a doping process, in this semiconductor substrate, form one source pole doped region and a drain doping region, and this source doping region and this drain doping region are respectively close to the sidewall of this groove.
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Application publication date: 20140115 |