CN112018119A

CN112018119A - Semiconductor structure and forming method thereof

Info

Publication number: CN112018119A
Application number: CN201910470606.4A
Authority: CN
Inventors: 成明
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-05-31
Filing date: 2019-05-31
Publication date: 2020-12-01

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a base, wherein the base comprises a substrate, and a discrete stacked gate structure and a selection gate which are positioned on the substrate, and side wall layers are formed on the side walls of the stacked gate structure and the selection gate; forming an interlayer dielectric layer covering the stacked gate structure and the selection gate; etching the interlayer dielectric layer between the stacked gate structure and the select gate, or etching the interlayer dielectric layer and the side wall layer to form an opening; a low-K dielectric layer is formed in the opening. Compared with the interlayer dielectric layer and the side wall layer, the dielectric constant of the low-K dielectric layer is lower, and the capacitance coupling effect between the stack gate structure and the selection gate is reduced according to the capacitance calculation formula C which is S/d, so that the programming voltage and the erasing voltage are reduced, the programming efficiency and the erasing efficiency are improved, and the power consumption of the device is reduced.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

In a semiconductor memory device, a flash memory is a non-volatile memory, and has the advantages of being capable of performing operations such as data storage, reading, and erasing for many times, and the stored data will not disappear after power is turned off. Therefore, in recent years, flash memories have been widely used in consumer electronics products, such as: digital cameras, digital video cameras, mobile phones, laptop computers, walkman, etc.

A conventional flash memory has a floating gate and a control gate made of doped polysilicon, the Floating Gate (FG) and the Control Gate (CG) are separated by a dielectric layer, and the floating gate and a substrate are separated by a tunnel oxide layer. When the flash memory is used for erasing data, the number of electrons discharged from the floating gate is not easy to control, so that the floating gate is easy to discharge excessive electrons to have positive charges, which is called overerase. When the overerase phenomenon is too severe, even the channel under the floating gate is continuously in a conducting state when the control gate is not under voltage, resulting in erroneous determination of data. In order to avoid the problem of data misjudgment caused by over-erase phenomenon during erasing of the flash memory, a select gate may be additionally disposed on the sidewall of the control gate and the floating gate and above the substrate to form a Separate Gate (SG).

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises a substrate, and a discrete stacked gate structure and a selection gate which are positioned on the substrate, and side wall layers are formed on the side walls of the stacked gate structure and the selection gate; forming an interlayer dielectric layer covering the stacked gate structure and the selection gate; etching the interlayer dielectric layer between the stacked gate structure and the select gate, or etching the interlayer dielectric layer and the side wall layer to form an opening; a low-K dielectric layer is formed in the opening.

Optionally, the step of forming an interlayer dielectric layer includes: forming an interlayer dielectric material layer covering the stacked gate structure and the selection gate; and flattening the interlayer dielectric material layer to form the interlayer dielectric layer.

Optionally, the step of forming the opening includes: forming a shielding layer on the interlayer dielectric layer, wherein the shielding layer exposes the interlayer dielectric layer and the side wall layer between the stacked gate structure and the selection gate; and etching the interlayer dielectric layer or the side wall layer or the interlayer dielectric layer and the side wall layer between the stack grid structure and the selection grid by taking the shielding layer as a mask to form the opening.

Optionally, the size of the opening is 50 nm to 200 nm in a direction perpendicular to the extending direction of the stacked gate structure.

Optionally, the opening is formed by etching with a dry etching process.

Optionally, the material of the low-K dielectric layer includes: silicon oxide doped with C, B or P, or SiOCH.

Optionally, the step of forming a low-K dielectric layer in the opening includes: forming a low-K dielectric material layer covering the opening; and removing the low-K dielectric material layer exposed out of the opening, wherein the low-K dielectric material layer remained in the opening is used as a low-K dielectric layer.

Optionally, a chemical mechanical planarization process is used to remove the low-K dielectric material layer exposing the opening.

Optionally, a chemical vapor deposition process is used to form the low-K dielectric material layer in the opening.

Optionally, the stacked gate structure includes: the gate-to-gate structure comprises a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer; the floating grid is doped with N-type ions, and the selection grid is doped with P-type ions.

Optionally, the substrate is a substrate with a fin portion; the stacked gate structure and the selection gate both cross the fin portion and cover part of the top wall and part of the side walls of the fin portion.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the stacked gate structure is positioned on the substrate; the selection gate is positioned on the substrate and positioned on the side edge of the stacked gate structure; the side wall layer is positioned on the side walls of the stacked gate structure and the selection gate; the interlayer dielectric layer is positioned on the stacked gate structure, the selection gate and the substrate exposed from the stacked gate structure and the selection gate; and the low-K dielectric layer is positioned between the stacked gate structure and the selection gate.

Optionally, the low-K dielectric layer is in contact with the stacked gate structure, or in contact with the select gate, or in contact with both the stacked gate structure and the select gate.

Optionally, the low-K dielectric layer is located in an interlayer dielectric layer between the stacked gate structure and the select gate.

Optionally, the low-K dielectric layer is located between the sidewall layers and between the stacked gate structure and the select gate.

Optionally, the size of the low-K dielectric layer in a direction perpendicular to the extension direction of the stacked gate structure is 50 nm to 200 nm.

Optionally, the material of the low-K dielectric layer includes: SiOCH, or silicon oxide doped with C, B or P.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the embodiment of the invention, the interlayer dielectric layer between the stacked gate structure and the selection gate or the interlayer dielectric layer and the side wall layer is etched, an opening is formed between the stacked gate structure and the selection gate, and a low-K dielectric layer is formed in the opening. Compared with the interlayer dielectric layer and the side wall layer, the dielectric constant of the low-K dielectric layer is lower, and the capacitance coupling effect between the stack gate structure and the selection gate is reduced according to the capacitance calculation formula C which is S/d, so that the programming voltage and the erasing voltage are reduced, the programming efficiency and the erasing efficiency are improved, and the power consumption of the device is reduced.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

fig. 2 to fig. 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for poor device performance is analyzed in combination with a schematic structure diagram of a semiconductor structure.

Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.

As shown in fig. 1, providing a base, where the base includes a substrate 1, a stacked gate structure 2 located on the substrate 1, and a select gate 3 located at a side of the stacked gate structure 2; wherein the stacked gate structure 2 includes: the tunnel oxide layer 21, the floating gate 22 on the tunnel oxide layer 21, the inter-gate dielectric layer 23 on the floating gate 22, and the control gate 24 on the inter-gate dielectric layer 23.

As the device size shrinks, the distance between the floating gate 22 and the select gate 3 becomes smaller, and compared with the capacitance between the control gate 24, the intergate dielectric layer 23 and the floating gate 22, and the capacitance between the floating gate 22, the tunnel oxide layer 21 and the substrate 1, the capacitive coupling effect between the floating gate 22 and the select gate 3 is not negligible, and the capacitive coupling effect between the floating gate 22 and the select gate 3 is too large, which easily causes the increase of the programming voltage and the erasing voltage, reduces the programming and erasing efficiency, causes the power consumption of the device to increase, and reduces the reading speed of the flash memory.

In order to solve the technical problem, an embodiment of the present invention provides a base, where the base includes a substrate, and a separate stacked gate structure and a select gate that are located on the substrate, and side wall layers are formed on sidewalls of the stacked gate structure and the select gate; forming an interlayer dielectric layer covering the stacked gate structure and the selection gate; etching the interlayer dielectric layer between the stacked gate structure and the select gate, or etching the interlayer dielectric layer and the side wall layer to form an opening; a low-K dielectric layer is formed in the opening.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Referring to fig. 2 to 6, a base is provided, the base includes a substrate 100, and a discrete stacked gate structure 106 (shown in fig. 6) and a select gate 107 (shown in fig. 6) that are located on the substrate 100, and sidewall layers 111 (shown in fig. 6) are formed on sidewalls of the stacked gate structure 106 and the select gate 107.

The substrate provides a process foundation for subsequently forming the semiconductor structure.

Specifically, the step of forming the substrate includes:

as shown in fig. 2, a substrate 100, a tunnel oxide layer 101 on the substrate 100, a first polysilicon layer 102 on the tunnel oxide layer 101, and an inter-gate dielectric layer 103 on the first polysilicon layer 102 are provided.

In this embodiment, taking the formed semiconductor structure as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) as an example, correspondingly, the substrate 100 is a planar substrate. In other embodiments, the formed semiconductor structure may be a fin field effect transistor (FinFET), and the substrate may be a substrate having a fin portion.

In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

The tunnel oxide layer 101 is used to electrically isolate the substrate 100 from a subsequently formed floating gate and a select gate.

The tunneling oxide layer 101 is made of a dielectric material.

Specifically, the material of the tunnel oxide layer 101 includes one or both of silicon oxide and silicon nitride. In this embodiment, the tunneling oxide layer 101 is made of silicon oxide.

The first polysilicon layer 102 provides for the subsequent formation of floating gates and select gates.

In this embodiment, the material of the first polysilicon layer 102 is polysilicon.

It should be noted that after the first polysilicon layer 102 is formed, N-type ions are doped into the first polysilicon layer 102 to prepare for forming a floating gate subsequently. The N-type ions enable the difference between the writing threshold voltage and the erasing threshold voltage of the floating grid to be larger, and the fluctuation of the loading voltage at two ends of the floating grid cannot influence the normal storage or the removal of electronic operation of the floating grid in the using process of the flash memory.

In this embodiment, the N-type ions include one or more of phosphorus, arsenic, and antimony.

In other embodiments, a shielding mask layer may be formed at a position where a select gate is formed in advance in the first polysilicon layer, so that N-type ions are not easily formed at the position of the preset select gate, and when the semiconductor structure works, a polysilicon depletion region is not easily formed in the select gate, thereby improving the read-write efficiency of the memory and the stability of the flash memory.

The inter-gate dielectric layer 103 is used to electrically isolate the subsequently formed floating gate from the control gate.

In this embodiment, the inter-gate dielectric layer 103 is made of a dielectric material.

Specifically, the material of the inter-gate dielectric layer 103 includes one or both of silicon oxide and silicon nitride. In this embodiment, the material of the inter-gate dielectric layer 103 is a sandwich structure composed of silicon oxide, silicon nitride and silicon oxide (ONO).

As shown in fig. 3, at a position corresponding to a predetermined select gate, the inter-gate dielectric layer 103 and a part of the thickness of the first polysilicon layer 102 are etched to form a groove (not shown in the figure); a second polysilicon layer 104 is formed overlying the recess and the inter-gate dielectric layer 103.

The groove penetrates through the inter-gate dielectric layer 103, and correspondingly, the second polysilicon layer 104 at the position corresponding to the preset select gate is in contact with the first polysilicon layer 102, so that in the subsequent process of doping P-type ions in the second polysilicon layer 104, the P-type ions in the second polysilicon layer 104 are easy to diffuse into the first polysilicon layer 102 below the groove, and preparation is made for forming the select gate subsequently.

In this embodiment, the second polysilicon layer 104 is made of polysilicon.

Specifically, the step of forming the second polysilicon layer 104 includes: forming a mask layer (not shown in the figure) on the inter-gate dielectric layer 103, wherein the mask layer exposes the inter-gate dielectric layer 103 at a position corresponding to a preset selection gate; etching the inter-gate dielectric layer 103 and the first polysilicon layer 102 with partial thickness by taking the mask layer as a mask to form a groove; forming a second polysilicon material layer covering the groove and the inter-gate dielectric layer 103; and carrying out planarization treatment on the second polysilicon material layer, wherein the rest second polysilicon material layer is used as a second polysilicon layer 104.

In this embodiment, a Low Pressure Chemical Vapor Deposition (LPCVD) method is used to form the second polysilicon material layer by using silane as a gas source.

In this embodiment, the second polysilicon layer is planarized by a Chemical Mechanical Planarization (CMP) process.

In this embodiment, since the groove is located at a position corresponding to a predetermined select gate, the formed second polysilicon layer 104 is also in a recessed state at the position corresponding to the predetermined select gate.

It should be noted that the method for forming the semiconductor structure further includes removing the mask layer after forming the second polysilicon layer 104.

As shown in fig. 4, P-type ions are doped in the second polysilicon layer 104. The P-type ions make the subsequently formed select gate and control gate less likely to be in a depleted state, thereby making the select gate in a conductive state.

In this embodiment, the P-type ions include one or more of boron, gallium, and indium.

Specifically, the second polysilicon layer 104 is doped with P-type ions by an ion implantation process.

It should be noted that, in the process of doping ions into the second polysilicon layer 104, the inter-gate dielectric layer 103 blocks P-type ions from entering the first polysilicon layer 102 below, so that the P-type ions only diffuse into the first polysilicon layer 102 exposed by the inter-gate dielectric layer 103, that is, the first polysilicon layer 102 at a position corresponding to a preset select gate. And the dosage of the P-type ion doping is greater than the dosage of the N-type doping to the first polysilicon layer 102, so as to ensure that the first polysilicon layer 102 at the position corresponding to the preset selection gate is in a P-type ion doping state.

As shown in fig. 5, after P-type ions are doped, the tunnel oxide layer 101, the first polysilicon layer 102 (shown in fig. 4), the inter-gate dielectric layer 103, and the second polysilicon layer 104 (shown in fig. 4) are etched to form a stacked gate structure 106 and a select gate 107.

The stacked gate structure 106 includes a tunneling oxide layer 101, a floating gate 108 formed by etching the first polysilicon layer 102, an inter-gate dielectric layer 103 on the floating gate 108, and a control gate 109 formed by etching the second polysilicon layer 104.

The select gate 107 includes: a tunnel oxide layer 101 and a select gate layer 110 formed by etching the first polysilicon layer 102 and the second polysilicon layer 104.

In this embodiment, a dry etching process is used to form the stacked gate structure 106 and the select gate 107. The dry etching process is an anisotropic etching process, has good etching profile controllability, is favorable for enabling the appearances of the stacked gate structure 106 and the select gate 107 to meet the process requirements, can etch each film layer in the same etching equipment by replacing etching gas, simplifies the process steps, is favorable for improving the forming efficiency of the stacked gate structure 106 and the select gate 107 and reduces the damage to other film layer structures.

It should be noted that, in the process of forming the stacked gate structure 106 and the select gate 107 by etching, the etched rate of the inter-gate dielectric layer 103 is less than the etched rate of the second polysilicon layer 104, so that the inter-gate dielectric layer 103 plays a role of etching pause, and the problem of excessive etching or insufficient etching caused by inconsistent etching rates in various regions can be avoided, so that the etching process is more uniform, and further, after the stacked gate structure 106 and the select gate 107 are formed, the surface of the substrate 100 is more flat. In order to make the inter-gate dielectric layer 103 perform a more uniform etching process during the etching process, therefore, the position of the preset select gate includes a position corresponding to the groove, and accordingly, in this embodiment, the select gate 107 includes a portion of the width of the inter-gate dielectric layer 103.

It should be further noted that, in other embodiments, the semiconductor structure is a fin field effect transistor (FinFET), the substrate is a substrate having a fin, and accordingly, the stacked gate structure and the select gate both cross the fin and cover a portion of the top wall and a portion of the sidewall of the fin.

As shown in fig. 6, sidewall layers 111 are formed on the sidewalls of the stacked gate structures 106 and the select gates 107.

The sidewall layer 111 is used for defining a formation region of a subsequent source-drain doped region, so that ions are not easily doped into the stacked gate structure 106 and the select gate 107 in the process of forming the source-drain doped region by subsequent doping, and the electrical properties of the stacked gate structure 106 and the select gate 107 are not affected.

Specifically, the material of the sidewall layer 111 includes: one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride boron silicon nitride, and boron nitride silicon carbide. In this embodiment, the sidewall layer 111 is made of silicon nitride.

The method of forming the substrate further comprises: after the sidewall layer 111 is formed, a source-drain doped region is formed on the substrate 100 exposed by the stacked gate structure 106 and the select gate 107, where the source-drain doped region includes: a common source-drain region 112 formed in the substrate 100 between the stacked gate structure 106 and the select gate 107, a source region 120 formed in the substrate 100 on the other side of the stacked gate structure 106, and a drain region 121 formed in the substrate 100 on the other side of the select gate 107.

The method for forming the semiconductor structure further comprises the following steps: after the source-drain doped regions are formed, a metal silicide layer 113 is formed on the stacked gate structure 106, the select gate 107, the source region 120, and the drain region 121.

The metal silicide layer 113 is used to reduce contact resistance between a contact hole plug formed subsequently and the stacked gate structure 106, the select gate 107, the source region 120 and the drain region 121, and improve electrical properties of the device.

In this embodiment, the metal silicide layer 113 is formed by a salicide process. The salicide process uses a metal material that reacts only with silicon but not with oxide or nitride materials, and thus reacts with the stacked gate structure 106, the select gate 107, the source region 120, and the drain region 121, so that the metal silicide layer 113 is formed in alignment with the stacked gate structure 106, the select gate 107, the source region 120, and the drain region 121.

In this embodiment, the metal material is nickel, and the material of the metal silicide layer 113 is correspondingly nickel-silicon compound. In other embodiments, the material of the metal silicide layer may also be a cobalt silicide or a titanium silicide.

Referring to fig. 7 and 8, an interlayer dielectric layer 114 (shown in fig. 8) is formed overlying the stacked gate structure 106 and the select gate 107.

Interlevel dielectric layer 114 is used to achieve electrical isolation between adjacent semiconductor structures.

The material of the interlayer dielectric layer 114 is a dielectric material.

In this embodiment, the interlayer dielectric layer 114 is made of silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric layer 114, and has simple removal process. In other embodiments, the material of the interlayer dielectric layer may also be one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

The step of forming the interlayer dielectric layer 114 includes: forming an interlayer dielectric material layer 115 (shown in fig. 7) covering the stacked gate structure 106 and the select gate 107; and flattening the interlayer dielectric material layer 115 to form the interlayer dielectric layer 114.

In this embodiment, the interlayer dielectric material layer 115 is formed by a Flowable Chemical Vapor Deposition (FCVD) process. The flow type chemical vapor deposition process has good filling capability, is beneficial to reducing the probability of defects such as cavities and the like in the interlayer dielectric material layer 115, and is correspondingly beneficial to improving the film forming quality of the interlayer dielectric layer 114.

Referring to fig. 9 to 11, the interlayer dielectric layer 114 between the stacked gate junction 106 and the select gate 107 is etched, or the interlayer dielectric layer 114 and the sidewall layer 111 are etched, so as to form an opening 116 (as shown in fig. 10).

And etching the interlayer dielectric layer 114 between the stacked gate structure 106 and the selection gate 107, or the interlayer dielectric layer 114 and the side wall layer 111, forming an opening 116 between the stacked gate structure 106 and the selection gate 107, and subsequently forming a low-K dielectric layer in the opening 116. Compared with the interlayer dielectric layer and the side wall layer, the dielectric constant of the low-K dielectric layer is lower, and it can be known that when the dielectric constant is reduced, the capacitive coupling effect between the stacked gate structure 106 and the select gate 107 is reduced, which is beneficial to reducing the programming voltage and the erasing voltage, improving the programming efficiency and the erasing efficiency, and reducing the power consumption of the device.

The step of forming the opening 116 includes: forming a shielding layer 117 on the interlayer dielectric layer 114, wherein the shielding layer 117 exposes the interlayer dielectric layer 114 and the sidewall layer 111 between the stacked gate structure 106 and the select gate 107; and etching the interlayer dielectric layer 114 and the side wall layer 111 by using the shielding layer 117 as a mask to form the opening 116.

The shielding layer 117 is used as an etching mask for removing the interlayer dielectric layer 114 and the sidewall layer 111 between the stacked gate structure 106 and the select gate 107, and the probability that the stacked gate structure 106 and the select gate 107 are etched is reduced in the process of removing the interlayer dielectric layer 114 and the sidewall layer 111.

Specifically, the material of the shielding layer 117 is an organic material, for example: BARC (bottom-antireflective coating) material, spin-on carbon (SOC), ODL (organic dielectric layer) material, photoresist, DARC (dielectric-antireflective coating) material, DUO (Deep UV Light Absorbing Oxide) material, or APF (Advanced Patterning Film) material. In this embodiment, the shielding layer 117 includes Spin On Carbon (SOC).

In other embodiments, the blocking layer may also be made of other materials that can serve as a mask and are easy to remove, so that damage to the protection layer is reduced when the blocking layer is subsequently removed.

The step of forming the shielding layer 117 includes: forming a shielding material layer (not shown) covering the interlayer dielectric layer 114; the masking material layer is patterned to form a masking layer 117.

In this embodiment, the blocking material layer is formed by a spin coating process, and the surface flatness of the blocking material layer is high.

In this embodiment, the interlayer dielectric layer 114 and the sidewall layer 111 exposed by the shielding layer 117 are etched by using a dry etching process to form the opening 116. The dry etching process is an anisotropic etching process, has good etching profile controllability, is favorable for enabling the appearance of the opening 116 to meet the process requirements, reduces the damage to other film structures, and is favorable for improving the removal efficiency of the interlayer dielectric layer 114 and the side wall layer 111.

It should be noted that the size of the opening 116 is not too large or too small in the direction perpendicular to the extending direction of the stacked gate structure 106. If the size of the opening 116 is too large, the stacked gate structure 106 and the select gate 107 are easily etched by mistake during the process of forming the opening 116, and during the writing process of the semiconductor structure operation, the quantum tunneling effect generated under the action of the strong electric field is weak, and electrons are not easy to break through the tunnel oxide layer 101 and enter the floating gate 108, so that the writing process is not easy to control. If the size of the opening 116 is too small, the capacitive coupling effect between the stacked gate structure 106 and the select gate 107 is reduced, the programming voltage and the erase voltage are increased, the programming and erase efficiency is reduced, and the performance of the semiconductor structure is poor. In the embodiment, the size of the opening 116 is 50 nm to 200 nm in a direction perpendicular to the extending direction of the stacked gate structure 106.

In other embodiments, in a direction perpendicular to the extending direction of the stacked gate structure, the width of the interlayer dielectric layer between the stacked gate structure and the select gate is much greater than the width of the sidewall layer, and only the interlayer dielectric layer between the stacked gate structure and the select gate may be etched to form an opening.

It should be noted that, during the process of forming the opening 116, polymer impurities are generated, and the polymer impurities are liable to accumulate at the bottom of the opening 116, which is liable to cause the bottom end of the low-K dielectric layer subsequently formed in the opening 116 to be higher than the bottom ends of the stacked gate structure 106 and the select gate 107, resulting in a severe capacitive coupling effect between the bottom end of the stacked gate structure 106 and the bottom end of the select gate 107.

Therefore, the method for forming the semiconductor structure further comprises the following steps: after forming the opening 116, the opening 116 is cleaned before forming a low-K dielectric layer in the opening 116.

In this embodiment, oxygen and the polymer impurities are oxidized to form gases such as carbon monoxide or carbon dioxide for removal. In other embodiments, the polymer impurities may also be removed by a reduction reaction of hydrogen with the polymer impurities, the hydrogen reacting with the polymer impurities to form water and carbon dioxide, and the like.

Referring to fig. 12 and 13, a low K dielectric layer 118 (shown in fig. 13) is formed in the opening 116 (shown in fig. 10).

The material of the low-K dielectric layer 118 is a low-K dielectric material. In this embodiment, the low-K dielectric material refers to a dielectric material having a relative dielectric constant of 3.9 or less. The low-K dielectric layer 118 is made of a low-K dielectric material, so that the capacitive coupling effect between the stacked gate structure 106 and the select gate 107 is reduced, the programming voltage and the erasing voltage are reduced, the programming efficiency and the erasing efficiency are improved, and the power consumption of the device is reduced.

Specifically, the materials of the low-K dielectric layer 118 include: SiOCH, or silicon oxide doped with C, B or P. In this embodiment, the materials of the low K dielectric layer 118 include: silicon oxide doped with C, B or P.

The step of forming a low-K dielectric layer 118 in the opening 116 includes: forming a layer of low-K dielectric material 119 covering the opening 116; the low-K dielectric material layer 119 exposed in the opening 116 is removed, and the low-K dielectric material layer 119 remaining in the opening 116 serves as a low-K dielectric layer 118.

In this embodiment, a Chemical Vapor Deposition (CVD) process is used to form the low-K dielectric material layer 119 in the opening 116. The chemical vapor deposition process has low process cost and simple operation.

In this embodiment, a Chemical Mechanical Planarization (CMP) process is used to remove the low-K dielectric material layer 119 exposing the opening 116. The cmp process is a global surface planarization technique that precisely and uniformly polishes the low-K dielectric material layer 119 to a desired thickness and flatness.

Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 100; a stacked gate structure 106 on the substrate 100; a select gate 107 on the substrate 100 and beside the stacked gate structure 106; a sidewall layer 111 located on sidewalls of the stacked gate structure 106 and the select gate 107; an interlayer dielectric layer 114, which is located on the stacked gate structure 106, the select gate 107 and the substrate 100 where the stacked gate structure 106 and the select gate 107 are exposed; a low-K dielectric layer 118 between the stacked gate structure 106 and the select gate 107.

In the embodiment of the present invention, the dielectric constant of the low-K dielectric layer 118 is lower than the dielectric constants of the interlayer dielectric layer 114 and the sidewall layer 111, the low-K dielectric layer 118 is formed between the stacked gate structure 106 and the select gate 107, and it can be known from the capacitance calculation formula C ═ S/d that when the dielectric constant is reduced, the capacitive coupling effect between the stacked gate structure 106 and the select gate 107 is reduced, which is beneficial to reducing the programming voltage and the erasing voltage, improving the programming efficiency and the erasing efficiency, and reducing the power consumption of the device.

In this embodiment, the semiconductor structure is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and correspondingly, the substrate 100 is a planar substrate.

In other embodiments, the semiconductor structure may also be a fin field effect transistor (FinFET), and the substrate may be a substrate having a fin portion, and accordingly, the stacked gate structure and the select gate may both cross the fin portion and cover a portion of a top wall and a portion of a sidewall of the fin portion. In other embodiments, the substrate is a substrate with a fin portion; the stacked gate structure and the selection gate both cross the fin portion and cover part of the top wall and part of the side walls of the fin portion.

The sidewall layer 111 is used for defining a forming region of a source-drain doped region, so that ions are not easily doped into the stacked gate structure 106 and the select gate 107 in the process of doping to form the source-drain doped region, and the electrical properties of the stacked gate structure 106 and the select gate 107 are not affected.

The semiconductor structure further includes: and the source and drain doped regions are positioned on the substrate 100 where the stacked gate structure 106 and the select gate 107 are exposed.

Specifically, the source-drain doped region includes: a common source drain region 112 located in the substrate 100 between the stacked gate structure 106 and the select gate 107; a source region 120 in the substrate 100 on a side of the stacked gate structure 106 away from the low-K dielectric layer 118; and a drain region 121 located in the substrate 100 on a side of the select gate 107 away from the low-K dielectric layer 118.

The semiconductor structure further includes: and a metal silicide layer 113 on the stacked gate structure 106, the select gate 107, the source region 120, and the drain region 121.

The metal silicide layer 113 is used to reduce the contact resistance between the contact hole plug and the stacked gate structure 106, the select gate 107, the source region 120, and the drain region 121, and improve the electrical performance of the device.

In this embodiment, the metal silicide layer 113 is made of nickel silicide. In other embodiments, the material of the metal silicide layer may also be a cobalt silicide or a titanium silicide.

In this embodiment, the low-K dielectric layer 118 is located between the sidewall layers 111 and the interlayer dielectric layers 114 between the stacked gate structures 106 and the select gates 107.

The material of the low-K dielectric layer 118 is a low-K dielectric material. In this embodiment, the low-K dielectric material refers to a dielectric material having a relative dielectric constant of 3.9 or less. Therefore, the capacitive coupling effect of the stacked gate structure 106 and the select gate 107 is reduced, which is beneficial to reducing programming voltage and erasing voltage, improving programming efficiency and erasing efficiency, and reducing power consumption of the device.

In other embodiments, the low-K dielectric layer is in contact with the stacked gate structure, or in contact with the select gate, or in contact with both the stacked gate structure and the select gate.

In other embodiments, the low-K dielectric layer is located in an interlayer dielectric layer between the stacked gate structure and the select gate.

It should be noted that the dimension of the low-K dielectric layer 118 is not too large or too small in the direction perpendicular to the extension direction of the stacked gate structure 106. If the size of the low-K dielectric layer 118 is too large, the semiconductor structure is easily made larger, the programming and erasing efficiency is reduced, the power consumption of the device is increased, and the reading speed of the flash memory is reduced. If the dimension of the low-K dielectric layer 118 is too small, the capacitive coupling effect between the stacked gate structure 106 and the select gate 107 is reduced, the programming voltage and the erase voltage are increased, the programming and erase efficiency is reduced, and the performance of the semiconductor structure is poor. In the embodiment, the dimension of the low-K dielectric layer 118 is 50 nm to 200 nm in the direction perpendicular to the extension direction of the stacked gate structure 106.

The interlayer dielectric layer 114 covers the stacked gate structure 106 and the select gate 107,

the material of the interlayer dielectric layer 114 is a dielectric material.

In this embodiment, the stacked gate structure 106 includes: the floating gate structure comprises a tunneling oxide layer 101, a floating gate 108 located on the tunneling oxide layer 101, a gate dielectric layer 103 located on the floating gate 108, and a control gate 109 located on the gate dielectric layer 103.

The tunnel oxide layer 101 is used to electrically isolate the substrate 100 from a subsequently formed floating gate.

The tunneling oxide layer 101 is made of a dielectric material.

Specifically, the tunnel oxide layer 101 includes one or both of silicon oxide and silicon nitride. In this embodiment, the tunneling oxide layer 101 is made of silicon oxide.

The floating gate 108 is used to store electrons. The flash memory is in a state after storing information or erasing information by storing or not storing electrons in the floating gate 108.

In this embodiment, the floating gate 108 is made of polysilicon. The floating gate 108 is doped with N-type ions.

In the process of writing and erasing, the N-type ions make the difference between the writing threshold voltage and the erasing threshold voltage of the floating gate 108 larger, and the fluctuation of the loading voltage at the two ends of the floating gate 109 does not influence the normal writing or erasing operation of the floating gate 108 in the using process of the flash memory.

The N-type ions include one or more of phosphorus, arsenic, and antimony.

The inter-gate dielectric layer 103 serves to electrically isolate the floating gate 108 from the control gate 109.

The control gate 109 is used to inject electrons into the floating gate 108 or pull electrons out of the floating gate 108 during data writing or erasing of the flash memory, and when data of the flash memory is read, the on/off state of the channel region at the bottom of the floating gate 108 is controlled by applying an operating voltage to the control gate 109, using the charged state of the floating gate 108.

In this embodiment, the control gate 109 is made of polysilicon.

It should be noted that the control gate 109 is doped with P-type ions, so that the control gate 109 is not easily in a depletion state, and the control gate 109 is in a conductive state.

The P-type ions include one or more of boron, gallium, and indium.

When the over-erase phenomenon of the select gate 107 is too severe, the source region on the left side of the stacked gate structure 106 and the drain on the right side of the select gate 107 are not easily turned on, thereby preventing data misreading.

In this embodiment, the select gate 107 includes: a tunnel oxide layer 101 and a select gate layer 110 on the tunnel oxide layer 101.

The material of the select gate layer 110 is polysilicon.

It should be noted that the select gate layer 110 is doped with P-type ions, so that the select gate layer 110 is not easily in a depletion state, and the select gate layer 110 is in a conductive state.

The semiconductor structure may be formed by the formation method of the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a base, wherein the base comprises a substrate, and a discrete stacked gate structure and a selection gate which are positioned on the substrate, and side wall layers are formed on the side walls of the stacked gate structure and the selection gate;

forming an interlayer dielectric layer covering the stacked gate structure and the selection gate;

etching the interlayer dielectric layer between the stacked gate structure and the select gate, or etching the interlayer dielectric layer and the side wall layer to form an opening;

a low-K dielectric layer is formed in the opening.

2. The method of forming a semiconductor structure of claim 1, wherein the step of forming an interlevel dielectric layer comprises: forming an interlayer dielectric material layer covering the stacked gate structure and the selection gate; and flattening the interlayer dielectric material layer to form the interlayer dielectric layer.

3. The method of forming a semiconductor structure of claim 2, wherein the step of forming the opening comprises: forming a shielding layer on the interlayer dielectric layer, wherein the shielding layer exposes the interlayer dielectric layer and the side wall layer between the stacked gate structure and the selection gate; and etching the interlayer dielectric layer or the side wall layer or the interlayer dielectric layer and the side wall layer between the stack grid structure and the selection grid by taking the shielding layer as a mask to form the opening.

4. The method of claim 1, wherein a dimension of the opening in a direction perpendicular to an extension direction of the stacked gate structure is between 50 nm and 200 nm.

5. The method of forming a semiconductor structure of claim 1, wherein the opening is formed by etching using a dry etching process.

6. The method of forming a semiconductor structure of claim 1, wherein a material of the low-K dielectric layer comprises: silicon oxide doped with C, B or P, or SiOCH.

7. The method of forming a semiconductor structure of claim 1, wherein forming a low-K dielectric layer in the opening comprises: forming a low-K dielectric material layer covering the opening; and removing the low-K dielectric material layer exposed out of the opening, wherein the low-K dielectric material layer remained in the opening is used as a low-K dielectric layer.

8. The method of claim 7, wherein a chemical mechanical planarization process is used to remove the low-K dielectric material layer exposing the opening.

9. The method of forming a semiconductor structure of claim 7, wherein the low-K dielectric material layer is formed in the opening using a chemical vapor deposition process.

10. The method of forming a semiconductor structure of claim 1, wherein the stacked gate structure comprises: the gate-to-gate structure comprises a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer;

the floating grid is doped with N-type ions, and the selection grid is doped with P-type ions.

11. The method of claim 1, wherein the substrate is a substrate having a fin portion;

the stacked gate structure and the selection gate both cross the fin portion and cover part of the top wall and part of the side walls of the fin portion.

12. A semiconductor structure, comprising:

a substrate;

the stacked gate structure is positioned on the substrate;

the selection gate is positioned on the substrate and positioned on the side edge of the stacked gate structure;

the side wall layer is positioned on the side walls of the stacked gate structure and the selection gate;

the interlayer dielectric layer is positioned on the stacked gate structure, the selection gate and the substrate exposed from the stacked gate structure and the selection gate;

and the low-K dielectric layer is positioned between the stacked gate structure and the selection gate.

13. The semiconductor structure of claim 12, wherein the low-K dielectric layer is in contact with the stacked gate structure, or with a select gate, or with both a stacked gate structure and a select gate.

14. The semiconductor structure of claim 12, wherein the low-K dielectric layer is located in an interlayer dielectric layer between the stacked gate structure and a select gate.

15. The semiconductor structure of claim 12, wherein said low-K dielectric layer is located between said sidewall layers and between said interlevel dielectric layers between said stacked gate structure and select gate.

16. The semiconductor structure of claim 12, wherein a dimension of the low-K dielectric layer in a direction perpendicular to an extension direction of the stacked gate structure is 50 nm to 200 nm.

17. The semiconductor structure of claim 12, wherein the material of the low-K dielectric layer comprises: SiOCH, or silicon oxide doped with C, B or P.

18. The semiconductor structure of claim 12, wherein the stacked gate structure comprises: the gate-to-gate structure comprises a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer;

19. The semiconductor structure of claim 12, wherein the substrate is a substrate having a fin;