CN104124210B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN104124210B CN104124210B CN201310156924.6A CN201310156924A CN104124210B CN 104124210 B CN104124210 B CN 104124210B CN 201310156924 A CN201310156924 A CN 201310156924A CN 104124210 B CN104124210 B CN 104124210B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 154
- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 133
- 230000002093 peripheral effect Effects 0.000 claims abstract description 64
- 238000007789 sealing Methods 0.000 claims abstract description 54
- 230000005669 field effect Effects 0.000 claims abstract description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 37
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 238000007667 floating Methods 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims description 37
- 238000002955 isolation Methods 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 239000010408 film Substances 0.000 claims description 17
- 125000006850 spacer group Chemical group 0.000 claims description 15
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 10
- 239000012528 membrane Substances 0.000 claims description 9
- 238000003860 storage Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 239000013039 cover film Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 9
- 238000012545 processing Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 107
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000004528 spin coating Methods 0.000 description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 210000003205 muscle Anatomy 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
A kind of forming method of semiconductor structure, including: Semiconductor substrate is provided, be formed with some discrete stacked structures in described Semiconductor substrate, the first silicon oxide layer in the stacked structure of memory area as the tunnel oxide of flash cell, the first polysilicon layer as the floating boom of flash cell；With described stacked structure as mask, etching described Semiconductor substrate, form the first groove in the outer peripheral areas and memory area of Semiconductor substrate, the Semiconductor substrate between the first groove adjacent in outer peripheral areas constitutes the first fin；Forming sealing coat on a semiconductor substrate, etching removes the part sealing coat of outer peripheral areas；Remove the stacked structure in outer peripheral areas, expose the top surface of the first fin；Form the first grid structure of fin field effect pipe at the sidewall of the first fin of outer peripheral areas and top surface, the floating boom of memory area is formed the control gate of flash cell.Form the processing technology of the process compatible fin field effect pipe of flash cell.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly to the forming method of a kind of semiconductor structure.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type: analog circuit,
Digital circuit and D/A hybrid circuit, an important kind during wherein memory device is digital circuit.Closely
Nian Lai, in memory device, the development of flash memory (flash memory is called for short flash cell) is outstanding
For rapidly.The information being mainly characterized by the case of not powered keeping storing for a long time of flash cell；
And have that integrated level is high, access speed fast, be prone to the advantages such as erasing and rewriting, thus at microcomputer, automatically
Change the multinomial fields such as control to be widely used.
Erasable Programmable Read Only Memory EPROM (Electrically Erasable Programmable ROM,
EEPROM) application widely has been obtained as a kind of important flash memory.Fig. 1 is existing skill
The cross-section structure of one memory element of the Erasable Programmable Read Only Memory EPROM (EEPROM) that art is formed
Schematic diagram, described EEPROM memory cell, including: Semiconductor substrate 100；It is positioned at described quasiconductor
Discrete memory transistor 10 on substrate 100 and selection transistor 20, described memory transistor 10 wraps
Include and be positioned at the gate stack on Semiconductor substrate 100 surface and be positioned at gate stack semiconductor substrates on two sides 100
Interior drain region and source region 109, described selection transistor 20 includes the grid being positioned at Semiconductor substrate 100 surface
Stacks and the drain region 107 and the source region that are positioned at gate stack semiconductor substrates on two sides 100, described storage
The source region of the drain region of transistor 10 and selection transistor 20 is the most overlapping, forms co-doped district 108, institute
State co-doped district 108 realize memory transistor 10 and select the connection between transistor 20.Described deposit
The gate stack of storage transistor 10 include being sequentially located at Semiconductor substrate 100 surface tunnel oxide 101,
Floating boom 102, control gate oxide layer 103 and control gate 104, described floating boom 102 is used for storing electric charge；Institute
State gate oxide 105 He selecting the gate stack of transistor 20 to include Semiconductor substrate 100 surface successively
Gate electrode 106.Described Semiconductor substrate 100 is also formed with N trap, described drain region 107, source region 109 and
Co-doped district 108 is p-type doping.
Described memory element carries out the process of erasing operation: select transistor 20 gate electrode 106 (with
Wordline is connected) apply positive voltage with the source region 109 (being connected with source line) of memory transistor 10, in storage
The control gate of transistor 10 applies negative voltage, the drain region 107 of transistor 20 will be selected (with bit line phase simultaneously
Even) being set to open circuit, in the floating boom 102 of memory transistor 10, the electronics of storage is by tunnel oxide 101
Transfer in drain region 109, it is achieved memory element carries out wiping operating process.
The processing technology of existing flash memory would generally be with peripheral circuit midplane MOS transistor
Processing technology is mutually compatible, but when semiconductor technology enters 30 nanometers with lower node, traditional plane formula
The control ability of channel current is died down by MOS transistor, causes serious leakage current.And fin field effect
Transistor (FinFET) is as a kind of emerging multi-gate device, compared with planar MOS transistors, fin
Formula field-effect transistor can improve driving electric current while keeping the lowest cut-off current, it is possible to effectively
Suppression short-channel effect, therefore fin formula field effect transistor is applied in the peripheral circuit of flash memory
A kind of trend is the most necessarily become in the future.Fig. 2 shows a kind of fin formula field effect transistor of prior art
Perspective view.As in figure 2 it is shown, include: Semiconductor substrate 10, described Semiconductor substrate 10
On be formed with the fin 14 of protrusion, fin 14 is generally by obtaining after etching Semiconductor substrate 10；
Dielectric layer 11, covers the surface of described Semiconductor substrate 10 and a part for the sidewall of fin 14；Grid
Electrode structure 12, across on described fin 14, covers top and the sidewall of described fin 14, and grid is tied
Structure 12 includes gate dielectric layer (not shown) and the gate electrode (not shown) being positioned on gate dielectric layer.
The fin 14 of existing fin formula field effect transistor is formed typically by etch semiconductor substrates 10.
Due to the huge diversity of structure of structure and the flash memory of fin formula field effect transistor, because of
This, fin formula field effect transistor faces challenge greatly with both compatible processing technology of flash memory.
Summary of the invention
The problem that the present invention solves is to provide a kind of making fin formula field effect transistor transistor and flash
The compatible technology of device.
For solving the problems referred to above, technical solution of the present invention provides the forming method of a kind of semiconductor structure,
The forming method of semiconductor structure, including: providing Semiconductor substrate, described Semiconductor substrate includes periphery
Region and memory area, the outer peripheral areas of described Semiconductor substrate and memory area are formed some discrete
The first silicon oxide layer, the first polysilicon layer being positioned in the first oxide layer and be positioned on the first polysilicon layer
First mask layer constitute stacked structure, first in the stacked structure of the memory area of Semiconductor substrate
Silicon oxide layer as the tunnel oxide of flash cell, the first polysilicon layer as the floating boom of flash cell；
With described some discrete stacked structures as mask, etch described Semiconductor substrate, in Semiconductor substrate
Outer peripheral areas and memory area form some the first discrete grooves, in the outer peripheral areas of Semiconductor substrate
The adjacent Semiconductor substrate between the first groove constitutes the first fin, in the memory area of Semiconductor substrate
Adjacent first groove between Semiconductor substrate constitute the second fin；Formed on the semiconductor substrate
Sealing coat, described sealing coat covers described stacked structure and fills full first groove, the surface of sealing coat and
The flush of the first mask layer；Etching removes the part sealing coat of the outer peripheral areas of Semiconductor substrate, cruelly
Expose the partial sidewall surface of the stacked structure in the outer peripheral areas of Semiconductor substrate and the first fin；Remove
Stacked structure in the outer peripheral areas of Semiconductor substrate, exposes the top surface of the first fin；Remove half
The first mask layer on the memory area of conductor substrate；The first fin in the outer peripheral areas of Semiconductor substrate
Sidewall and top surface formed fin formula field effect transistor first grid structure, serve as a contrast at described quasiconductor
The control gate of flash cell is formed on the floating boom of the memory area at the end.
Optionally, the forming method of described stacked structure is: be formed with first on the semiconductor substrate
Silicon oxide film, the first polysilicon membrane and the first mask thin film；It is sequentially etched removal part described first
Mask thin film, the first polysilicon layer thin film and the first silicon oxide film, in the outer peripheral areas of Semiconductor substrate
With form some the first discrete silicon oxide layers, the first polysilicon layer and the first mask layer structure on memory area
The stacked structure become.
Optionally, the material of described sealing coat is silicon oxide.
Optionally, the forming process of described sealing coat is: is formed and covers described stacked structure and quasiconductor lining
The spacer material layer at the end, described spacer material layer fills full first groove；Planarize described spacer material layer,
With the first mask layer as stop-layer, form sealing coat.
Optionally, before the part sealing coat of the outer peripheral areas that etching removes Semiconductor substrate, also include:
Described sealing coat is formed the second mask layer, the second mask layer has the periphery of exposing semiconductor substrate
Zone isolation layer surface and first opening on stacked structure surface.
Optionally, described second mask material is photoresist.
Optionally, described second mask layer has the part stacking on exposing semiconductor substrate memory area
Some second openings of the sealing coat of structure and described part stacked structure both sides.
Optionally, when described etching removes the part sealing coat of outer peripheral areas of Semiconductor substrate, go simultaneously
The part sealing coat exposed except the second opening, the surface of the second remaining sealing coat of open bottom is less than second
The top surface of fin.
Optionally, during stacked structure in the outer peripheral areas of described removal Semiconductor substrate, remove simultaneously
The part stacked structure on Semiconductor substrate memory area that two openings expose, exposed portion the second fin
Top surface.
Optionally, the forming process of described first grid structure and control gate is: remove described second mask
Layer；Formed and cover described Semiconductor substrate, sealing coat, the first fin and the memory area of Semiconductor substrate
On the second silicon oxide film of floating boom；Described second silicon oxide film forms the second polysilicon membrane；
It is sequentially etched removal described second polysilicon membrane of part and the second silicon oxide film, in Semiconductor substrate
Form first grid dielectric layer on the sidewall of the first fin of outer peripheral areas and top surface and be positioned at first grid Jie
First gate electrode on matter layer, forms isolation oxidation on the floating boom of the memory area of described Semiconductor substrate
Silicon layer and the control gate being positioned on isolation oxidation silicon layer, wherein said first grid dielectric layer and first grid electricity
Pole constitutes the first grid structure of fin formula field effect transistor, isolation oxidation silicon layer and control gate and constitutes sudden strain of a muscle
The control gate of memory cell.
Optionally, while forming first grid structure and control gate, at Semiconductor substrate memory area
Second fin top surface formed flash cell select MOS transistor second grid structure.
Optionally, described Semiconductor substrate is carried out ion implanting, in the of the both sides of first grid structure
The source/drain region of fin formula field effect transistor is formed, at the second fin of second grid structure both sides in one fin
The interior source/drain region forming selection MOS transistor.
Optionally, while forming first grid structure and control gate, at Semiconductor substrate memory area
The second fin sidewall and top surface formed flash cell select fin formula field effect transistor the 3rd grid
Electrode structure.
Optionally, described Semiconductor substrate is carried out ion implanting, in the of the both sides of first grid structure
The source/drain region of fin formula field effect transistor is formed, at the second fin of the 3rd grid structure both sides in one fin
The interior source/drain region forming selection fin formula field effect transistor.
Optionally, remove the upper first grid structure of the first fin, form the second groove, described
High-K gate dielectric layer is formed on the sidewall of two grooves and bottom, forms metal gates on high-K gate dielectric layer.
Optionally, it is also formed with work-function layer between described metal gates and high-K gate dielectric layer.
Optionally, the material of described first mask layer be silicon nitride, silicon oxynitride, silicon oxide carbide, without fixed
Shape carbon or carbon silicon oxynitride.
Optionally, the thickness of described first mask layer is 300～800 angstroms.
Optionally, the thickness of described first silicon oxide layer is 20～60 angstroms.
Optionally, the thickness of described first polysilicon layer is 800～1200 angstroms.
Compared with prior art, technical solution of the present invention has the advantage that
Form some discrete stacked structures, the heap of the memory area of Semiconductor substrate on a semiconductor substrate
The first silicon oxide layer in stack structure as the tunnel oxide of flash cell, the first polysilicon layer as sudden strain of a muscle
The floating boom of memory cell, the stacked structure of the outer peripheral areas of Semiconductor substrate is formed as etch semiconductor substrates
The mask of the first fin；Then, with described some discrete stacked structures as mask, etch and described partly lead
Body substrate, forms some the first discrete grooves in the outer peripheral areas and memory area of Semiconductor substrate,
The Semiconductor substrate between the first groove adjacent in the outer peripheral areas of Semiconductor substrate constitutes the first fin,
The Semiconductor substrate between adjacent first groove in the memory area of Semiconductor substrate constitutes the second fin；
Then, forming sealing coat on the semiconductor substrate, etching removes the outer peripheral areas of Semiconductor substrate
Part sealing coat, exposes the stacked structure in the outer peripheral areas of Semiconductor substrate and the part of the first fin
Sidewall surfaces；Then, remove the stacked structure in the outer peripheral areas of Semiconductor substrate, expose the first fin
The top surface in portion；The sidewall of the first fin of outer peripheral areas and top surface in Semiconductor substrate are formed
The first grid structure of fin formula field effect transistor, simultaneously can be at the memory area of described Semiconductor substrate
Floating boom on form the control gate of flash cell.The forming method of the semiconductor structure of the present invention, is being formed
Compatible can form fin formula field effect transistor while flash cell, technical process is simple and convenient.
Further, while forming first grid structure and control gate, at Semiconductor substrate memory area
What the second fin sidewall exposed and top surface formed flash cell selects the of fin formula field effect transistor
Three grid structures.Owing to fin formula field effect transistor has the leakage current little driving big feature of electric current, by fin
Field-effect transistor, as the selection transistor of flash cell, is greatly improved the property of whole flash cell
Can, and the fin formula field effect transistor that selects of memory area can be brilliant with the fin field effect of outer peripheral areas
Body pipe concurrently forms, and processing step is relatively simple.
Accompanying drawing explanation
Fig. 1 is the section knot of one flash cell of Erasable Programmable Read Only Memory EPROM that prior art is formed
Structure schematic diagram；
Fig. 2 shows the perspective view of a kind of fin formula field effect transistor of prior art；
Fig. 3～Figure 17 is the structural representation of the forming method of embodiment of the present invention semiconductor structure.
Detailed description of the invention
As background technology is sayed, the forming method of existing fin formula field effect transistor and flash memory
Manufacture method be difficult to compatibility.
Embodiments provide the forming method of a kind of semiconductor structure, form the same of flash cell
Time formed fin formula field effect transistor, process is simple and convenient.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.
Fig. 3～Figure 17 is the structural representation of the forming method of embodiment of the present invention semiconductor structure.
First, with reference to Fig. 3, it is provided that Semiconductor substrate 300, described Semiconductor substrate 300 includes external zones
Territory 31 and memory area 32, outer peripheral areas 31 can be adjacent or non-conterminous with memory area 32, and described half
Some the first discrete silicon oxides it are formed with in the outer peripheral areas 31 of conductor substrate 300 and memory area 32
Layer 301, the first polysilicon layer 302 of being positioned in the first oxide layer 301 and be positioned at the first polysilicon layer 302
On first mask layer 303 constitute stacked structure 33, the heap of the memory area 32 of Semiconductor substrate 300
The first silicon oxide layer 301 in stack structure 33 is as the tunnel oxide of flash cell, the first polysilicon layer
302 as the floating boom of flash cell.
Concrete, described stacked structure 33 forming process is: depend in described Semiconductor substrate 300 successively
Secondary formation the first silicon oxide film, the first polysilicon membrane, the first mask thin film, patterned photoresist
Layer；With described patterned photoresist layer as mask, be sequentially etched described first mask thin film, more than first
Polycrystal silicon film and the first silicon oxide film, form first silicon oxide layer the 301, first polysilicon layer 302 and
The stacked structure 33 that one mask layer 303 is constituted.
The quantity of the stacked structure 33 formed on described memory area 32 is more than or equal to 2, stacked structure
Being parallel to each other between 33, and have equal spacing and identical length and width, stacked structure 33 is follow-up
For forming the flash cell of array arrangement, width and the length of stacked structure 33 are entered according to concrete application
Row sets.
The width of the stacked structure 33 formed in described outer peripheral areas 31 is brilliant with fin field effect to be formed
The width of the fin of body pipe is correlated with, and the stacked structure 33 that outer peripheral areas 31 is formed is as subsequent etching half
Conductor substrate 300 forms mask during the first fin.Stacked structure 33 number formed in outer peripheral areas 31
Amount, more than or equal to 1, can be parallel to each other between the adjacent stacks structure 33 that outer peripheral areas 31 is formed
Or not parallel, the width of adjacent stacks structure 33 and length can be equal or unequal.
The stacked structure 33 formed in outer peripheral areas 31 and the stacked structure 33 of formation in outer peripheral areas 31
Width equal or unequal.
The material of described first mask layer 303 is silicon nitride, silicon oxynitride, silicon oxide carbide, amorphous carbon
Or carbon silicon oxynitride, in the present embodiment, the material of described first mask layer 303 is silicon nitride, described
The thickness of one mask layer 303 is 300～800 angstroms.
The thickness of described first silicon oxide layer 301 is 20～60 angstroms.
The thickness of described first polysilicon layer 302 is 800～1200 angstroms.
Then, it is the Fig. 4 cross-sectional view along line of cut AB direction with reference to Fig. 4 and Fig. 5, Fig. 5,
With described some discrete stacked structures 33 as mask, etch described Semiconductor substrate 300, at quasiconductor
The outer peripheral areas 31 of substrate 300 and memory area 32 are formed some the first discrete grooves 304, partly leads
The Semiconductor substrate 300 between the first groove 304 adjacent in the outer peripheral areas 31 of body substrate 300 is constituted
First fin 305, between adjacent first groove 304 in the memory area 32 of Semiconductor substrate 300
Semiconductor substrate 300 constitutes the second fin 306.
In the present embodiment, use the stacked structure 33 of outer peripheral areas 31 can serve as a contrast with etching semiconductor for mask
The end 300, forms mask when the first fin 305 and the first groove 304, and the first fin 305 of formation can
Using as the fin of fin formula field effect transistor in peripheral circuit, the groove of the first fin 305 both sides is follow-up
Fill isolated material and form fleet plough groove isolation structure, for the fin formula field effect transistor that electric isolation is adjacent
And outer peripheral areas and the electric isolation of memory area, while forming the first fin 305, to deposit
The stacked structure 33 in storage area territory 32 is mask, forms the first groove 304 and the second fin 306, described
One groove 304 follow-up filling isolated material forms isolation structure for the adjacent row of electric isolation or row
Memory array cell, a part of top surface of described second fin 306 is subsequently formed flash cell
Floating boom and control gate, another part of described second fin 306 is subsequently formed the selection of flash cell
MOS transistor or selection fin formula field effect transistor.
The method etching described Semiconductor substrate is dry etching, dry etching use gas be HBr and/
Or Cl2。
Described first groove 304 be shaped as rectangle or U-shaped or V-type, the degree of depth of the first groove 304 is
50～500 nanometers.
It is the Fig. 6 cross-sectional view along line of cut AB direction with reference to Fig. 6 and Fig. 7, Fig. 7, in institute
Stating formation sealing coat 307 in Semiconductor substrate 300, described sealing coat 307 covers described stacked structure 33
And fill full first groove 304 (with reference to Fig. 4), the surface of sealing coat 307 and the first mask layer 303
Flush；Described sealing coat 307 is formed the second mask layer 308, the second mask layer 308 has
Sealing coat 307 surface of the outer peripheral areas 31 of exposing semiconductor substrate and the first of stacked structure surface open
Mouth 34.
The material of described sealing coat 307 is silicon oxide or other suitable materials.
The forming process of described sealing coat 307 is: the described stacked structure of described covering 33 and Semiconductor substrate
The spacer material layer (not shown) of 300, described spacer material layer is filled full first groove, is isolated material
The surface of the bed of material is higher than stacked structure 33 top surface；Use chemical mechanical milling tech planarization described every
From material layer, with the first mask layer 303 as stop-layer, form sealing coat 307.
Described spacer material layer is monolayer or double stacked structure, due to the first groove 304 degree of depth and stacking
The degree of depth sum of the opening between structure 33 is relatively big, when described spacer material layer is single layer structure, forms institute
The technique stating spacer material layer is preferably plasma enhanced chemical vapor deposition processes (PECVD), energy
Effectively prevent from deposition process occurs opening blockage effect (overhang).
When described spacer material layer is double stacked structure, first-selected employing spin coating proceeding forms the first isolation material
The bed of material (such as: silica glass)；Then using plasma enhanced chemical vapor deposition processes is
The second spacer material layer is formed on one spacer material layer.Owing to spin coating proceeding has preferable filling perforation performance,
Therefore use spin coating proceeding and plasma enhanced chemical vapor deposition processes depth of cracking closure deeper the
When one groove 304 and stacked structure 33, the defect such as spacer material layer void that can make formation is less,
And the uniformity on the surface of the spacer material layer formed is preferable, cmp planarization isolated material
During layer, reduced the generation of grinding phenomenon.
In the present embodiment, described second mask layer 308 for photoresist mask, in the second mask layer 308
There is sealing coat 307 surface and first opening 34 on stacked structure surface exposing outer peripheral areas 31, after
The sealing coat 307 of the continuous segment thickness that can remove outer peripheral areas 31 along the first opening 34 etching, in periphery
First groove 304 in region 31 is formed isolation structure.
Described second mask layer 308 also has the part stacking on exposing semiconductor substrate memory area 32
Some second openings 35 of the sealing coat 307 of structure 33 and described part stacked structure 33 both sides, some
Second opening 35 and the second mask layer 308 are spaced apart along the length direction of the second fin 306, the most biphase
Be the second mask layer 308 partly between adjacent second opening 35, follow-up etch segmentation along the second opening 35 and deposit
Storage area territory 32 can form some flash cell tunnel oxides and floating boom.In the present embodiment, with one
Two openings 35 are as embodiment, in follow-up etching technics, and the memory block that the second mask layer 308 covers
The first silicon oxide layer 301 and the first polysilicon layer 302 in territory 32 stacked structure 33 are retained, and make
For tunnel oxide and the floating boom of flash cell, and the memory area 32 that covers of the second mask layer 308
Sealing coat 307 is also retained, as isolation between flash cell in the adjacent column or row of flash array
Structure, the stacked structure 33 that the second opening 35 exposes is removed in subsequent technique so that the second fin
The part surface of 306 is exposed, thus forms the selection of flash cell on the second fin 306 exposed
MOS transistor or select fin formula field effect transistor and the source/drain of flash cell, and remove second
The memory area 32 segment thickness sealing coat 307 that opening 35 exposes, the first groove 304 of memory area 32
In remaining sealing coat 307 as in the adjacent column or row of flash array select MOS transistor or select fin
Isolation structure between formula field-effect transistor.
In other embodiments of the invention, described second mask layer 308 can also be other suitable materials
Material, such as: the hard mask material layers such as titanium nitride, amorphous carbon, silicon nitride, boron nitride.
Then, it is the cross-sectional view along Fig. 8 line of cut AB direction with reference to Fig. 8 and Fig. 9, Fig. 9,
The part sealing coat of the outer peripheral areas 31 of Semiconductor substrate is removed along the first opening 34 (with reference to Fig. 6) etching
307, expose the stacked structure in the outer peripheral areas 31 of Semiconductor substrate and the part of the first fin 305
Sidewall surfaces, remaining part sealing coat 307 in the first groove 304 (with reference to Fig. 4) of outer peripheral areas 31
As isolation junction between adjacent fin formula field effect transistor and between outer peripheral areas 31 and memory area 32
Structure, removes, along the second opening 35 (with reference to Fig. 6), the part sealing coat 307 that the second opening 35 exposes simultaneously,
Bottom second opening 35, the surface of remaining sealing coat 307 is less than the top surface of the second fin 306.
Etching described sealing coat 307 is dry etching, the CF that dry etching uses4And CHF3, described dry
The gas that method etching uses can also be NF3And CHF3。
In other embodiments of the invention, the surface of described remaining sealing coat 307 can also be higher than the
One fin 305 or the second fin 306 top surface, follow-up at removal the first opening 34 and the second opening 35
During the part stacked structure exposed, can remaining sealing coat 307 be etched back to so that surplus simultaneously
Remaining sealing coat 307 surface is less than the first fin 305 or the second fin 306 top surface.
Then, with reference to Figure 10, Figure 11 and Figure 12, Figure 11 is Figure 10 to be shown along the cross-section structure in AB direction
Being intended to, Figure 12 is the Figure 11 cross-sectional view along CD direction, removes the first opening 34 (reference
Stacked structure in the outer peripheral areas 31 of Semiconductor substrate Fig. 6) exposed, exposes the first fin 305
Top surface, remove the Semiconductor substrate memory area that the second opening 35 (with reference to Fig. 6) exposes simultaneously
Part stacked structure on 32, the top surface of exposed portion the second fin 306.
Removing described stacked structure is dry etching, and other of dry etching employing include fluorine-containing and/or chloride
Gas.
Then, refer to Figure 13, Figure 14 and Figure 15, Figure 14 is the Figure 13 cross-section structure along AB direction
Schematic diagram, Figure 15 is the Figure 13 cross-sectional view along CD direction, removes the storage of Semiconductor substrate
The second mask layer 308 (with reference to Fig. 8) on region 32 and the first mask layer 303 in stacked structure
(with reference to Fig. 8)；The sidewall of the first fin 305 of outer peripheral areas 31 and top surface in Semiconductor substrate
Form the first grid structure 309 of fin formula field effect transistor, at the memory area of described Semiconductor substrate
Isolation oxidation silicon layer 311 and the control gate being positioned on isolation oxidation silicon layer 311 is formed on the floating boom 302 of 32
Pole 312, isolation oxidation silicon layer 311 and control gate 312 constitute the control gate of flash cell.
Concrete, the forming process of described first grid structure 309 and control gate is: remove described second
Mask layer 308 and the first mask layer 313；Formed cover described Semiconductor substrate 300, sealing coat 307,
Second silicon oxide film (the figure of the floating boom 302 on the memory area 32 of the first fin 305 and Semiconductor substrate
Not shown in)；Described second silicon oxide film is formed the second polysilicon membrane (not shown)；
It is sequentially etched removal described second polysilicon membrane of part and the second silicon oxide film, in Semiconductor substrate
Form first grid dielectric layer on the sidewall of the first fin 305 of outer peripheral areas 31 and top surface and be positioned at the
First gate electrode on one gate dielectric layer, on the floating boom 302 of the memory area 32 of described Semiconductor substrate
Form isolation oxidation silicon layer 311 and the control gate 312 being positioned on isolation oxidation silicon layer 311, wherein said
First grid dielectric layer and first gate electrode constitute the first grid structure 309 of fin formula field effect transistor, isolation
Silicon oxide layer 311 and control gate 312 constitute the control gate of flash cell.Etching described second polycrystalline
Before silicon thin film and the second silicon oxide film, form patterned on described second polysilicon membrane surface
Three mask layers.
In the present embodiment, while forming first grid structure 309 and control gate, in Semiconductor substrate
Second fin sidewall of memory area 32 exposure and top surface form the selection fin field effect of flash cell
3rd grid structure 310 of transistor.Due to fin formula field effect transistor, to have leakage current little driving electric current big
Feature, using fin formula field effect transistor as the selection transistor of flash cell, is greatly improved whole
The performance of flash cell, and the selection fin formula field effect transistor of memory area 32 can and outer peripheral areas
The fin formula field effect transistor of 31 concurrently forms, and processing step is relatively simple.
In other embodiments of the invention, while forming first grid structure and control gate, half
Second fin 306 top surface of the exposure of conductor substrate storage region 32 forms the selection of flash cell
The second grid structure of MOS transistor (planar MOS transistors).
Finally, reference Figure 16 and Figure 17, Figure 16 is the Figure 13 sectional structure chart formation fin along EF direction
The schematic diagram of formula field-effect transistor source/drain region, Figure 17 is the Figure 13 cross-section structure figure along CD direction
Become to select the schematic diagram of transistor source/drain region, described Semiconductor substrate 300 is carried out ion implanting, the
The source/drain region of fin formula field effect transistor is formed in first fin 305 of the both sides of one grid structure 309
313, formed in the second fin 306 of the 3rd grid structure 310 both sides and select fin formula field effect transistor
Source region 314 and drain region 315 (or formed in the second fin of second grid structure both sides and select MOS
The source/drain region of transistor).
The dopant ion of described ion implanting is N-type impurity ion or p type impurity ion, according to formed
The type of the type selecting dopant ion of fin formula field effect transistor.
Source region 314 between floating boom 302 and the 3rd grid structure 310 as flash cell general character doped region,
Source region in second fin 306 of floating boom other side is the most not shown.
In other embodiments of the invention, also include: the first grid structure removing on the first fin,
Form the second groove, form high-K gate dielectric layer in sidewall and the bottom of described second groove；At high K grid
Work-function layer is formed on dielectric layer；Forming metal gates in work-function layer, metal gates fills full residue
The second groove.It should be noted that while the first grid structure removed on the first fin, also
The second grid structure on the second fin or the 3rd grid structure can be removed, form the 3rd groove, then
High-K gate dielectric layer and metal gates is formed so that the selection transistor (choosing of memory area in the 3rd groove
Select MOS transistor or select fin formula field effect transistor) there is metal gates, select transistor to reduce
The parasitic capacitance of grid, improves the speed selecting transistor, thus improves the performance of whole flash cell.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, appoints
What those skilled in the art without departing from the spirit and scope of the present invention, may be by the disclosure above
Technical solution of the present invention is made possible variation and amendment by method and technology contents, therefore, every does not takes off
From the content of technical solution of the present invention, it is any that above example is made by the technical spirit of the foundation present invention
Simple modification, equivalent variations and modification, belong to the protection domain of technical solution of the present invention.
Claims (20)
1. the forming method of a semiconductor structure, it is characterised in that including:
Thering is provided Semiconductor substrate, described Semiconductor substrate includes outer peripheral areas and memory area, described quasiconductor
It is formed with some the first discrete silicon oxide layers in the outer peripheral areas of substrate and memory area, is positioned at the first oxygen
Change the stacking knot that the first polysilicon layer on layer is constituted with the first mask layer being positioned on the first polysilicon layer
Structure, the first silicon oxide layer in the stacked structure of the memory area of Semiconductor substrate is as the tunnel of flash cell
Wear oxide layer, the first polysilicon layer as the floating boom of flash cell；
With described some discrete stacked structures as mask, etch described Semiconductor substrate, in Semiconductor substrate
Outer peripheral areas and memory area in form some the first discrete grooves, the outer peripheral areas of Semiconductor substrate
In Semiconductor substrate between adjacent the first groove constitute the first fin, the memory area of Semiconductor substrate
In adjacent first groove between Semiconductor substrate constitute the second fin；
Forming sealing coat on the semiconductor substrate, described sealing coat covers described stacked structure and fills full
The flush of the first groove, the surface of sealing coat and the first mask layer；
Etching removes the part sealing coat of the outer peripheral areas of Semiconductor substrate, exposes the periphery of Semiconductor substrate
Stacked structure on region and the partial sidewall surface of the first fin；
Remove the stacked structure in the outer peripheral areas of Semiconductor substrate, expose the top surface of the first fin；
Remove the first mask layer on the memory area of Semiconductor substrate；
The sidewall of the first fin of outer peripheral areas and top surface in Semiconductor substrate form fin field effect
The first grid structure of transistor, forms flash memory list on the floating boom of the memory area of described Semiconductor substrate
The control gate of unit.
2. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described stacked structure
Forming method be: be formed with the first silicon oxide film, the first polysilicon on the semiconductor substrate thin
Film and the first mask thin film；It is sequentially etched the removal described first mask thin film of part, the first polysilicon layer thin
Film and the first silicon oxide film, formed some discrete in the outer peripheral areas and memory area of Semiconductor substrate
The first silicon oxide layer, the stacked structure that constitutes of the first polysilicon layer and the first mask layer.
3. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described sealing coat
Material is silicon oxide.
4. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that described sealing coat
Forming process is: is formed and covers described stacked structure and the spacer material layer of Semiconductor substrate, described isolation
Material layer fills full first groove；Planarize described spacer material layer, with the first mask layer as stop-layer,
Form sealing coat.
5. the forming method of semiconductor structure as claimed in claim 1, it is characterised in that etching is removed and partly led
Before the part sealing coat of the outer peripheral areas of body substrate, also include: on described sealing coat, form second cover
Film layer, has outer peripheral areas insulation surface and the stacking knot of exposing semiconductor substrate in the second mask layer
First opening on structure surface.
6. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that described second mask
Layer material is photoresist.
7. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that described second mask
There is in Ceng the part stacked structure on exposing semiconductor substrate memory area and described part stacked structure two
Some second openings of the sealing coat of side.
8. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that described etching is removed
During the part sealing coat of the outer peripheral areas of Semiconductor substrate, remove the part isolation that the second opening exposes simultaneously
Layer, the surface of the second remaining sealing coat of open bottom is less than the top surface of the second fin.
9. the forming method of semiconductor structure as claimed in claim 7, it is characterised in that described removal is partly led
During stacked structure in the outer peripheral areas of body substrate, remove the Semiconductor substrate that the second opening exposes simultaneously and deposit
Part stacked structure on storage area territory, the top surface of exposed portion the second fin.
10. the forming method of semiconductor structure as claimed in claim 5, it is characterised in that described first grid
The forming process of structure and control gate is: remove described second mask layer；Formed and cover described quasiconductor lining
Second silicon oxide film of the floating boom on the memory area of the end, sealing coat, the first fin and Semiconductor substrate；
Described second silicon oxide film forms the second polysilicon membrane；It is sequentially etched removal part described second
Polysilicon membrane and the second silicon oxide film, at the sidewall of the first fin of the outer peripheral areas of Semiconductor substrate
With form first grid dielectric layer and the first gate electrode that is positioned on first grid dielectric layer on top surface, in institute
Form isolation oxidation silicon layer on the floating boom of the memory area stating Semiconductor substrate and be positioned on isolation oxidation silicon layer
Control gate, wherein said first grid dielectric layer and first gate electrode constitute fin formula field effect transistor
First grid structure, isolation oxidation silicon layer and control gate constitute the control gate of flash cell.
The forming method of 11. semiconductor structures as described in claim 8 or 9 or 10, it is characterised in that
While forming first grid structure and control gate, at the second fin top of Semiconductor substrate memory area
Surface forms the second grid structure selecting MOS transistor of flash cell.
The forming method of 12. semiconductor structures as claimed in claim 11, it is characterised in that partly lead described
Body substrate carries out ion implanting, forms fin field effect in the first fin of the both sides of first grid structure
The source/drain region of transistor, is formed in the second fin of second grid structure both sides and selects MOS transistor
Source/drain region.
The forming method of 13. semiconductor structures as described in claim 8 or 9 or 10, it is characterised in that
While forming first grid structure and control gate, at the second fin sidewall of Semiconductor substrate memory area
With the 3rd grid structure selecting fin formula field effect transistor that top surface forms flash cell.
The forming method of 14. semiconductor structures as claimed in claim 13, it is characterised in that partly lead described
Body substrate carries out ion implanting, forms fin field effect in the first fin of the both sides of first grid structure
The source/drain region of transistor, is formed in the second fin of the 3rd grid structure both sides and selects fin field effect brilliant
The source/drain region of body pipe.
The forming method of 15. semiconductor structures as claimed in claim 10, it is characterised in that remove the first fin
First grid structure in portion, forms the second groove, forms high K in sidewall and the bottom of described second groove
Gate dielectric layer, forms metal gates on high-K gate dielectric layer.
The forming method of 16. semiconductor structures as claimed in claim 15, it is characterised in that described metal gate
Work-function layer it is also formed with between pole and high-K gate dielectric layer.
The forming method of 17. semiconductor structures as claimed in claim 1, it is characterised in that described first mask
The material of layer is silicon nitride, silicon oxynitride, silicon oxide carbide, amorphous carbon or carbon silicon oxynitride.
The forming method of 18. semiconductor structures as claimed in claim 1, it is characterised in that described first mask
The thickness of layer is 300～800 angstroms.
The forming method of 19. semiconductor structures as claimed in claim 1, it is characterised in that described first oxidation
The thickness of silicon layer is 20～60 angstroms.
The forming method of 20. semiconductor structures as claimed in claim 1, it is characterised in that described first polycrystalline
The thickness of silicon layer is 800～1200 angstroms.
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| CN107170686B (en) * | 2016-03-08 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Method for forming fin field effect transistor |
| US9666589B1 (en) * | 2016-03-21 | 2017-05-30 | Globalfoundries Inc. | FinFET based flash memory cell |
| US10840150B2 (en) * | 2017-01-10 | 2020-11-17 | Samsung Electronics Co., Ltd. | Semiconductor device and method for manufacturing the same |
| CN109103102B (en) * | 2017-06-20 | 2021-06-08 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN109979943B (en) * | 2017-12-28 | 2022-06-21 | 联华电子股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN110875186B (en) * | 2018-08-31 | 2023-08-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111383994B (en) * | 2018-12-29 | 2023-02-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111508897A (en) * | 2019-01-31 | 2020-08-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN113808947B (en) * | 2020-06-16 | 2024-03-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112951830B (en) * | 2021-02-01 | 2023-02-07 | 泉芯集成电路制造(济南)有限公司 | Integrated circuit device, memory, and electronic apparatus |
| CN114175232A (en) * | 2021-05-12 | 2022-03-11 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| JP2023553679A (en) * | 2021-05-12 | 2023-12-25 | 長江存儲科技有限責任公司 | Memory peripheral circuit with three-dimensional transistor and method for forming the same |
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