CN107170686B - Method for forming fin field effect transistor - Google Patents
Method for forming fin field effect transistor Download PDFInfo
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- CN107170686B CN107170686B CN201610130609.XA CN201610130609A CN107170686B CN 107170686 B CN107170686 B CN 107170686B CN 201610130609 A CN201610130609 A CN 201610130609A CN 107170686 B CN107170686 B CN 107170686B
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 230000005669 field effect Effects 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 284
- 239000011229 interlayer Substances 0.000 claims abstract description 117
- 239000011241 protective layer Substances 0.000 claims abstract description 65
- 238000005530 etching Methods 0.000 claims abstract description 23
- 230000000149 penetrating effect Effects 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 239000012044 organic layer Substances 0.000 claims description 4
- 229910052582 BN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- -1 copper nitride Chemical class 0.000 claims description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 230000003667 anti-reflective effect Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 238000005520 cutting process Methods 0.000 description 10
- 238000002955 isolation Methods 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method for forming a fin field effect transistor comprises the steps of forming dielectric layer bulges on the interlayer dielectric layers and the side walls between adjacent fin parts and between adjacent grid structures by etching a second interlayer dielectric layer with a part of thickness; forming a protective layer covering the raised surface of the dielectric layer; then forming a flat layer covering the interlayer dielectric layer and the protective layer, and forming a mask layer with a groove pattern opening on the flat layer, wherein the position of the groove pattern opening corresponds to the area between the adjacent grid structures; etching the flat layer and the interlayer dielectric layer downwards by taking the mask layer and the protective layer as masks to form a contact hole penetrating through the interlayer dielectric layer, wherein the bottom of the contact hole is positioned between adjacent grid structures; and removing the mask layer and the flat layer. The method can avoid punch-through between corresponding contact holes on adjacent fin parts in the extending direction of the groove pattern opening.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor.
Background
MOS transistors are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; the gate structure is positioned on the surface of the semiconductor substrate, and the source and drain regions are positioned in the semiconductor substrate on two sides of the gate structure. The operating principle of the MOS transistor is as follows: the switching signal is generated by applying a voltage to the gate structure to regulate current through the bottom channel of the gate structure.
With the development of semiconductor technology, the conventional planar MOS transistor has a weak ability to control channel current, resulting in a serious leakage current. Fin field effect transistors (Fin FETs) are emerging multi-gate devices, and generally include a Fin portion protruding from the surface of a semiconductor substrate, a gate structure covering a portion of the top surface and sidewalls of the Fin portion, and source and drain regions in the Fin portion at both sides of the gate structure.
However, the performance of the finfet formed in the prior art is to be improved.
Disclosure of Invention
The invention provides a method for forming a fin field effect transistor, which avoids punch-through between corresponding contact holes on adjacent fins in the extending direction of a groove pattern opening.
In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, including: providing a semiconductor substrate, wherein a fin part, a grid structure crossing the fin part, side walls positioned on the side walls of the two sides of the grid structure and interlayer dielectric layers covering the grid structure and the side walls are formed on the semiconductor substrate, and the interlayer dielectric layers comprise a first interlayer dielectric layer covering the side walls of the side walls and a second interlayer dielectric layer positioned on the first interlayer dielectric layer, the grid structure and the side walls; etching the second interlayer dielectric layer with partial thickness to form dielectric layer bulges, wherein the dielectric layer bulges are positioned between the adjacent fin parts and above the interlayer dielectric layer and the side wall between the adjacent grid structures; forming a protective layer covering the raised surface of the dielectric layer, and then forming a flat layer covering the interlayer dielectric layer and the protective layer; forming a mask layer with a groove pattern opening on the flat layer, wherein the position of the groove pattern opening corresponds to the area between the adjacent gate structures; etching the flat layer and the interlayer dielectric layer downwards by taking the mask layer and the protective layer as masks to form a contact hole penetrating through the interlayer dielectric layer, wherein the bottom of the contact hole is positioned between adjacent grid structures; and removing the mask layer and the flat layer.
Optionally, the step of forming the protective layer comprises: forming a protective layer on the surface of the interlayer dielectric layer and the surface of the protrusion of the dielectric layer; and removing the protective layer positioned on the surface of the interlayer dielectric layer outside the raised surface of the dielectric layer.
Optionally, the process for forming the protective layer is an atomic layer deposition process, a plasma chemical vapor deposition process, or a sub-atmospheric pressure chemical vapor deposition process.
Optionally, the process of removing the protective layer on the surface of the interlayer dielectric layer outside the raised surface of the dielectric layer is a dry etching process.
Optionally, the thickness of the protective layer is 120 angstroms to 180 angstroms.
Optionally, the protective layer is made of titanium nitride, copper nitride, boron nitride, or aluminum nitride.
Optionally, the height of the protrusion of the dielectric layer is 400-700 angstroms.
Optionally, the material of the planarization layer is a carbon-containing organic layer or a bottom anti-reflection layer.
Optionally, the interlayer dielectric layer is made of silicon oxide, silicon oxynitride or silicon oxycarbide.
Optionally, the process of etching the planarization layer and the interlayer dielectric layer downward to form the contact hole is an anisotropic dry etching process.
Optionally, the method further includes: and filling the contact hole with a conductive layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
after the second interlayer dielectric layer with partial thickness is etched, dielectric layer protrusions are formed above the interlayer dielectric layers and the side walls between the adjacent fin parts and between the adjacent grid structures, then protective layers are formed on the surfaces of the dielectric layer protrusions, namely protective layers are formed on the top surfaces of the dielectric layer protrusions and on the side walls of the dielectric layer protrusions, so that the protective layers enhance the protective effect on the interlayer dielectric layers covered by the protective layers, after the flat layers and the mask layers are formed, in the process of etching the flat layers and the interlayer dielectric layers downwards by taking the mask layers and the protective layers as masks, the etching degree of the interlayer dielectric layers below the protective layers can be reduced, and therefore the situation that the corresponding contact holes on the adjacent fin parts are penetrated in the extending direction of the groove pattern opening is avoided, and after a conductive layer is formed in the contact holes, short circuits between corresponding conductive layers on adjacent fins in the extending direction of the trench pattern openings can be avoided.
Drawings
Fig. 1, fig. 2a, fig. 2b, fig. 3a, fig. 3b, fig. 4a, fig. 4b, fig. 5a, fig. 5b, fig. 6a, fig. 6b, fig. 7a and fig. 7b are schematic structural diagrams of a finfet formation process in the prior art;
fig. 8, 9a, 9b, 9c, 10a, 10b, 10c, 11a, 11b, 11c, 12a, 12b, 12c, 13a, 13b, 13c, 14a, 14b, 14c, 15a, 15b, and 15c are schematic structural diagrams of a finfet formation process according to the first embodiment of the present invention.
Detailed Description
As described in the background, the performance of the finfet formed by the prior art is expected to improve.
Fig. 1, 2a, 2b, 3a, 3b, 4a, 4b, 5a, 5b, 6a, 6b, 7a and 7b are schematic structural diagrams of a finfet formation process in the prior art.
Referring to fig. 1, fig. 2a and fig. 2B in combination, fig. 2a is a cross-sectional view taken along a cutting line a-a1 in fig. 1, and fig. 2B is a cross-sectional view taken along a cutting line B-B1 in fig. 1, wherein a direction of the cutting line a-a1 is parallel to an extending direction of the fins and passes through the fins, and a direction of the cutting line B-B1 is parallel to the extending direction of the fins and is located between adjacent fins, so as to provide a semiconductor substrate 100, and fins 120 and dummy gate structures 130 crossing the fins 120 are formed on the semiconductor substrate 100.
Isolation structures 110 are further formed on the semiconductor substrate 100 between the adjacent fins 120 for electrically isolating the adjacent fins 120; the dummy gate structure 130 includes a gate dielectric layer 131 crossing the fin 120 and a dummy gate electrode 132 on the gate dielectric layer 131, wherein the gate dielectric layer 131 is located on the surface of the isolation structure 110 and covers a portion of the top surface and the sidewall of the fin 120.
With reference to fig. 3a and fig. 3b, forming spacers 140 on sidewalls of two sides of the dummy gate structure 130; after source and drain regions (not shown) are formed in the dummy gate structure 130 and the fin portions on the two sides of the sidewall 140, a first interlayer dielectric layer 150 covering the sidewall of the sidewall 140 is formed on the semiconductor substrate 100, and the surface of the first interlayer dielectric layer 150 is flush with the top surface of the dummy gate structure 130.
With combined reference to fig. 4a and 4b, after removing the dummy gate electrode 132, an opening (not shown) is formed, and then a metal gate electrode 133 is formed in the opening; forming a second interlayer dielectric layer 160 covering the metal gate electrode 133, the sidewall spacers 140 and the first interlayer dielectric layer 150; a protective material layer 170 is formed overlying the second interlayer dielectric layer 160. The metal gate electrode 133 and the gate dielectric layer 131 form a gate structure; the first interlayer dielectric layer 150 and the second interlayer dielectric layer 160 form an interlayer dielectric layer.
Referring to fig. 5a and 5b in combination, the protective material layer 170 is etched to form a protective layer 171, where the protective layer 171 is located above the interlayer dielectric layer between adjacent fins 120 and between adjacent gate structures. The over-etching may be performed during the etching of the protective material layer 170, so that a portion of the thickness of the second interlayer dielectric layer 160 is also etched.
With combined reference to fig. 6a and 6b, a planarization layer 180 is formed covering the interlayer dielectric layer and the protection layer 171; a mask layer 190 with a trench pattern opening is formed on the planarization layer 180, the trench pattern opening being located above the interlevel dielectric layer between adjacent gate structures and crossing over the protection layer 171.
With reference to fig. 7a and 7b, the mask layer 190 and the protection layer 171 are used as masks to etch the planarization layer 180 and the interlayer dielectric layer downward, so as to form a contact hole 191 penetrating through the interlayer dielectric layer, wherein the bottom of the contact hole 191 is located between adjacent gate structures.
A conductive layer is then formed in the contact hole 191.
Research shows that in the fin field effect transistor formed by the method, in the extending direction of the trench pattern opening, the corresponding contact holes on the adjacent fins are easy to punch through, so that the corresponding conductive layers on the adjacent fins are short-circuited, and the reason is as follows:
etching the protective material layer 170 to form a protective layer 171, wherein the protective layer 171 is located between the adjacent fins 120 and above the interlayer dielectric layer between the adjacent gate structures, at this time, the protective layer 171 is only located on the top surface of the interlayer dielectric layer which is projected and covered downwards by the protective layer 171 and the mask layer 190, the protective layer 171 is used as a mask to etch the flat layer 180 and the interlayer dielectric layer downwards to form the contact holes 191 penetrating through the interlayer dielectric layer, the etching degree of the top of the interlayer dielectric layer between the contact holes 191 in the extending direction of the trench pattern opening is larger, and no corresponding protective layer for reducing the etching degree of the interlayer dielectric layer between the contact holes 191 in the extending direction of the trench pattern opening is provided on the sidewall of the interlayer dielectric layer between the contact holes 191, so that the corresponding contact holes on the adjacent fins in the extending direction of the trench pattern opening are easily penetrated, after the conductive layers are formed in the contact holes, short circuits are easy to occur between the corresponding conductive layers on the adjacent fin parts in the extending direction of the groove pattern opening.
On the basis, the invention provides a method for forming a fin field effect transistor, wherein dielectric layer bulges are formed on the interlayer dielectric layers and the side walls between the adjacent fin parts and between the adjacent grid electrode structures by etching the second interlayer dielectric layer with partial thickness; forming a protective layer covering the raised surface of the dielectric layer, and then forming a flat layer covering the interlayer dielectric layer and the protective layer; forming a mask layer with a groove pattern opening on the flat layer, wherein the position of the groove pattern opening corresponds to the area between the adjacent gate structures; etching the flat layer and the interlayer dielectric layer downwards by taking the mask layer and the protective layer as masks to form a contact hole penetrating through the interlayer dielectric layer, wherein the bottom of the contact hole is positioned between adjacent grid structures; and removing the mask layer and the flat layer. The method can avoid punch-through between corresponding contact holes on adjacent fins in the extending direction of the groove pattern opening.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
First embodiment
Fig. 8, 9a, 9b, 9c, 10a, 10b, 10c, 11a, 11b, 11c, 12a, 12b, 12c, 13a, 13b, 13c, 14a, 14b, 14c, 15a, 15b, and 15c are schematic structural diagrams of a finfet formation process according to the first embodiment of the present invention.
With combined reference to fig. 8, 9a, 9B and 9C, fig. 9a is a cross-sectional view taken along a cutting line a2-A3 in fig. 8, fig. 9B is a cross-sectional view taken along a cutting line B2-B3 in fig. 8, and fig. 9C is a cross-sectional view taken along a cutting line C2-C3 in fig. 8, wherein a direction of the cutting line a-a1 is parallel to a fin extending direction and passes through the fin, a direction of the cutting line B-B1 is parallel to the fin extending direction and is located between adjacent fins, and a cutting line C2-C3 is parallel to a gate structure extending direction and is located between adjacent gate structures, so as to provide a semiconductor substrate 200 on which the fin 220 and the dummy gate structure 230 crossing the fin 220 are formed.
The semiconductor substrate 200 provides a process platform for the subsequent formation of semiconductor devices. The semiconductor substrate 200 may be single crystal silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 200 may be a semiconductor material such as silicon, germanium, silicon germanium, or gallium arsenide; in this embodiment, the material of the semiconductor substrate 200 is silicon.
The fin portion 220 is formed by patterning the semiconductor substrate 200, or a fin portion material layer is formed on the semiconductor substrate 200 and then patterned to form the fin portion 220.
The surface of the semiconductor substrate 200 on both sides of the fin portion 220 further has an isolation structure 210, the surface of the isolation structure 210 is lower than the top surface of the fin portion 220, and the isolation structure 210 is used for electrically isolating the fin portion 220. The material of the isolation structure 210 includes silicon oxide or silicon oxynitride.
The dummy gate structure 230 spans the fin 220 and covers a portion of a top surface and sidewalls of the fin 220. The dummy gate structure 230 includes a gate dielectric layer 231 crossing the fin 220 and a dummy gate electrode 232 covering the gate dielectric layer 231. The gate dielectric layer 231 is located on the surface of the isolation structure 210 and covers a portion of the top surface and the sidewall of the fin 220.
In this embodiment, the gate dielectric layer 231 is made of a high-K dielectric material, such as HfO2、HfSiON、HfAlO2、ZrO2Or Al2O3The dummy gate electrode 232 is made of polysilicon, and the dummy gate electrode 232 is removed later. In other embodiments, it may also be: the gate dielectric layer 231 is made of silicon oxide, the dummy gate electrode 232 is made of polysilicon, and the gate dielectric layer 231 and the dummy gate electrode 232 need to be removed subsequently.
The method for forming the dummy gate structure 230 includes: forming a gate dielectric material layer (not shown) covering the semiconductor substrate 200, the fin 220 and the isolation structure 210 and a dummy gate electrode material layer (not shown) covering the gate dielectric material layer by using a deposition process; the dummy gate electrode material layer and the gate dielectric material layer are patterned to form a dummy gate structure 230.
With reference to fig. 10a, 10b and 10c, forming a sidewall spacer 240 covering sidewalls of two sides of the dummy gate structure 230; forming source and drain regions (not labeled) in the dummy gate structure 230 and the fin portion 220 on both sides of the sidewall spacer 240; after the source and drain regions are formed, a first interlayer dielectric layer 250 covering the side wall of the side wall 240 is formed on the semiconductor substrate 200, and the surface of the first interlayer dielectric layer 250 is flush with the top surface of the dummy gate structure 230.
The first interlayer dielectric layer 250 is made of silicon oxide, silicon oxynitride or silicon oxycarbide.
The steps of forming the first interlayer dielectric layer 250 are: forming a first interlayer dielectric material layer (not shown) covering the fin 220, the dummy gate structure 230, the isolation structure 210, the sidewall spacers 240 and the semiconductor substrate 200, wherein the entire surface of the first interlayer dielectric material layer is higher than the top surface of the dummy gate structure 230; the first interlayer dielectric material layer is planarized until the top surface of the dummy gate structure 230 is exposed, forming a first interlayer dielectric layer 250.
With combined reference to fig. 11a, 11b, and 11c, the dummy gate electrode 232 is removed to form an opening (not shown); then, a metal gate electrode 233 is formed in the opening; and forming a second interlayer dielectric layer 260 covering the metal gate electrode 233, the sidewall spacers 240 and the first interlayer dielectric layer 250.
The dummy gate electrode 232 is etched and removed by using a dry etching process or a wet etching process. In this embodiment, a tetramethylammonium hydroxide solution is used to remove the dummy gate electrode 232.
The method of forming the metal gate electrode 233 is: and forming a metal gate electrode 233 on the surface of the opening and the first interlayer dielectric layer 250 by using a deposition process, and then removing the metal gate electrode 233 higher than the surface of the first interlayer dielectric layer 250 by using a planarization process, thereby forming the metal gate electrode 233 in the opening.
The second interlayer dielectric layer 260 is made of silicon oxide, silicon oxynitride or silicon oxycarbide, and the process for forming the second interlayer dielectric layer 260 is a deposition process, such as a plasma chemical vapor deposition process or an atmospheric pressure chemical vapor deposition process.
In this embodiment, the metal gate electrode 233 and the gate dielectric layer 231 form a gate structure; the second interlayer dielectric layer 260 and the first interlayer dielectric layer 250 form an interlayer dielectric layer.
With reference to fig. 12a, 12b and 12c, the second interlayer dielectric layer 260 is etched by a certain thickness to form a dielectric layer protrusion 261, where the dielectric layer protrusion 261 is located between adjacent fins 220 and above the interlayer dielectric layer and the sidewall spacers 240 between adjacent gate structures.
Specifically, a patterned mask layer is formed on the surface of the second interlayer dielectric layer 260, the patterned mask layer defines the position of a dielectric layer protrusion 261 to be formed, and the second interlayer dielectric layer 260 with a partial thickness is etched by using the patterned mask layer as a mask to form the dielectric layer protrusion 261.
The height of the dielectric layer protrusion 261 needs to be selected within a proper range, if the height of the dielectric layer protrusion 261 is smaller than 400 angstroms, the height of a subsequently formed protective layer on the side wall of the dielectric layer protrusion 261 is smaller, namely the protective effect of the subsequently formed protective layer on the covered interlayer dielectric layer is weakened, and in the subsequent process of forming the contact hole, the contact hole cannot be effectively prevented from being penetrated along the extending direction of the groove pattern opening; if the height of the dielectric layer protrusion 261 is greater than 700 angstroms, the process cost is increased, and therefore, in this embodiment, the height of the dielectric layer protrusion 261 is selected to be 400 angstroms to 700 angstroms.
With combined reference to fig. 13a, 13b and 13c, a protective layer 270 is formed to cover the surface of the dielectric layer protrusion 261.
The material of the protection layer 270 is titanium nitride, copper nitride, boron nitride or aluminum nitride.
The steps of forming the protective layer 270 are: forming a protective layer 270 on the surfaces of the interlayer dielectric layer and the dielectric layer protrusion 261; the dielectric layer is positioned outside the surface of the bulge 261The protective layer 270 on the surface of the interlayer dielectric layer is removed. Specifically, in this embodiment, a deposition process, such as a plasma chemical vapor deposition process, a sub-atmospheric pressure chemical vapor deposition process, or an atomic layer deposition process, is adopted to form the protective layer 270 on the surfaces of the second interlayer dielectric layer 260 and the dielectric layer protrusion 261, then a dry etching process is adopted to remove the protective layer 270 on the surface of the second interlayer dielectric layer 260 except the surface of the dielectric layer protrusion 261, and the etching gas may use C4F6And Cl2Or C4F8And Cl2。
If the protective layer 270 is not formed on the sidewall of the dielectric layer protrusion 261, the top of the interlayer dielectric layer covered downward by the protective layer 270 is subjected to a large etching loss in the subsequent contact hole forming process, which easily causes punch-through between contact holes in the extending direction of the subsequently formed trench pattern opening, but in this embodiment, the protective layer 270 is formed on the surface of the dielectric layer protrusion 261, that is, the protective layer 270 is formed on the sidewall of the dielectric layer protrusion 261 as well as on the top surface of the dielectric layer protrusion 261, so that the protective effect on the interlayer dielectric layer covered by the protective layer 270 is increased.
The thickness of the protective layer 270 needs to be selected within a proper range, and if the thickness of the protective layer 270 is less than 120 angstroms, the protective layer 270 is easily consumed and removed in the process of forming the contact hole, so that the protective effect of the protective layer 270 on the covered interlayer dielectric layer is reduced; if the thickness of the protection layer 270 is greater than 180 angstroms, the positions for forming contact holes on the fin portion are too much in the extending direction of the subsequently formed trench pattern opening, which is not favorable for forming contact holes. Therefore, in this embodiment, the thickness of the passivation layer 270 is selected to be 120 to 180 angstroms.
With combined reference to fig. 14a, 14b and 14c, a planarization layer 280 is formed to cover the interlayer dielectric layer and the protection layer 270, and a mask layer 290 having a trench pattern opening 291 is formed on the planarization layer 280, wherein the trench pattern opening 291 corresponds to an area between adjacent gate structures.
Specifically, the trench pattern opening 291 is located on an interlayer dielectric layer between adjacent gate structures and crosses the protection layer 270.
The material of the planarization layer 280 is a carbon-containing organic layer or a bottom anti-reflective layer (BARC). The process of forming the planarization layer 280 is a spin-on process.
In this embodiment, the mask layer 290 is made of photoresist, and if the planarization layer 280 is made of a carbon-containing organic layer, a bottom anti-reflection layer may be further formed between the planarization layer 280 and the mask layer 290.
The trench pattern opening 291 is located at a position where a contact hole to be formed is formed.
With reference to fig. 15a, 15b and 15c, the mask layer 290 and the protection layer 270 are used as masks to etch the planarization layer 280 and the interlayer dielectric layer downward, so as to form a contact hole 292 penetrating through the interlayer dielectric layer, wherein the bottom of the contact hole 292 is located between adjacent gate structures.
The process of etching the planarization layer 280 and the interlayer dielectric layer downward to form the contact hole 292 is an anisotropic dry etching process, such as an anisotropic plasma etching process or a reactive ion etching process. In this embodiment, the planarization layer 280 and the interlayer dielectric layer are etched downward by using an anisotropic plasma etching process until the top surface of the fin portion 220 is exposed, so as to form a contact hole 292, wherein the bottom of the contact hole 292 is located between adjacent gate structures.
The protective layer 270 is formed on the top surface of the dielectric layer protrusion 261 and on the side wall of the dielectric layer protrusion 261, so that the protective effect on the interlayer dielectric layer covered by the protective layer 270 is increased, the etching degree of the interlayer dielectric layer below the protective layer 270 can be reduced in the process of forming the contact hole 292, and the contact holes 292 corresponding to the adjacent fins 220 are prevented from being penetrated in the extending direction of the groove pattern opening 291.
After the contact hole 292 is formed, the mask layer 290 and the planarization layer 280 are removed.
The mask layer 290 and the planarization layer 280 are removed, and the contact hole 292 is filled with a conductive layer.
The material of the conducting layer is metal, such as tungsten or copper. The process of forming the conductive layer may be a physical vapor deposition process.
Since no punch-through occurs between the corresponding contact holes 292 of the adjacent fins 220 in the extending direction of the trench pattern opening 291, the conductive layer filled in the adjacent contact holes 292 is shorted in the extending direction of the trench pattern opening 291.
Second embodiment
The second embodiment differs from the first embodiment in that: the second embodiment describes a forming process of a fin field effect transistor of a front gate process, and on the basis of the first embodiment, after a pseudo gate structure is formed, the pseudo gate structure cannot be removed, the pseudo gate structure forms a gate structure, and then side walls covering two side walls of the gate structure are formed; forming source and drain regions in the grid structure and the fin parts on two sides of the side wall; and after the source drain region is formed, forming an interlayer dielectric layer covering the grid structure and the side wall on the semiconductor substrate, wherein the whole surface of the interlayer dielectric layer is higher than the top surface of the pseudo grid structure.
For convenience of description, the interlayer dielectric layer is divided into a first interlayer dielectric layer and a second interlayer dielectric layer, the first interlayer dielectric layer covers the side wall of the side wall, the surface of the first interlayer dielectric layer is flush with the top surface of the gate structure, and the second interlayer dielectric layer is located on the gate structure, the side wall and the first interlayer dielectric layer.
And etching the second interlayer dielectric layer with partial thickness to form dielectric layer bulges, wherein the dielectric layer bulges are positioned between the adjacent fin parts and above the interlayer dielectric layer and the side wall between the adjacent grid structures.
The method for forming the dielectric layer protrusion is described with reference to the first embodiment and will not be described in detail.
And then, after forming a protective layer covering the raised surface of the dielectric layer, forming a flat layer covering the interlayer dielectric layer and the protective layer.
The method for forming the protective layer and the planarization layer is described with reference to the first embodiment and will not be described in detail.
And then, forming a mask layer with a groove pattern opening on the flat layer, wherein the position of the groove pattern opening corresponds to the area between the adjacent gate structures.
Specifically, the groove pattern opening is located on an interlayer dielectric layer between adjacent gate structures and stretches across the protective layer.
The method for forming the mask layer is described with reference to the first embodiment and will not be described in detail.
And then, downwards etching the flat layer and the interlayer dielectric layer by taking the mask layer and the protective layer as masks to form a contact hole penetrating through the interlayer dielectric layer, wherein the bottom of the contact hole is positioned between adjacent gate structures.
The method for forming the contact hole refers to the first embodiment and is not described in detail.
And after the contact hole is formed, removing the mask layer and the flat layer, and then filling a conducting layer in the contact hole.
The method of forming the conductive layer is described with reference to the first embodiment and will not be described in detail.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A method for forming a fin field effect transistor (FinFET), comprising:
providing a semiconductor substrate, wherein a fin part, a grid structure crossing the fin part, side walls positioned on the side walls of the two sides of the grid structure and interlayer dielectric layers covering the grid structure and the side walls are formed on the semiconductor substrate, and the interlayer dielectric layers comprise a first interlayer dielectric layer covering the side walls of the side walls and a second interlayer dielectric layer positioned on the first interlayer dielectric layer, the grid structure and the side walls;
etching the second interlayer dielectric layer with partial thickness to form dielectric layer bulges, wherein the dielectric layer bulges are positioned between the adjacent fin parts and above the interlayer dielectric layer and the side wall between the adjacent grid structures;
forming a protective layer covering the top and the side wall surface of the protrusion of the dielectric layer, and forming a flat layer covering the interlayer dielectric layer and the protective layer;
forming a mask layer with a groove pattern opening on the flat layer, wherein the position of the groove pattern opening corresponds to the area between the adjacent gate structures;
etching the flat layer and the interlayer dielectric layer downwards by taking the mask layer and the protective layer as masks to form a contact hole penetrating through the interlayer dielectric layer, wherein the bottom of the contact hole is positioned between adjacent grid structures;
and removing the mask layer and the flat layer.
2. The method of claim 1, wherein the step of forming the protective layer comprises:
forming a protective layer on the surface of the interlayer dielectric layer and the surface of the protrusion of the dielectric layer;
and removing the protective layer positioned on the surface of the interlayer dielectric layer outside the raised surface of the dielectric layer.
3. The method of claim 2, wherein the process for forming the protective layer is an atomic layer deposition process, a plasma chemical vapor deposition process, or a sub-atmospheric pressure chemical vapor deposition process.
4. The method of claim 2, wherein the step of removing the protective layer on the surface of the interlayer dielectric layer outside the raised surface of the dielectric layer is a dry etching process.
5. The method of claim 1, wherein the protective layer has a thickness of 120-180 angstroms.
6. The method of claim 1, wherein the protective layer is formed of titanium nitride, copper nitride, boron nitride, or aluminum nitride.
7. The method of claim 1, wherein the dielectric layer protrusion has a height of 400-700 angstroms.
8. The method of claim 1, wherein the planarization layer is formed from a carbon-containing organic layer or a bottom anti-reflective layer.
9. The method of claim 1, wherein the interlayer dielectric layer is formed of silicon oxide, silicon oxynitride, or silicon oxycarbide.
10. The method of claim 1, wherein the step of etching the planarization layer and the interlayer dielectric layer downward to form the contact hole is an anisotropic dry etching process.
11. The method of claim 1, further comprising: and filling the contact hole with a conductive layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103839818A (en) * | 2012-11-25 | 2014-06-04 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN104022036A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin type field effect transistor |
| CN104124210A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN105225950A (en) * | 2014-05-29 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | The formation method of fin formula field effect transistor, the formation method of MOS transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103839818A (en) * | 2012-11-25 | 2014-06-04 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN104022036A (en) * | 2013-02-28 | 2014-09-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of fin type field effect transistor |
| CN104124210A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN105225950A (en) * | 2014-05-29 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | The formation method of fin formula field effect transistor, the formation method of MOS transistor |
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