CN117153787A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN117153787A
CN117153787A CN202210565372.3A CN202210565372A CN117153787A CN 117153787 A CN117153787 A CN 117153787A CN 202210565372 A CN202210565372 A CN 202210565372A CN 117153787 A CN117153787 A CN 117153787A
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CN
China
Prior art keywords
layer
device region
forming
work function
channel
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CN202210565372.3A
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Chinese (zh)
Inventor
殷立强
陈子钊
崇二敏
张海洋
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210565372.3A priority Critical patent/CN117153787A/en
Publication of CN117153787A publication Critical patent/CN117153787A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, wherein the substrate comprises a first device region and a second device region which are adjacent, a channel structure layer is suspended on the top of the substrate of the first device region and the second device region along the normal direction of the surface of the substrate, and the channel structure layer comprises one or more channel layers which are arranged at intervals in the longitudinal direction; forming a gate dielectric layer and a work function layer surrounding and covering the gate dielectric layer on part of the top, part of the side wall and part of the bottom of the channel layer; filling a sacrificial layer covering the work function layer in a space position opposite to the adjacent channel layer and a space position opposite to the channel layer and the substrate in the first device region; forming a shielding layer covering the top and the side wall of the work function layer and the side wall of the sacrificial layer on the substrate exposed by the channel structure layer; removing the shielding layer, the sacrificial layer and the work function layer of the first device region; and removing the shielding layer of the second device region. The performance of the semiconductor structure is improved.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor transistors are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor transistors, and therefore, as the element density and integration level of the semiconductor transistors are increased, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.
To better accommodate the demands of transistor scaling, semiconductor processes are gradually beginning to transition from planar transistors to three-dimensional transistors with higher power, such as fin field effect transistors (finfets), gate-all-around (GAA) transistors, and the like. Wherein the fully-enclosed gate transistors include vertical fully-enclosed gate transistors and horizontal fully-enclosed gate transistors. In the fully-enclosed gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.
As device dimensions shrink further, it becomes increasingly difficult and challenging to improve the performance of fully surrounding gate structure devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which is beneficial to further improving the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device region and a second device region which are adjacent, a channel structure layer is suspended on the top of the substrate of the first device region and the second device region along the normal direction of the surface of the substrate, and the channel structure layer comprises one or more channel layers which are arranged at intervals in the longitudinal direction; forming a gate dielectric layer and a work function layer surrounding and covering the gate dielectric layer on part of the top, part of the side wall and part of the bottom of the channel layer; filling a sacrificial layer covering the work function layer in a space position opposite to the adjacent channel layer and a space position opposite to the channel layer and the substrate in the first device region; forming a shielding layer covering the top and the side wall of the work function layer and the side wall of the sacrificial layer on the substrate exposed by the channel structure layer; removing the shielding layer, the sacrificial layer and the work function layer of the first device region; and removing the shielding layer, the sacrificial layer and the work function layer of the first device region, and then removing the shielding layer of the second device region.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a method for forming a semiconductor structure, wherein a sacrificial layer covering a work function layer is filled in a space position opposite to an adjacent channel layer and a space position opposite to a substrate, namely, the space position opposite to the channel layer and the substrate and the space position opposite to the adjacent channel layer are occupied by the sacrificial layer, so that in the step of forming a shielding layer in a first device region and a second device region, the probability of forming the shielding layer in the space position opposite to the channel layer and the substrate and the space position opposite to the adjacent channel layer is reduced, correspondingly, in the step of removing the shielding layer in the first device region, the shielding layer in the first device region can be removed completely through a one-time etching process, the probability of excessively consuming the shielding layer in the second device region is reduced, the risk of exposing the shielding layer in the second device region is reduced, and in the step of removing the work function layer in the first device region, the probability of damaging the work function layer in the second device region is reduced, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 6 are schematic structural views of a semiconductor structure;
fig. 7 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of current semiconductor structures is to be improved. The reasons for the improvement in performance are now analyzed in connection with a semiconductor structure.
Fig. 1 to 6 are schematic structural views corresponding to a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, the substrate 10 includes adjacent first and second device regions 10A and 10B, a channel structure layer 16 is suspended on top of the substrate 10 of the first and second device regions 10A and 10B along a surface normal direction of the substrate 10, the channel structure layer 16 includes one or more channel layers 15 disposed at intervals in a longitudinal direction, a gate dielectric layer 18 is formed on a part of a top, a part of a side wall and a part of a bottom of the channel layer 15, and a work function layer 19 surrounding the gate dielectric layer 18 is formed.
Referring to fig. 2, a blocking layer 20 covering the work function layer 19 is formed on the substrate 10 where the channel structure layer 16 is exposed.
Referring to fig. 3, in the first device region 10A, the shielding layer 20 of the sidewall of the channel structure layer 16 is removed.
Referring to fig. 4, after removing the shielding layer 20 of the sidewall of the channel structure layer 16, in the first device region 10A, the shielding layer 20 is removed in a spatial position facing the adjacent channel layer 15 and a spatial position facing the channel layer 15 with the substrate 10.
Referring to fig. 5, the work function layer 19 of the first device region 10A is removed.
Referring to fig. 6, after removing the work function layer 19 of the first device region 10A, the shielding layer 20 of the second device region 10B is removed.
After the removal of the shielding layer 20 on the sidewall of the channel structure layer 16, it is found that, in the first device region 10A, in the process of removing the shielding layer 20 located in a spatial position opposite to the adjacent channel layer 15 and in a spatial position opposite to the substrate 10 of the channel layer 15, the etching process adopted easily causes excessive consumption of the shielding layer 20 of the second device region 10B, and accordingly, the risk that the work function layer 19 in the second device region 10B is exposed is increased, and in the subsequent step of removing the work function layer 19 of the first device region 10A, the probability that the work function layer 19 in the second device region 10B is damaged is increased, thereby affecting the performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device region and a second device region which are adjacent, a channel structure layer is suspended on the top of the substrate of the first device region and the second device region along the normal direction of the surface of the substrate, and the channel structure layer comprises one or more channel layers which are arranged at intervals in the longitudinal direction; forming a gate dielectric layer and a work function layer surrounding and covering the gate dielectric layer on part of the top, part of the side wall and part of the bottom of the channel layer; filling a sacrificial layer covering the work function layer in a space position opposite to the adjacent channel layer and a space position opposite to the channel layer and the substrate in the first device region; forming a shielding layer covering the top and the side wall of the work function layer and the side wall of the sacrificial layer on the substrate exposed by the channel structure layer; removing the shielding layer, the sacrificial layer and the work function layer of the first device region; and removing the shielding layer, the sacrificial layer and the work function layer of the first device region, and then removing the shielding layer of the second device region.
The embodiment of the invention provides a method for forming a semiconductor structure, wherein a sacrificial layer covering a work function layer is filled in a space position opposite to an adjacent channel layer and a space position opposite to a substrate, namely, the space position opposite to the channel layer and the substrate and the space position opposite to the adjacent channel layer are occupied by the sacrificial layer, so that in the step of forming a shielding layer in a first device region and a second device region, the probability of forming the shielding layer in the space position opposite to the channel layer and the substrate and the space position opposite to the adjacent channel layer is reduced, correspondingly, in the step of removing the shielding layer in the first device region, the shielding layer in the first device region can be removed completely through a one-time etching process, the probability of excessively consuming the shielding layer in the second device region is reduced, the risk of exposing the shielding layer in the second device region is reduced, and in the step of removing the work function layer in the first device region, the probability of damaging the work function layer in the second device region is reduced, and the performance of the semiconductor structure is improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 7 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 7, a substrate (not shown) is provided, the substrate including adjacent first and second device regions 100A and 100B, and a channel structure layer 106 is suspended on top of the substrate of the first and second device regions 100A and 100B along a direction normal to a surface of the substrate, the channel structure layer 106 including one or more channel layers 105 spaced apart in a longitudinal direction.
The substrate is used for providing a process platform for the subsequent process.
In this embodiment, the base is a three-dimensional structure, and the base includes a substrate 100 and a fin 101 on the substrate 100 separated from the first device region 100A and the second device region 100B. In other embodiments, the base may also be a planar substrate 100. In this embodiment, the substrate 100 is a silicon substrate 100. In other embodiments, the substrate 100 may also be a silicon germanium bond.
In this embodiment, the material of the fin 101 is the same as that of the substrate 100, and the material of the fin 101 is silicon.
In this embodiment, the first device region 100A is used to form a first type transistor, the second device region 100B is used to form a second type transistor, and the channel conductivity types of the first type transistor and the second type transistor are different. Specifically, the first type transistor is an NMOS transistor, and the second type transistor is a PMOS transistor; in other embodiments, the first type transistor is a PMOS transistor and the second type transistor is an nmos transistor.
The channel layer 105 serves as a conductive channel for the first device region 100A and the second device region 100B.
In this embodiment, the first type transistor and the second type transistor are all surrounding gate transistors, and thus the channel layer 105 is disposed at intervals from the substrate in the longitudinal direction.
In this embodiment, the material of channel layer 105 includes one or more of silicon, silicon germanium, and a group iii-v semiconductor material. Wherein the channel layer 105 material of the first device region 100A is dependent on the properties of the first type transistor and the channel layer 105 material of the second device region 100B is dependent on the properties of the second type transistor. As an example, the material of the channel layer 105 of the first device region 100A and the second device region 100B is silicon.
In this embodiment, the number of channel layers 105 is three. In other embodiments, the number of channel layers 105 may also be other numbers.
In this embodiment, the method for forming a semiconductor structure further includes: before forming the channel structure layer 106, an isolation layer 102 is formed on the substrate 100 where the fin 101 is exposed, the isolation layer 102 covering the sidewalls of the fin 101.
The isolation layer 102 serves to isolate adjacent first device regions 100A and second device regions 100B. For this purpose, the material of the isolation layer 102 is a dielectric material, and the material of the isolation layer 102 may include silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the isolation layer 102 is silicon oxide.
In this embodiment, in the step of providing the substrate, an interlayer dielectric layer (not shown) covering the channel structure layer 106 is further formed on the substrate, and a gate opening 107 is formed in the interlayer dielectric layer and spans the channel structure layer 106, and the gate opening 107 exposes a portion of the top and a portion of the sidewall of the channel structure layer 106.
The interlayer dielectric layer is used for isolating adjacent devices. The interlayer dielectric layer is made of insulating materials, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer is made of silicon oxide.
In this embodiment, the gate opening 107 provides a process window for a subsequent process.
Referring to fig. 8, a gate dielectric layer 108, and a work function layer 109 surrounding and covering the gate dielectric layer 108 are formed on a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer 105.
The gate dielectric layer 108 is used to reduce the probability of leakage current generated by the semiconductor device, thereby improving the reliability of the semiconductor device.
In this embodiment, in the step of forming the gate dielectric layer 108, the gate dielectric layer 108 is formed on a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer 105 exposed by the gate opening 107.
In this embodiment, the material of the gate dielectric layer 108 includes HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following.
Specifically, gate dielectric layer 108 includes a gate oxide layer conformally covering a portion of the top, a portion of the sidewalls, and a portion of the bottom of channel layer 105, and a high-k gate dielectric layer 108 conformally covering the gate oxide layer. The material of the high-k gate dielectric layer 108 is a high-k dielectric material, and the high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.
In this embodiment, the process of forming the gate dielectric layer 108 includes an atomic layer deposition process.
The work function layer 109 is used to adjust the threshold voltage of the second type transistor.
In this embodiment, the material of the work function layer 109 includes one or more of TiN, taN, tiAl, tiSiN and TiAlC. The particular material of work function layer 109 depends, among other things, on the properties of the second type transistor.
In this embodiment, the process of forming the work function layer 109 includes an atomic layer deposition process.
Referring to fig. 9, in the first device region 100A, a sacrificial layer 112 covering the work function layer 109 is filled in a space position where adjacent channel layers 105 face each other and a space position where the channel layers 105 face the substrate.
It should be noted that, the space positions opposite to the adjacent channel layer 105 and the space positions opposite to the substrate are filled with the sacrificial layer 112 covering the work function layer 109, that is, the space positions opposite to the channel layer 105 and the substrate and the space positions opposite to the adjacent channel layer 105 are occupied by the sacrificial layer 112, so that in the subsequent step of forming the shielding layer in the first device region 100A and the second device region 100B, the probability of forming the shielding layer in the space positions opposite to the channel layer 105 and the space positions opposite to the adjacent channel layer 105 is reduced, and correspondingly, in the subsequent step of removing the shielding layer in the first device region 100A, the shielding layer in the first device region 100A can be completely removed through one etching process, the probability of excessively consuming the shielding layer in the second device region 100B is reduced, thereby reducing the risk of exposing the shielding layer 109 in the second device region 100B, and in the subsequent step of removing the layer 109 in the first device region 100A, the probability of damaging the work function layer 109 in the second device region 100B is also reduced, and the performance of the semiconductor structure is further improved.
In this embodiment, the step of filling the sacrificial layer 112 covering the work function layer 109 in the spatial position where the adjacent channel layer 105 faces, and the spatial position where the channel layer 105 faces the substrate includes: a sacrificial layer 112 is formed on the exposed top surface of the substrate of the channel structure layer 106, the top, side walls and bottom of the channel layer 106, and the sacrificial layer 112 circumferentially covers the work function layer 109.
The thickness of the sacrificial layer 112 on the sidewall of the channel layer 105 should not be too large or too small. If the thickness of the sacrificial layer 112 on the sidewall of the channel layer 105 is too large, the process difficulty of removing the sacrificial layer 112 is increased and the process efficiency of the semiconductor manufacturing process is reduced in the subsequent removal of the sacrificial layer 112; if the thickness of the sacrificial layer 112 located on the sidewall of the channel layer 105 is too small, it is easy to cause that the sacrificial layer 112 cannot fill up the space position opposite to the adjacent channel layer 105 and the space position opposite to the substrate of the channel layer 105, and accordingly, in the subsequent step of forming the shielding layer, the probability of forming the shielding layer in the space position opposite to the adjacent channel layer 105 and the space position opposite to the substrate of the channel layer 105 is increased, and in the subsequent step of removing the shielding layer, the probability of excessively consuming the shielding layer in the second device region 100B is increased, that is, the risk of exposing the work function layer 109 in the second device region 100B is increased, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the thickness of the sacrificial layer 112 located at the sidewall of the channel layer 105 is 10 nm to 20 nm.
In this embodiment, the process of forming the sacrificial layer 112 on the exposed top surface of the substrate of the channel structure layer 106, the top, the sidewall and the bottom of the channel layer 106 includes an atomic layer deposition process.
The atomic layer deposition process includes performing multiple atomic layer deposition cycles to facilitate improving thickness uniformity of the sacrificial layer 112 and enabling the sacrificial layer 112 to cover the exposed top surface of the substrate of the channel structure layer 106, the top, sidewalls, and bottom of the channel layer 106. In other embodiments, the sacrificial layer 112 may also be formed using a chemical vapor deposition process (Chemical Vapor Deposition, CVD).
Note that, in the step of forming the sacrifice layer 112 in this embodiment, the sacrifice layer 112 is also formed in the second device region 100B.
Specifically, by forming the sacrificial layer 112 in the second device region 100B, the probability of forming the shielding layer in the spatial position opposite to the adjacent channel layer 105 of the second device region 100B and the spatial position opposite to the substrate of the channel layer 105 is reduced in the subsequent step of forming the shielding layer, and accordingly, in the subsequent step of removing the shielding layer of the second device region 100B, the shielding layer can be removed by one etching process, thereby reducing the process steps and reducing the process cost.
In this embodiment, the material of the sacrificial layer 112 includes one or more of silicon oxide, aluminum oxide, and amorphous silicon.
Specifically, the silicon oxide, the aluminum oxide and the amorphous silicon have a larger etching selection ratio with the materials adopted by the channel structure layer 106, which is beneficial to removing the sacrificial layer by adopting the etching process later, and simultaneously, reduces the probability of damaging the channel structure layer 106.
Referring to fig. 10, a blocking layer 115 covering the top and sidewalls of the work function layer 109 and the sidewalls of the sacrificial layer 112 is formed on the exposed substrate of the channel structure layer 106.
Specifically, by forming the shielding layer 115 covering the top and the side walls of the work function layer 109 and the side walls of the sacrificial layer 112 on the substrate exposed by the channel structure layer 106, the second device region 100B is protected during the subsequent removal of the sacrificial layer 112 of the first device region 100A, and at the same time, the shielding layer 115 located in the second device region 100B functions as an etching mask during the subsequent removal of the work function layer 109 of the first device region 100A.
In this embodiment, the process of forming the shielding layer 115 covering the top and the side walls of the work function layer 109 and the side walls of the sacrificial layer 112 on the exposed substrate of the channel structure layer 106 includes a spin coating process.
In this embodiment, the material of the barrier layer 115 includes one or more of BARC (bottom anti-reflective coating) and SARC (sacrificial anti-reflective coating).
Specifically, the BARC and SARC materials have a larger etching selectivity ratio to the material of the work function layer 109, and in the subsequent step of removing the work function layer 109 of the first device region 100A, the shielding layer 115 of the second device region 100B can be used as an etching mask, and meanwhile, both the BARC and SARC materials are organic materials, and in the subsequent step of removing the shielding layer 115, the process difficulty of removing the shielding layer 115 is reduced, thereby improving the performance of the semiconductor structure.
Referring to fig. 11 to 14, the shielding layer 115, the sacrificial layer 112, and the work function layer 109 of the first device region 100A are removed.
Specifically, the removal of the masking layer 115, the sacrificial layer 112, and the work function layer 109 of the first device region 100A facilitates the subsequent formation of a gate electrode layer across the channel layer 105.
The steps of removing the shielding layer 115, the sacrificial layer 112, and the work function layer 109 of the first device region 100A will be described in detail with reference to fig. 11 to 14.
Referring to fig. 11 to 12, the blocking layer 115 of the first device region 100A is removed.
Specifically, the masking layer 115 of the first device region 100A is removed, exposing the sacrificial layer 112 of the first device region 100A, providing a process basis for subsequent removal of the sacrificial layer 112 and the work function layer 109.
In this embodiment, the step of removing the shielding layer 115 of the first device region 100A includes: as shown in fig. 11, a mask layer 118 is formed on top of the shielding layer 115 of the second device region 100B, the mask layer 118 exposing the first device region 100A; as shown in fig. 12, the blocking layer 115 of the first device region 100A is removed using the mask layer 118 as a mask.
In this embodiment, the mask layer 118 is made of photoresist.
In this embodiment, the process of removing the shielding layer 115 of the first device region 100A includes a dry etching process.
The dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, so that the longitudinal etching rate is far greater than the transverse etching rate, and the method is beneficial to ensuring the shape quality of the side wall of the shielding layer 115 of the second device region 100B while quite accurate pattern transfer can be obtained, and is beneficial to ensuring that the shielding layer 115 of the second device region 100B can completely cover the work function layer 109.
Referring to fig. 13 to 14, the sacrificial layer 112 and the work function layer 109 of the first device region 100A are removed using the remaining blocking layer 115 of the second device region 100B as a mask.
In this embodiment, the step of removing the sacrificial layer 112 and the work function layer 109 of the first device region 100A includes: as shown in fig. 13, the sacrificial layer 112 of the first device region 100A is removed; as shown in fig. 14, after the sacrificial layer 112 of the first device region 100A is removed, the work function layer 109 of the first device region 100A is removed.
Specifically, by removing the sacrificial layer 112 first, the work function layer 109 of the first device region 100A is exposed, which facilitates subsequent removal of the exposed work function layer 109 by an etching process.
In this embodiment, the process of removing the sacrificial layer 112 of the first device region 100A includes a wet etching process or an isotropic dry etching process.
Specifically, the wet etching process has the characteristics of simple operation, high process efficiency and the like, and can remove the sacrificial layer 112 of the first device region 100A completely, thereby reducing the probability of residual sacrificial layer 112 in the first device region 100A.
In this embodiment, the process of removing the work function layer 109 of the first device region 100A includes a wet etching process or an isotropic dry etching process.
Specifically, the wet etching process has the characteristics of simple operation, high process efficiency and the like, and can remove the work function layer 109 of the first device region 100A completely, so that the probability of residual work function layer 109 in the first device region 100A is reduced.
After removing the shielding layer 115, the sacrificial layer 112, and the work function layer 109 of the first device region 100A, the method further includes: mask layer 118 is removed.
Specifically, the process of removing the mask layer 118 includes one or both of a wet etching process and an ashing process.
Referring to fig. 15, after removing the blocking layer 115, the sacrificial layer 112, and the work function layer 109 of the first device region 100A, the blocking layer 115 of the second device region 100B is removed.
Specifically, removing the blocking layer 115 of the second device region 100B exposes the sacrificial layer 112 of the second device region 100B, facilitating subsequent removal of the sacrificial layer 112 through the gate opening 107.
In this embodiment, the process of removing the shielding layer 115 of the second device region 100B includes an ashing process
Specifically, the ashing process has the characteristics of low process cost, simple operation and the like, and the ashing process is adopted to remove the shielding layer 115 of the second device region 100B, so that the shielding layer 115 of the second device region 100B is completely removed, the probability of residual shielding layer 115 in the second device region 100B is reduced, and the performance of the semiconductor structure is improved.
In this embodiment, after removing the shielding layer 115 of the second device region 100B; the sacrificial layer 112 of the second device region 100B is removed.
Referring to fig. 16, after removing the shielding layer 115, the sacrificial layer 112, and the work function layer 109 of the first device region 100A, further includes: the sacrificial layer 112 of the second device region 100B is removed.
Specifically, the sacrificial layer 112 of the second device region 100B is removed, facilitating the subsequent formation of a gate electrode layer in the second device region 100B surrounding the capping work function layer 109.
In this embodiment, the process of removing the sacrificial layer 112 of the second device region 100B includes a wet etching process.
Specifically, the wet etching process has the characteristics of simple operation, high process efficiency and the like, and can remove the sacrificial layer 112 of the second device region 100B completely, so that the probability of residual sacrificial layer 112 in the second device region 100B is reduced, and the performance of the semiconductor structure is improved.
Referring to fig. 17, after removing the shielding layer 115 of the second device region 100B, the method for forming a semiconductor structure further includes: a gate electrode layer 130 is formed across the channel layer 105 on top of the substrate of the first device region 100A and the second device region 100B, wherein the gate electrode layer 130 in the first device region 100A surrounds the overlying gate dielectric layer 108 and the gate electrode layer 130 in the second device region 100B surrounds the overlying work function layer 109.
The gate electrode layer 130 is used for subsequent electrical connection with external structures.
The material of the gate electrode layer 130 includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN and TiAlC. In this embodiment, the material of the gate electrode layer 130 includes W.
In this embodiment, the process of forming the gate electrode layer 130 across the channel layer 105 on top of the substrate of the first device region 100A and the second device region 100B includes a chemical vapor deposition process.
Note that, when the work function layer 109 formed as described above is the first work function layer 109, before forming the gate electrode layer 130, the method may further include: a second work function layer (not shown) is formed in the first device region 100A surrounding the capping gate dielectric layer 108, the second work function layer being used to adjust the threshold voltage of the first type transistor.
As an example, the first type transistor is an NMOS transistor, the second work function layer is an N type work function layer, and a material of the second work function layer includes one or more of TiAl, mo, moN, alN and TiAlC.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first device region and a second device region which are adjacent, a channel structure layer is suspended on the top of the substrate of the first device region and the second device region along the normal direction of the surface of the substrate, and the channel structure layer comprises one or more channel layers which are arranged at intervals in the longitudinal direction;
forming a gate dielectric layer and a work function layer surrounding and covering the gate dielectric layer on part of the top, part of the side wall and part of the bottom of the channel layer;
filling a sacrificial layer covering the work function layer in the first device region at a space position opposite to the adjacent channel layer and a space position opposite to the substrate;
forming a shielding layer covering the top and the side wall of the work function layer and the side wall of the sacrificial layer on the substrate exposed by the channel structure layer;
removing the shielding layer, the sacrificial layer and the work function layer of the first device region;
and removing the shielding layer, the sacrificial layer and the work function layer of the first device region, and then removing the shielding layer of the second device region.
2. The method of forming a semiconductor structure of claim 1, wherein filling the sacrificial layer covering the work function layer in a spatial position where adjacent channel layers face each other and a spatial position where the channel layers face the substrate comprises: and forming a sacrificial layer on the top surface of the substrate, the top, the side wall and the bottom of the channel layer, which are exposed out of the channel structure layer, wherein the sacrificial layer circumferentially covers the work function layer.
3. The method of forming a semiconductor structure of claim 2, wherein in the step of filling the sacrificial layer, a thickness of the sacrificial layer located at a sidewall of the channel layer is 10 nm to 20 nm.
4. The method of forming a semiconductor structure of claim 2, wherein the process of forming a sacrificial layer on the exposed top surface of the substrate, the top, side walls and bottom of the channel layer comprises an atomic layer deposition process.
5. The method of forming a semiconductor structure of claim 1, wherein removing the masking layer, sacrificial layer, and work function layer of the first device region comprises: removing the shielding layer of the first device region; and removing the sacrificial layer and the work function layer of the first device region by taking the residual shielding layer of the second device region as a mask.
6. The method of forming a semiconductor structure of claim 5, wherein removing the masking layer of the first device region comprises: forming a mask layer on the top of the shielding layer of the second device region, wherein the mask layer exposes the first device region; and removing the shielding layer of the first device region by taking the mask layer as a mask.
7. The method of forming a semiconductor structure of claim 1 or 5, wherein the process of removing the masking layer of the first device region comprises a dry etching process.
8. The method of forming a semiconductor structure of claim 5, wherein removing the sacrificial layer and work function layer of the first device region comprises: removing the sacrificial layer of the first device region; after the sacrificial layer of the first device region is removed, the work function layer of the first device region is removed.
9. The method of forming a semiconductor structure of claim 1 or 8, wherein the process of removing the sacrificial layer of the first device region comprises a wet etching process or an isotropic dry etching process;
the process of removing the work function layer of the first device region includes a wet etching process or an isotropic dry etching process.
10. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the sacrificial layer, the sacrificial layer is further formed in the second device region;
after removing the shielding layer, the sacrificial layer and the work function layer of the first device region, the method further comprises: and removing the sacrificial layer of the second device region.
11. The method of forming a semiconductor structure of claim 10, wherein the process of removing the sacrificial layer of the second device region comprises a wet etch process.
12. The method of forming a semiconductor structure of claim 10, wherein after removing the masking layer of the second device region; and removing the sacrificial layer of the second device region.
13. The method of forming a semiconductor structure of claim 1 or 12, wherein the process of removing the masking layer of the second device region comprises an ashing process.
14. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the sacrificial layer, a material of the sacrificial layer comprises one or more of silicon oxide, aluminum oxide, and amorphous silicon.
15. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the masking layer, a material of the masking layer comprises one or both of BARC and SARC.
16. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the gate dielectric layer and the work function layer, the material of the gate dielectric layer includes HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following;
the material of the work function layer includes one or more of TiN, taN, tiAl, tiSiN and TiAlC.
17. The method of forming a semiconductor structure of claim 1, wherein after removing the masking layer of the second device region, the method of forming a semiconductor structure further comprises: and forming a gate electrode layer crossing the channel layer on top of the substrates of the first device region and the second device region, wherein the gate electrode layer in the first device region circumferentially covers the gate dielectric layer, and the gate electrode layer in the second device region circumferentially covers the work function layer.
18. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, an interlayer dielectric layer is further formed on the substrate to cover the channel structure layer, and a gate opening is formed in the interlayer dielectric layer to cross the channel structure layer, the gate opening exposing a portion of a top and a portion of a sidewall of the channel structure layer;
in the step of forming the gate dielectric layer, the gate dielectric layer is formed on part of the top, part of the side wall and part of the bottom of the channel layer exposed by the gate opening.
CN202210565372.3A 2022-05-23 2022-05-23 Method for forming semiconductor structure Pending CN117153787A (en)

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