CN116314029A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN116314029A CN116314029A CN202111561592.0A CN202111561592A CN116314029A CN 116314029 A CN116314029 A CN 116314029A CN 202111561592 A CN202111561592 A CN 202111561592A CN 116314029 A CN116314029 A CN 116314029A
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a first device region and a second device region which are adjacent to each other, channel layer structures are respectively formed on the substrate of the first device region and the second device region, the channel layer structures comprise one or more channel layers with intervals, and initial isolation walls which cover opposite side walls of the channel layer structures are formed between adjacent channel layer structures at the junction of the first device region and the second device region; forming a cap layer on the side wall of the initial isolation wall, wherein the cap layer covers part of the side wall of the initial isolation wall, which is higher than the top surface of the channel layer structure, and a space is reserved between the bottom of the cap layer and the topmost channel layer, and the cap layer and the initial isolation wall are used as isolation walls together; forming a cross channel layer structure and a partition wall gate structure; forming a first partition opening penetrating through the grid structure at the top of the isolation wall; a first gate isolation structure is formed in the first isolation opening. The invention increases the process window for forming the first partition opening at the top of the partition wall.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. To better accommodate the demands of device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors and fork-Gate (fork-Gate) transistors.
In the current process of forming the Gate, a Gate cutting (Gate Cut) technology is generally adopted to Cut off the strip-shaped Gate, and the Cut Gate corresponds to different transistors, so that the integration level of the transistors can be improved. In addition, when a plurality of gates are arranged in a row along the extending direction, the Gate cutting technique can reduce the pitch (Gate Cut CD) in the abutting direction between the disconnected gates after Gate cutting with high accuracy.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate comprising a first device region and a second device region adjacent to each other; the channel layer structure is respectively positioned on the substrates of the first device region and the second device region, and comprises one or more channel layers at intervals along the normal direction of the surfaces of the substrates; an initial isolation wall protruding on the substrate at the junction of the first device region and the second device region, wherein the initial isolation wall covers opposite side walls of the channel layer structures of the first device region and the second device region; the cap layer is positioned on the side wall of the initial isolation wall and covers part of the side wall of the initial isolation wall, which is higher than the top surface of the channel layer structure, a space is reserved between the bottom of the cap layer and the topmost channel layer, and the cap layer and the initial isolation wall are used as isolation walls together; a gate structure on the substrate and crossing the channel layer structure and the isolation wall, wherein the gate structure covers the top, the bottom and the side wall of the channel layer exposed; the grid isolation structure comprises a first grid isolation structure which is positioned at the top of the isolation wall and penetrates through the grid structure, and the grid isolation structure divides the grid structure along the extending direction of the grid structure.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first device region and a second device region which are adjacent, channel layer structures are respectively formed on the substrate of the first device region and the second device region, the channel layer structures comprise one or more channel layers with intervals, and initial isolation walls which cover opposite side walls of the channel layer structures are formed on the substrate between the adjacent channel layer structures at the junction of the first device region and the second device region; forming a cap layer on the side wall of the initial isolation wall, wherein the cap layer covers part of the side wall of the initial isolation wall, which is higher than the top surface of the channel layer structure, a space is reserved between the bottom of the cap layer and the topmost channel layer, and the cap layer and the initial isolation wall are used as isolation walls together; forming a gate structure crossing the channel layer structure and the isolation wall, wherein the gate structure covers the exposed top, bottom and side walls of the channel layer; forming a first partition opening penetrating through the grid structure at the top of the isolation wall, wherein the first partition opening partitions the grid structure along the extending direction of the grid structure; a first gate isolation structure is formed in the first isolation opening.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the semiconductor structure provided by the embodiment of the invention comprises an initial isolation wall, wherein the initial isolation wall is convexly arranged on a substrate at the junction of the first device region and the second device region, the initial isolation wall covers opposite side walls of channel layer structures of the first device region and the second device region, a cap layer is positioned on the side walls of the initial isolation wall and covers part of the side walls of the initial isolation wall, which are higher than the top surface of the channel layer structure, a space is reserved between the bottom of the cap layer and a topmost channel layer, and the cap layer and the initial isolation wall are used as isolation walls together; as feature sizes of integrated circuits continue to decrease, adjacent devices get closer and closer, in this embodiment of the present invention, the isolation wall isolates the first device region and the second device region, so that, under a condition that an isolation effect on the adjacent devices is better ensured, the first device region and the second device region are made to be as close as possible, which is favorable to reducing a distance between adjacent channel layer structures of the first device region and the second device region, thereby forming a device with a tighter and smaller size, and meanwhile, the first gate isolation structure is located at the top of the isolation wall and penetrates through the gate structure, so that the cap layer covers a portion of a sidewall of the initial isolation wall, which is higher than the top of the channel layer structure, which is favorable to increasing an area of the top of the isolation wall for contacting with the first gate isolation structure, thereby increasing a process window for forming the first gate isolation structure at the top of the isolation wall, and favorable to reducing a probability of damaging a film layer (e.g., a work function layer or a channel layer covering a channel layer) at a side of the isolation wall, thereby improving performance of the semiconductor structure.
In the forming method provided by the embodiment of the invention, an initial isolation wall covering opposite side walls of the channel layer structure is formed on a substrate between adjacent channel layer structures at the junction of the first device region and the second device region, a cap layer is formed on the side walls of the initial isolation wall, the cap layer covers part of the side walls of the initial isolation wall, which are higher than the top surface of the channel layer structure, a space is reserved between the bottom of the cap layer and the topmost channel layer, and the cap layer and the initial isolation wall are used as isolation walls together; as the feature size of the integrated circuit continues to decrease, the adjacent devices are closer and closer, so that under the condition that the isolation effect on the adjacent devices is better ensured, the adjacent first device region and second device region are as close as possible, which is beneficial to reducing the distance between the adjacent channel layer structures of the first device region and the second device region, thereby forming a device with a tighter and smaller size, meanwhile, a first isolation opening penetrating through the gate structure is formed at the top of the isolation wall, and a first gate isolation structure is formed in the first isolation opening, the cap layer covers a part of the side wall of the initial isolation wall higher than the top surface of the channel layer structure, which is beneficial to increasing the contact area of the top of the isolation wall with the first gate isolation structure, thereby increasing the process window for forming the first isolation opening at the top of the isolation wall, and reducing the probability of damaging the film layer (such as a work function layer or a semiconductor layer) at the side of the isolation wall, thereby improving the performance of the semiconductor structure.
Drawings
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
FIG. 4 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 5 to 18 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of current semiconductor structures is to be improved. The reason why the performance of a semiconductor structure is to be improved is now analyzed in conjunction with a method of forming the semiconductor structure.
Fig. 1 to 3 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, including a first device region 10A and a second device region 10B adjacent to each other, a channel layer structure 20 is formed on the substrate 10 of the first device region 10A and the second device region 10B, respectively, the channel layer structure 20 includes one or more spaced channel layers 21, and a partition wall 30 covering opposite sidewalls of the channel layer structure 20 is formed on the substrate 10 between adjacent channel layer structures 20 at the interface of the first device region 10A and the second device region 10B; a gate structure 40 is formed across the channel layer structure 20 and the spacer 30, the gate structure 40 covering the exposed top, bottom and sidewalls of the channel layer 21.
Referring to fig. 2, a partition opening 43 penetrating the gate structure 40 is formed at the top of the partition wall 30, and the partition opening 43 partitions the gate structure 40 along the extending direction of the gate structure 30.
Referring to fig. 3, a gate blocking structure 44 is formed in the blocking opening 43.
At present, in order to make the distance between adjacent channel structures 20 smaller at the junction of the first device region 10A and the second device region 10B, a partition wall 30 covering the sidewall of the channel structure 20 is formed at the junction of the first device region 10A and the second device region 10B, and the partition wall 30 ensures the isolation effect on adjacent devices when the adjacent first device region 10A and the adjacent second device region 10B are as close as possible.
As feature sizes of integrated circuits continue to decrease, adjacent devices get closer together, and in order to occupy less space, the dimension of the isolation wall 30 along the extending direction of the channel layer 21 is smaller, that is, the top surface area of the isolation wall 30 is smaller, and the partition structure 44 is formed on top of the isolation wall 30, so that a process window for forming the partition opening 43 is smaller, which results in difficulty in accurately positioning the partition opening 43, and in forming the partition opening 43, etching is easily caused to the side of the isolation wall 30 due to etching deviation, so that other film layers on the side of the isolation wall 30, for example, a work function layer or the channel layer 21 covering the channel layer 21, are damaged, thereby affecting performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device region and a second device region which are adjacent to each other, channel layer structures are respectively formed on the substrate of the first device region and the second device region, each channel layer structure comprises one or more channel layers with intervals, and initial isolation walls which cover opposite side walls of the channel layer structures are formed on the substrate between the adjacent channel layer structures at the junction of the first device region and the second device region; forming a cap layer on the side wall of the initial isolation wall, wherein the cap layer covers part of the side wall of the initial isolation wall, which is higher than the top surface of the channel layer structure, and a space is reserved between the bottom of the cap layer and the topmost channel layer, and the cap layer and the initial isolation wall are used as isolation walls together; forming a gate structure crossing the channel layer structure, the isolation wall and the cap layer, wherein the gate structure covers the top, the bottom and the side wall of the channel layer exposed; forming a first partition opening penetrating through the grid structure at the top of the isolation wall, wherein the first partition opening partitions the grid structure along the extending direction of the grid structure; a first gate isolation structure is formed in the first isolation opening.
With the continuous decrease of the feature size of the integrated circuit, the adjacent devices are closer and closer, in the forming method provided by the embodiment of the invention, the first device region and the second device region are isolated by the isolation wall, so that the adjacent first device region and the adjacent second device region are as close as possible under the condition of better guaranteeing the isolation effect on the adjacent devices, the distance between the adjacent channel layer structures of the first device region and the adjacent channel layer structure of the second device region is reduced, a device with a tighter size is formed, meanwhile, a first isolation opening penetrating through the gate structure is formed at the top of the isolation wall, and a first gate isolation structure is formed in the first isolation opening, the cap layer covers a part of the side wall of the initial isolation wall which is higher than the top surface of the channel layer structure, the area of the top of the isolation wall, which is used for being contacted with the first gate isolation structure, is increased, a process window for forming the first isolation opening at the top of the isolation wall is increased, and the probability of damaging a film layer (for example, a layer covering the channel layer or the channel layer) at the side of the isolation wall is reduced when the first gate isolation opening is formed is facilitated, and the work function performance of the semiconductor structure is improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
The semiconductor structure includes: a substrate 101 comprising a first device region 101A and a second device region 101B adjacent; a channel layer structure 201 on the substrate 101 of the first device region 101A and the second device region 101B, respectively, the channel layer structure 201 including one or more spaced channel layers 211 along a normal direction (as shown in a Y direction in fig. 4) of a surface of the substrate 101; an initial isolation wall 301 protruding over the substrate 101 at the interface of the first device region 101A and the second device region 101B, the initial isolation wall 301 covering opposite sidewalls of the channel layer structure 201 of the first device region 101A and the second device region 101B; the cap layer 331 is located on the side wall of the initial isolation wall 301 and covers a part of the side wall of the initial isolation wall 301 higher than the top surface of the channel layer structure 201, a space is arranged between the bottom of the cap layer 331 and the topmost channel layer 211, and the cap layer 331 and the initial isolation wall 301 are used as isolation walls 341 together; a gate structure 401 on the substrate 101 and crossing the channel layer structure 201 and the isolation wall 341, the gate structure 401 covering the exposed top, bottom and sidewalls of the channel layer 211; a gate isolation structure (not shown) includes a first gate isolation structure 441 located on top of the isolation wall 341 and penetrating the gate structure 401, and the gate isolation structure divides the gate structure 401 along an extending direction of the gate structure 401.
The substrate 101 provides a process operation basis for the formation process of the semiconductor structure. Wherein the semiconductor structure comprises a fork gate (fork-type) transistor.
The base 101 includes a substrate 111.
In this embodiment, the material of the substrate 111 is silicon, and in other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or another type of substrate such as a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the substrate 101 further includes an isolation layer 121 on the substrate 121, where the isolation layer 121 is used to achieve isolation between different devices, for example, in a CMOS manufacturing process, the isolation layer 121 is typically formed between an NMOS transistor and a PMOS transistor.
In this embodiment, taking a semiconductor structure as a fork gate transistor as an example, the substrate 101 includes a first device region 101A and a second device region 101B adjacent to each other, where the first device region 101A is used to form a first device, and the second device region 101B is used to form a second device.
In this embodiment, the first device region 101A includes an NMOS region, and the second device region 101B includes a PMOS region, where the NMOS region is used to form an NMOS transistor, and the PMOS region is used to form a PMOS transistor.
With the continued shrinking of device feature sizes, by employing fork gate transistors, smaller spacing between adjacent NMOS and PMOS transistors can be allowed, resulting in better area scalability.
In this embodiment, the NMOS transistor formed in the first device region 101A and the PMOS transistor formed in the first device region 101B constitute a fork gate transistor.
Accordingly, the first device region 101B and the second device region 101B constitute a third device region 101C, and the third device region 101C is used to form a fork gate transistor.
The channel layer structure 201 includes one or more spaced apart channel layers 211, the channel layers 211 serving as channels for the semiconductor structure.
In this embodiment, the material of the channel layer 211 includes silicon, germanium, silicon germanium, or a group iii-v semiconductor material. As an example, the material of the channel layer 211 is silicon. In other embodiments, the material of the channel layer is determined by the type and performance of the transistor.
The initial isolation wall 301 is used to isolate devices close to the first device region 101A and the second device region 101B, so that devices adjacent to the first device region 101A and the second device region 101B are as close as possible under the condition of better guaranteeing the isolation effect on the adjacent devices, which is beneficial to reducing the distance between adjacent channel layer structures 201 of the first device region 101A and the second device region 101B, so as to form a tighter and smaller-size device.
In this embodiment, the top of the initial isolation wall 301 is higher than the top of the channel layer structure 201, so as to improve the isolation effect on the adjacent devices, and also serves as a support portion of the cap layer 331.
In this embodiment, the material of the initial isolation wall 301 includes SiBCN or SiN.
The SiBCN or SiN has a better insulation property, so that a better isolation effect can be provided between the devices in the first device region 101A and the second device region 101B.
The cap layer 331 is used to isolate the devices of the first device region 101A and the second device region 101B as a partition wall 341 together with the initial partition wall 301.
As feature sizes of integrated circuits continue to decrease, adjacent devices get closer and closer, in this embodiment, the isolation wall 341 isolates the first device region 101A and the second device region 101B, so that, under a condition that an isolation effect on the adjacent devices is better ensured, the adjacent first device region 101A and the second device region 101B are as close as possible, which is favorable for reducing a distance between adjacent channel layer structures 201 of the first device region 101A and the second device region 101B, so as to form a tighter device with smaller size, and meanwhile, the first gate isolation structure 441 is located on top of the isolation wall 341 and penetrates through the gate structure 401, so that the cap layer 331 covers a portion of a sidewall of the initial isolation wall 301 higher than the top surface of the channel layer structure 201, which is favorable for increasing an area of the top of the isolation wall 341 for contacting the first gate isolation structure 441, so as to increase a process window for forming the first gate isolation structure 441 on top of the isolation wall 341, which is favorable for reducing a probability of damaging a film layer (e.g., a work function layer or a channel layer 211 covering a side of the isolation wall 341 when forming the first gate isolation structure 441, so as to improve performance of the semiconductor structure.
In this embodiment, the step of forming the cap layer 331 includes: forming a filling layer covering the channel layer structure 201 and part of the side wall of the initial isolation wall 301, wherein the top surface of the filling layer is lower than the top surface of the initial isolation wall 301; forming a cap material layer covering the filling layer and the initial barrier 301 with the filling layer exposed; removing the capping material layer covering the filling layer, and reserving the capping material layer covering the initial isolation wall 301 exposed by the filling layer as a capping layer 331; after the cap layer 331 is formed, the fill layer is removed. The thickness of the capping material layer formed on top of the initial isolation wall 301 can be adjusted by adjusting the process parameters of forming the capping material layer, and thus, by adjusting such that the thickness of the capping material layer formed on top of the initial isolation wall 301 is greater than the thickness of the capping material layer covering the filling layer, the capping material layer covering the top of the initial isolation wall 301 is still maintained in the step of removing the capping material layer covering the filling layer, and for this reason, in this embodiment, the capping layer 331 also extends to cover the top surface of the initial isolation wall 301.
In other embodiments, the cap layer covering the top of the initial isolation wall may also be removed in the step of removing the cap material layer covering the filling layer by adjusting the thickness of the cap material layer formed on the top of the initial isolation wall to be equal to the thickness of the cap material layer covering the filling layer, and for this purpose, the cap layer may also be located only on the side wall of the initial isolation wall.
In this embodiment, the material of the cap layer 331 includes SiC.
SiC has a good insulation property, can be used as the isolation wall 341 together with the initial isolation wall 301, and enables a good isolation effect between devices of the first device region 101A and the second device region 101B.
It should be noted that, in this embodiment, the width of the cap layer 331 at the sidewall of the initial isolation wall 301 is not too large or too small. If the width of the capping layer 331 located at the sidewall of the initial isolation wall 301 is too large, the thickness of the capping material layer formed is too large, increasing the difficulty of removing the capping material layer covering the filling layer, and also, causing unnecessary waste while properly increasing the area of the top of the isolation wall 341 for contact with the first gate partition structure 441; if the width of the cap layer 331 located at the sidewall of the initial isolation wall 301 is too small, the area of the top of the isolation wall 341 for contact with the first gate partition structure 441 increases too little, so that the process window for forming the first gate partition structure 441 at the top of the isolation wall 341 is still small, which easily results in damage to the film layer (e.g., the work function layer covering the channel layer 211 or the channel layer 211) at the side of the isolation wall 341 when the first gate partition structure 441 is formed, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the width of the cap layer 331 located at the sidewall of the initial isolation wall 301 is 10nm to 26nm.
The gate structure 401 is used to control the turning on or off of the channel of the transistor.
In this embodiment, the gate structure 401 includes a gate dielectric layer 411 and a gate electrode layer 421 on the gate dielectric layer 411.
The gate dielectric layer 411 is used to isolate the gate structure 401 from the channel layer 211.
The material of the gate dielectric layer 411 includes HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following. In this embodiment, the material of the gate dielectric layer 411 includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer comprises HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
The gate electrode layer 421 includes a work function layer (not shown), and an electrode layer (not shown) over the work function layer.
The work function layer is used to adjust the threshold voltage of the transistor. For a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, taN, taSiN, taAlN and TiAlN; for an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or two of TiAl and TiAlC.
The electrode layer is used for leading out the electricity of the gate electrode layer. In this embodiment, the material of the electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN and TiAlC.
In other embodiments, the gate structure may be a polysilicon gate structure, depending on the process requirements.
The gate isolation structure is used to insulate the gate structures 401 from each other, wherein the first gate isolation structure 441 is used to insulate the gate structures 401 of the adjacent first device region 101A and second device region 101B from each other.
In this embodiment, the gate isolating structure further includes: the second gate isolating structure 461 is located on the substrate 101 at the junction of the adjacent third device region 101C and penetrates the gate structure 401.
The second gate blocking structure 461 is used to insulate the gate structures 401 of adjacent third device regions 101C from each other.
The hardness and the compactness of the material of the grid isolation structure are higher, so that the probability of damage of the grid isolation structure in the formation process of the semiconductor structure is reduced, and the isolation performance of the grid isolation structure is ensured.
Therefore, in this embodiment, the material of the gate isolation structure is silicon nitride, and has better isolation performance. In other embodiments, the gate isolation structure may also be other nitrogen-containing dielectric materials.
Fig. 5 to 18 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5, a substrate 100 is provided, including a first device region 100A and a second device region 100B adjacent to each other, a channel layer structure 200 is formed on the substrate 100 of the first device region 100A and the second device region 100B, respectively, the channel layer structure 200 includes one or more spaced apart channel layers 210, and an initial isolation wall 300 is formed on the substrate 100 between adjacent channel layer structures 200 at the interface of the first device region 100A and the second device region 100B, covering opposite sidewalls of the channel layer structure 200.
The substrate 100 provides a process operation basis for the formation process of the semiconductor structure. Wherein the semiconductor structure comprises a fork gate (fork-type) transistor.
The base 100 includes a substrate 110.
In this embodiment, the material of the substrate 110 is silicon, and in other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or another type of substrate such as a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the substrate 100 further includes an isolation layer 120, where the isolation layer 120 is used to isolate different devices, for example, in a CMOS manufacturing process, the isolation layer 120 is typically formed between an NMOS transistor and a PMOS transistor.
In this embodiment, taking a semiconductor structure as a fork gate transistor as an example, the substrate 100 includes a first device region 100A and a second device region 100B adjacent to each other, where the first device region 100A is used to form a first device, and the second device region 100B is used to form a second device.
In this embodiment, the first device region 100A includes an NMOS region, and the second device region 100B includes a PMOS region for forming an NMOS transistor, and a PMOS region for forming a PMOS transistor, thereby forming a fork gate transistor.
With the continued shrinking of device feature sizes, by employing fork gate transistors, smaller spacing between adjacent NMOS and PMOS transistors can be allowed, resulting in better area scalability.
In this embodiment, the NMOS transistor formed in the first device region 100A and the PMOS transistor formed in the first device region 100B constitute a fork gate transistor.
Accordingly, the first device region 100B and the second device region 100B constitute a third device region 100C, and the third device region 100C is used to form a fork gate transistor.
In this embodiment, an interlayer dielectric layer (not shown) is formed on the substrate 100 to cover the substrate 100, a gate opening 220 is formed in the interlayer dielectric layer, and a channel layer structure 200 is formed in the gate opening 220.
The interlayer dielectric layer is used for isolating adjacent devices.
The gate opening 220 exposes the channel layer structure 200, providing a spatial location for the subsequent formation of the gate structure.
The channel layer structure 200 includes one or more spaced apart channel layers 210, the channel layers 210 serving as channels for the semiconductor structure.
In this embodiment, the material of channel layer 210 includes silicon, germanium, silicon germanium, or a group iii-v semiconductor material. As an example, the material of the channel layer 210 is silicon. In other embodiments, the material of the channel layer is determined by the type and performance of the transistor.
The initial isolation wall 300 is used for isolating devices close to the first device region 100A and the second device region 100B, so that devices adjacent to the first device region 100A and the second device region 100B are as close as possible under the condition of better guaranteeing the isolation effect on the adjacent devices, and the distance between adjacent channel layer structures 200 of the first device region 100A and the second device region 100B is reduced, so that devices with tighter sizes are formed.
In this embodiment, the top of the initial isolation wall 300 is higher than the top of the channel layer structure 200, so as to improve the isolation effect on the adjacent devices, and is also used as a support portion for forming a cap layer later.
In this embodiment, the material of the initial isolation wall 300 includes SiBCN or SiN.
The SiBCN or SiN has a better insulation property, so that a better isolation effect can be provided between the devices in the first device region 100A and the second device region 100B.
Referring to fig. 6 to 8 in combination, a cap layer 330 is formed on the sidewall of the initial isolation wall 300, the cap layer 330 covers a portion of the sidewall of the initial isolation wall 300 higher than the top surface of the channel layer structure 200, a space is provided between the bottom of the cap layer 330 and the topmost channel layer 210, and the cap layer 330 and the initial isolation wall 300 together serve as a isolation wall 340.
The cap layer 330 is used to isolate the devices of the first device region 100A and the second device region 100B together with the initial isolation wall 300 as the isolation wall 340.
As feature sizes of integrated circuits continue to decrease, adjacent devices get closer and closer, in this embodiment, the isolation wall 340 isolates the first device region 100A and the second device region 100B, so that, under a condition that an isolation effect on the adjacent devices is better ensured, the adjacent first device region 100A and the second device region 100B are made to be as close as possible, which is favorable for reducing a distance between the adjacent channel layer structures 200 of the first device region 100A and the second device region 100B, so as to form a tighter and smaller device, and simultaneously, a first isolation opening penetrating the gate structure is formed at the top of the isolation wall 340, and a first gate isolation structure is formed in the first isolation opening, so that the cap layer 330 covers a portion of the sidewall of the initial isolation wall 300 higher than the top surface of the channel layer structure 200, which is favorable for increasing an area for contacting the first gate isolation structure at the top of the isolation wall 340, thereby increasing a process window for forming the first isolation opening at the top of the isolation wall 340, and favorable for reducing a probability of damaging a film layer (e.g., a work function layer 210 covering the channel layer 210) at the side of the isolation wall 340, so as to improve performance of the semiconductor structure.
In this embodiment, the step of forming the cap layer 330 includes: forming a filling layer covering the channel layer structure 200 and part of the side wall of the initial isolation wall 300, wherein the top surface of the filling layer is lower than the top surface of the initial isolation wall 300; forming a cap material layer covering the filling layer and the initial isolation wall 300 where the filling layer is exposed; removing the capping material layer covering the filling layer, and retaining the capping material layer covering the initial barrier 300 exposed by the filling layer as the capping layer 330; after the cap layer 330 is formed, the fill layer is removed. The thickness of the capping material layer formed on top of the initial isolation wall 300 can be adjusted by adjusting the process parameters for forming the capping material layer, and thus, by adjusting the thickness of the capping material layer formed on top of the initial isolation wall 300 to be greater than the thickness of the capping material layer covering the filling layer, the capping material layer covering the top of the initial isolation wall 300 is still maintained in the step of removing the capping material layer covering the filling layer, and for this reason, in this embodiment, the capping layer 330 also covers the top surface of the initial isolation wall 300.
In other embodiments, the cap layer covering the top of the initial isolation wall may also be removed in the step of removing the cap material layer covering the filling layer by adjusting the thickness of the cap material layer formed on the top of the initial isolation wall to be equal to the thickness of the cap material layer covering the filling layer, and for this purpose, the cap layer may also be located only on the side wall of the initial isolation wall.
In this embodiment, the material of the cap layer 330 includes SiC.
SiC has a good insulation property, can be used as the partition wall 340 together with the initial partition wall 300, and allows a good isolation effect between devices of the first device region 100A and the second device region 100B.
It should be noted that, in the present embodiment, the width of the cap layer 330 located on the sidewall of the initial isolation wall 300 is not too large or too small. If the width of the capping layer 330 located at the sidewall of the initial isolation wall 300 is excessively large, the thickness of the capping material layer formed is excessively large, increasing the difficulty of removing the capping material layer covering the filling layer, and also, causing unnecessary waste while properly increasing the area of the top of the isolation wall 340 for contact with the first gate isolation structure 440; if the width of the capping layer 330 located at the sidewall of the initial isolation wall 300 is too small, the area of the top of the isolation wall 340 for contact with the first gate blocking structure 440 is increased too little, so that the process window for forming the first gate blocking structure 440 at the top of the isolation wall 340 is still small, which easily results in damage to the film layer (e.g., the work function layer or the channel layer 210 covering the channel layer 210) at the side of the isolation wall 340 when the first gate blocking structure 440 is formed, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the width of the cap layer 330 located at the sidewall of the initial isolation wall 300 is 10nm to 26nm.
Specifically, referring to fig. 5, the step of forming the cap layer 330 on the sidewall of the initial partition wall 300 includes: a filling layer 310 is formed to cover the channel layer structure 200 and a portion of the sidewalls of the initial isolation wall 300, and the top surface of the filling layer 310 is lower than the top surface of the initial isolation wall 300.
The filling layer 310 provides a process basis for the subsequent formation of the capping material layer, the filling layer 310 covers the channel layer structure 200, the channel layer structure 200 can be protected during the step of forming the capping material layer, the top surface of the filling layer 310 is lower than the top surface of the initial isolation wall 300, so that the cap layer 330 can be formed on the sidewall of the initial isolation wall 300, and the area of the cap layer 330 covering the sidewall of the initial isolation wall 300 can be controlled by controlling the height of the filling layer 310.
In this embodiment, the filling layer 310 is formed by a chemical vapor deposition process.
The chemical vapor deposition process has good deposition effect, high gap filling capability, high quality of the filling layer 310, and reduced voids in the film.
In this embodiment, the filling layer 310 is required to be removed later, and the filling layer 310 is required to be made of a material easy to remove, so in this embodiment, the material of the filling layer 310 includes an advanced patterning film (Advanced Patterning Film, APF) material, which is easy to remove the filling layer 310 later, and is beneficial to reducing damage to the channel layer 210 and the initial isolation wall 300 during the removal process.
Referring to fig. 7, a capping material layer 320 covering the filling layer 310 and the initial partition wall 300 where the filling layer 310 is exposed is formed.
The cap material layer 320 is used to directly form the cap layer 330.
In this embodiment, the process of forming the cap material layer 320 covering the filling layer 310 and the initial isolation wall 300 where the filling layer 310 is exposed includes an atomic layer deposition process or a chemical vapor deposition process.
The atomic layer deposition process or the chemical vapor deposition process has a good deposition effect and a good step coverage capability, so that the capping material layer 320 can better cover the filling layer 310 and the initial isolation wall 300 exposed by the filling layer 310, and the atomic layer deposition process or the chemical vapor deposition process can adjust the capping material layer 320 formed on the top of the initial isolation wall 300 by adjusting process parameters.
Accordingly, in this embodiment, the material of cap material layer 320 comprises SiC.
Referring to fig. 8, the capping material layer 320 covering the filling layer 310 is removed, and the capping material layer 320 covering the initial isolation wall 300 where the filling layer 310 is exposed remains as the capping layer 330.
The capping material layer 320 covering the fill layer 310 is removed to form the cap layer 330 while exposing the fill layer 310 in preparation for subsequent removal of the fill layer 310.
In other embodiments, the cap material layer on top of the original spacer may also be removed at the same time as the cap material layer covering the filler layer is removed.
In this embodiment, the process of removing the capping material layer 320 covering the filling layer 310 and leaving the capping material layer 320 covering the initial isolation wall 300 exposed by the filling layer 310 as the capping layer 330 includes an anisotropic etching process.
The anisotropic etching process includes an anisotropic dry etching process that is more directional and facilitates the formation of the cap layer 330 with higher sidewall quality.
Referring to fig. 9, after forming the cap layer 330, further includes: the filler layer 310 is removed.
The fill layer 310 is removed to expose the various surfaces of the channel layer 210 in preparation for subsequent formation of a gate structure overlying the channel layer 210.
In this embodiment, the process of removing the filling layer 310 includes an isotropic etching process.
The isotropic etching process includes an isotropic wet etching process that can achieve a large etching selectivity ratio, thereby reducing damage to the channel layer 210 while removing the filler layer 310 cleanly.
Referring to fig. 10, a gate structure 400 is formed across the channel layer structure 200 and the spacers 340, the gate structure 400 covering the exposed top, bottom and sidewalls of the channel layer 210.
The gate structure 400 is used to control the turning on or off of the channel of the transistor.
In this embodiment, the gate structure 400 includes a gate dielectric layer 410 and a gate electrode layer 420 on the gate dielectric layer 410.
The gate dielectric layer 410 is used to isolate the gate structure 400 from the channel layer 210.
The material of gate dielectric layer 410 includes HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following. In this embodiment, the material of gate dielectric layer 410 comprises a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer comprises HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
The gate electrode layer 420 includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer.
The work function layer is used to adjust the threshold voltage of the transistor. For a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer comprises one or more of TiN, taN, taSiN, taAlN and TiAlN; for an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer comprises one or two of TiAl and TiAlC.
The electrode layer is used for leading out the electricity of the gate electrode layer. In this embodiment, the material of the electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN and TiAlC.
In other embodiments, the gate structure may be a polysilicon gate structure, depending on the process requirements.
Referring to fig. 11 to 15 in combination, a first partition opening 430 penetrating the gate structure 400 is formed on top of the partition wall 340, and the first partition opening 430 partitions the gate structure 400 along an extension direction of the gate structure 400.
The first partition openings 430 are used to provide spatial locations for subsequent formation of first gate partition structures.
In this embodiment, an anisotropic etching process is used to form the first isolation opening 430 through the gate structure 400.
The anisotropic etching process comprises an anisotropic dry etching process, the longitudinal etching rate of the anisotropic dry etching process is greater than the transverse etching rate, equal and accurate pattern conversion can be obtained, the bottom of the first partition opening 430 is accurately positioned at the top of the partition wall 340, and meanwhile, the anisotropic dry etching process has better directivity, and is beneficial to improving the shape quality and the dimensional accuracy of the side wall of the first partition opening 430.
Specifically, referring to fig. 11, the step of forming a first partition opening 430 through the gate structure 400 on top of the partition wall 340 includes: a mask layer 500 is formed overlying the gate structure 400.
The mask layer 500 is used as an etch mask for etching the gate structure 400.
In this embodiment, the material of the mask layer 500 includes one or more of silicon oxide and silicon nitride, i.e., the mask layer 500 may have a single-layer structure or a stacked-layer structure. As an example, the material of the mask layer 500 is silicon nitride, i.e., the mask layer 500 has a single layer structure, and the silicon nitride has a high hardness, which is advantageous for protecting the top of the gate structure 400 during etching.
Specifically, a chemical vapor deposition process is used to form a mask layer 500 that covers the gate structure 400.
Referring to fig. 11 and 12 in combination, the mask layer 500 over the spacer 340 is removed, forming a mask opening 510 exposing the gate structure 400.
The gate structure 400 is etched through the mask opening 510 to improve the accuracy of the pattern transfer.
Specifically, referring to fig. 11, a photoresist 600 is formed to cover the mask layer 500, and a pattern opening 610 is formed in the photoresist 600.
Referring to fig. 12, in the step of removing the mask layer 500 above the partition walls 340, a part of the thickness of the mask layer 500 is removed, forming a mask opening 510.
In this embodiment, a protective material layer covering the bottom and the sidewall of the mask opening 510 is further required to be formed later, and then the protective material layer covering the bottom of the mask opening 510 is removed, so that a part of the thickness of the mask layer 500 is removed, and the remaining part of the thickness of the mask layer 500 is remained at the bottom of the mask opening 510, which is beneficial to reducing or avoiding the damage to the gate structure 400 caused by the process of removing the protective material layer covering the bottom of the mask opening 510.
In other embodiments, a mask opening penetrating the mask layer may be formed, where the mask opening exposes the gate structure, and the exposed gate structure is directly removed through the mask opening to form the first isolation opening.
Referring to fig. 13 and 14 in combination, after forming the mask opening 510, before removing the gate structure 400 located on top of the isolation wall 340 along the mask opening 510, further includes: a protective layer 530 is formed covering the sidewalls of the mask opening 510.
The protective layer 530 serves to reduce the opening size of the mask opening 510, thereby reducing the top size of the first partition opening 430 in the step of forming the first partition opening 430, thereby reducing the bottom size of the first partition opening 430, which is advantageous in ensuring that the first partition opening 430 is formed on the top of the partition wall 340.
After the first partition opening 430 is further formed, the protection layer 530 needs to be removed, and then the protection layer 530 needs to be made of a material that is easy to remove, and for this reason, in this embodiment, the material of the protection layer 530 includes silicon oxide.
Specifically, referring to fig. 13, the step of forming the protective layer 530 on the sidewall of the mask opening 510 includes: a layer 520 of protective material is formed to cover the bottom and sidewalls of the mask opening 510 and the top of the mask layer 500.
The protective material layer 520 is used to directly form the protective layer 530.
In this embodiment, the protective material layer 520 also covers the sidewalls of the pattern opening 610 and the top of the photoresist 600.
In other embodiments, after forming the mask opening, the photoresist may be removed before forming the protective material layer, and then in the step of forming the protective material layer, the protective material layer covers only the bottom and the side walls of the mask opening and the top of the mask layer.
In this embodiment, the protective material layer 520 is formed by an atomic layer deposition process.
The thickness uniformity of the protective material layer 520 formed by adopting the atomic layer deposition process is good, and the protective material layer 520 has good step coverage capability, so that the bottom and the side wall of the mask opening 510 and the top of the mask layer 500 can be well covered by the protective material layer 520 in a conformal manner.
Accordingly, the material of the protective material layer 520 includes silicon oxide.
Referring to fig. 14, the protective material layer 520 at the bottom of the mask opening 510 and the top of the mask layer 500 is removed, and the protective material layer 520 at the sidewall of the mask opening 510 remains as the protective layer 530.
The protective material layer 520 at the bottom of the mask opening 510 is removed, exposing the remaining thickness of the mask layer 500 in preparation for forming the first partition opening 430.
In this embodiment, the protective material layer 520 at the bottom of the mask opening 510 and at the top of the mask layer 500 is removed by using an anisotropic dry etching process, which is more directional and is beneficial to forming the protective layer 530 with better sidewall quality.
Referring to fig. 15, the gate structure 400 on top of the isolation wall 340 is removed along the mask opening 510, forming a first partition opening 430.
Accordingly, the mask layer 500 is also removed along the mask openings 510 for the remaining portion of the thickness.
Referring to fig. 16, after forming the first partition opening 430, further includes: the protective layer 530 is removed.
The protective layer 530 is removed, in preparation for subsequent formation of a first gate isolation structure in the first isolation opening 430,
in this embodiment, the protection layer 530 is removed by using an isotropic wet etching process, which can achieve a larger etching selectivity, so that the damage to the gate structure 400 and the mask layer 500 can be reduced while the protection layer 530 is removed cleanly.
In this embodiment, after forming the first partition opening 430, the method further includes: photoresist 600 is removed.
In this embodiment, in the same step, the isotropic wet etching process is used to remove the protective layer 530 and the photoresist 600, thereby improving the process efficiency.
Referring to fig. 17, a first gate blocking structure 440 is formed in the first blocking opening 430.
The first gate isolation structure 440 serves to insulate the gate structures 400 of the adjacent first and second device regions 100A and 100B from each other.
The hardness and the compactness of the material of the first gate isolation structure 440 are high, so that the probability of damage of the first gate isolation structure 440 in the formation process of the semiconductor structure is reduced, and the isolation performance of the first gate isolation structure 440 is ensured.
For this reason, in the present embodiment, the material of the first gate isolation structure 440 is silicon nitride, and has better isolation performance. In other embodiments, the first gate isolation structure may also be other nitrogen-containing dielectric materials.
With continued reference to fig. 17, after forming the first gate isolation structure 440, the forming method further includes: the gate structure 400 at the boundary of the adjacent third device regions 100C is removed, and a second partition opening 450 is formed, and the second partition opening 450 partitions the gate structure 400 along the extending direction of the gate structure 400.
The second partition openings 450 are used to provide spatial locations for subsequent formation of second gate partition structures.
In this embodiment, an anisotropic etching process is used to form the second isolation opening 450 through the gate structure 400.
Referring to fig. 18, a second gate blocking structure 460 is formed in the second blocking opening 450.
The second gate blocking structure 460 serves to insulate the gate structures 400 of adjacent third device regions 100C from each other.
Correspondingly, in the present embodiment, the material of the second gate isolation structure 460 is silicon nitride, and has better isolation performance. In other embodiments, the second gate isolation structure may also be other nitrogen-containing dielectric materials.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (20)
1. A semiconductor structure, comprising:
a substrate comprising a first device region and a second device region adjacent to each other;
the channel layer structure is respectively positioned on the substrates of the first device region and the second device region, and comprises one or more channel layers at intervals along the normal direction of the surfaces of the substrates;
an initial isolation wall protruding on the substrate at the junction of the first device region and the second device region, wherein the initial isolation wall covers opposite side walls of the channel layer structures of the first device region and the second device region;
The cap layer is positioned on the side wall of the initial isolation wall and covers part of the side wall of the initial isolation wall, which is higher than the top surface of the channel layer structure, a space is reserved between the bottom of the cap layer and the topmost channel layer, and the cap layer and the initial isolation wall are used as isolation walls together;
a gate structure on the substrate and crossing the channel layer structure and the isolation wall, wherein the gate structure covers the top, the bottom and the side wall of the channel layer exposed;
the grid isolation structure comprises a first grid isolation structure which is positioned at the top of the isolation wall and penetrates through the grid structure, and the grid isolation structure divides the grid structure along the extending direction of the grid structure.
2. The semiconductor structure of claim 1, wherein the cap layer further extends over a top surface of the initial isolation wall.
3. The semiconductor structure of claim 1, wherein the first device region and the second device region comprise a third device region;
the gate shut off structure further includes: and the second grid isolating structure is positioned on the substrate at the junction of the adjacent third device regions and penetrates through the grid structure.
4. The semiconductor structure of claim 1, wherein the material of the initial isolation wall comprises SiBCN or SiN.
5. The semiconductor structure of claim 1, wherein a material of the cap layer comprises SiC.
6. The semiconductor structure of claim 1, wherein the cap layer on the sidewalls of the initial spacer has a width of 10nm to 26nm.
7. The semiconductor structure of claim 1, wherein a material of the gate isolation structure comprises SiN.
8. The semiconductor structure of claim 1, wherein the material of the channel layer comprises a silicon, germanium, silicon germanium, or a group iii-v semiconductor material.
9. The semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric layer and a gate electrode layer on the gate dielectric layer;
the gate dielectric layer material comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following;
the material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.
10. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first device region and a second device region which are adjacent, channel layer structures are respectively formed on the substrate of the first device region and the second device region, the channel layer structures comprise one or more channel layers with intervals, and initial isolation walls which cover opposite side walls of the channel layer structures are formed on the substrate between the adjacent channel layer structures at the junction of the first device region and the second device region;
Forming a cap layer on the side wall of the initial isolation wall, wherein the cap layer covers part of the side wall of the initial isolation wall, which is higher than the top surface of the channel layer structure, a space is reserved between the bottom of the cap layer and the topmost channel layer, and the cap layer and the initial isolation wall are used as isolation walls together;
forming a gate structure crossing the channel layer structure and the isolation wall, wherein the gate structure covers the exposed top, bottom and side walls of the channel layer;
forming a first partition opening penetrating through the grid structure at the top of the isolation wall, wherein the first partition opening partitions the grid structure along the extending direction of the grid structure;
a first gate isolation structure is formed in the first isolation opening.
11. The method of forming a semiconductor structure of claim 10, wherein in the step of forming a cap layer on the sidewalls of the initial isolation wall, the cap layer also covers a top surface of the initial isolation wall.
12. The method of forming a semiconductor structure of claim 11, wherein forming a cap layer on the initial sidewall spacer comprises: forming a filling layer covering the channel layer structure and the side wall of the initial isolation wall part, wherein the top surface of the filling layer is lower than the top surface of the initial isolation wall;
Forming a capping material layer covering the filling layer and the initial isolation wall exposed by the filling layer;
removing the capping material layer covering the filling layer, and reserving the capping material layer covering the initial isolation wall exposed by the filling layer as a capping layer;
after forming the cap layer, the method further comprises: and removing the filling layer.
13. The method of forming a semiconductor structure of claim 10, wherein forming a first partition opening through the gate structure at a top of the spacer comprises: forming a mask layer covering the grid structure;
removing the mask layer above the isolation wall to form a mask opening exposing the gate structure;
and removing the grid structure positioned at the top of the isolation wall along the mask opening to form a first isolation opening.
14. The method of forming a semiconductor structure of claim 13, wherein in the step of removing the mask layer over the isolation wall, a portion of the thickness of the mask layer is removed to form the mask opening;
after forming the mask opening, before removing the gate structure located at the top of the isolation wall along the mask opening, the method further comprises: forming a protective layer covering the side wall of the mask opening;
After forming the first partition opening, the method further comprises: and removing the protective layer.
15. The method of forming a semiconductor structure of claim 14, wherein forming a protective layer on sidewalls of the mask opening comprises: forming a protective material layer covering the bottom and the side wall of the mask opening and the top of the mask layer;
and removing the protective material layer at the bottom of the mask opening and the top of the mask layer, and reserving the protective material layer at the side wall of the mask opening as a protective layer.
16. The method of forming a semiconductor structure of claim 10, wherein in the step of providing the substrate, the first device region and the second device region comprise a third device region;
after forming the first gate isolation structure, the forming method further includes: removing the grid structure positioned at the juncture of the adjacent third device regions to form a second partition opening, wherein the second partition opening partitions the grid structure along the extending direction of the grid structure;
and forming a second grid isolating structure in the second isolating opening.
17. The method of claim 12, wherein forming a capping material layer that covers the fill layer and the exposed initial isolation wall of the fill layer comprises an atomic layer deposition process or a chemical vapor deposition process.
18. The method of claim 12, wherein removing the capping material layer overlying the filler layer, leaving the capping material layer overlying the exposed initial spacer as a capping layer comprises an anisotropic etching process.
19. The method of forming a semiconductor structure of claim 12, wherein the process of removing the fill layer comprises an isotropic etching process.
20. The method of forming a semiconductor structure of claim 10, wherein in the step of providing the substrate, an interlayer dielectric layer is formed on the substrate to cover the substrate, a gate opening is formed in the interlayer dielectric layer, and a channel layer structure is formed in the gate opening.
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