CN117747615A

CN117747615A - Semiconductor structure and forming method thereof

Info

Publication number: CN117747615A
Application number: CN202211119768.1A
Authority: CN
Inventors: 章毅; 荆学珍
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2022-09-15
Filing date: 2022-09-15
Publication date: 2024-03-22

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding from the substrate, a grid structure crossing the fin part is formed on the substrate, a first dielectric layer covering the fin part and the side wall of the grid structure is also formed on the substrate, and a first hard mask layer is also formed on the first dielectric layer and the grid structure; forming a stop layer on the first hard mask layer, wherein the grinding rate of the stop layer is smaller than that of the first hard mask layer; performing partition treatment, including: forming a partition opening penetrating through the stop layer and the first hard mask layer on the substrate, wherein the partition opening also extends along a first direction and penetrates through the grid structure between the adjacent grid structures, or extends along a second direction and penetrates through the grid structure between the adjacent grid structures; forming a partition material layer filling the partition opening and covering the top of the stop layer, wherein the partition material layer in the partition opening is used as a partition structure; and removing the partition material layer higher than the stop layer. The invention is beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. Transistors are currently being widely used as one of the basic semiconductor devices. Therefore, with the improvement of the density and the integration level of the semiconductor device, the gate size of the transistor is also shorter and shorter, the control capability of the traditional planar transistor on the channel current is weakened, a short channel effect occurs, the leakage current is increased, and the electrical performance of the semiconductor device is finally affected.

To better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the current semiconductor process, a Gate cutting (Gate Cut) technology is generally adopted to Cut off the strip-shaped Gate, the Cut-off Gate corresponds to different transistors, the integration level of the transistors can be improved, meanwhile, a single diffusion break (SDB, single diffusion break) structure is adopted to Cut off the strip-shaped fin parts, the structure is used for electrically isolating active areas at two sides of the SDB, and the contact spacing (contact poly pitch, CPP) of polysilicon can be reduced.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a substrate and a fin part protruding from the substrate, the fin part extends along a first direction and is arranged in parallel along a second direction, a grid structure crossing the fin part is formed on the substrate, the grid structure covers part of the top and part of the side wall of the fin part, the grid structure extends along the second direction and is arranged in parallel along the first direction, a first dielectric layer covering the fin part and the side wall of the grid structure is also formed on the substrate, a hard mask layer is also formed on the first dielectric layer and the grid structure, and the first direction is perpendicular to the second direction; the stop layer is positioned on the hard mask layer, and the grinding rate of the stop layer is smaller than that of the hard mask layer; and the isolating structure extends along the first direction and penetrates through the stop layer, the hard mask layer and the grid electrode structure between the adjacent grid electrode structures, and/or extends along the second direction and penetrates through the stop layer, the hard mask layer and the grid electrode structure between the adjacent grid electrode structures.

Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding from the substrate, the fin part extends along a first direction and is arranged in parallel along a second direction, a grid structure crossing the fin part is formed on the substrate, the grid structure covers part of the top and part of the side wall of the fin part, the grid structure extends along the second direction and is arranged in parallel along the first direction, a first dielectric layer covering the fin part and the side wall of the grid structure is also formed on the substrate, a first hard mask layer is also formed on the first dielectric layer and the grid structure, and the first direction is perpendicular to the second direction; forming a stop layer on the first hard mask layer, wherein the grinding rate of the stop layer is smaller than that of the first hard mask layer; performing partition processing to form a partition structure, wherein the partition structure extends along a first direction and penetrates through the stop layer, the first hard mask layer and the gate structure between the adjacent fin parts, and/or extends along a second direction and penetrates through the stop layer, the first hard mask layer and the fin parts between the adjacent gate structures; the partition treatment includes: forming a partition opening penetrating through the stop layer and the first hard mask layer on the substrate, wherein the partition opening also extends along a first direction and penetrates through the grid structure between the adjacent grid structures, or extends along a second direction and penetrates through the grid structure between the adjacent grid structures; forming a partition material layer filling the partition opening and covering the top of the stop layer, wherein the partition material layer in the partition opening is used as a partition structure; and removing the partition material layer higher than the stop layer, and reserving the partition structure.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the semiconductor structure provided by the embodiment of the invention, the stop layer is positioned on the hard mask layer, and the grinding rate of the stop layer is smaller than that of the hard mask layer; in the embodiment of the invention, the step of forming the partition structure comprises the following steps: forming a partition opening, forming a filling partition opening, covering a partition material layer at the top of a stop layer, removing the partition material layer higher than the stop layer, and forming a partition structure, wherein the grinding rate of the stop layer is smaller than that of a hard mask layer, and in the step of removing the partition material layer higher than the stop layer, compared with the step of taking the top of the hard mask layer as a grinding stop position, the scheme takes the top of the stop layer as the grinding stop position, thereby being beneficial to reducing the damage of the stop layer in the process of removing the partition material layer higher than the stop layer, reducing the height difference of the stop layer around the partition structure, improving the flatness of the top surface of the stop layer, providing a better process platform for the subsequent process, and correspondingly being beneficial to improving the performance of a semiconductor structure.

In the forming method provided by the embodiment of the invention, a stop layer is formed on a first hard mask layer, the grinded rate of the stop layer is smaller than that of the first hard mask layer, a partition material layer filling a partition opening and covering the top of the stop layer is formed, the partition material layer in the partition opening is used as a partition structure, the partition material layer higher than the stop layer is removed, and the partition structure is reserved; in the embodiment of the invention, the polished rate of the stop layer is smaller than that of the first hard mask layer, so in the step of removing the partition material layer higher than the stop layer, compared with the step of taking the top of the first hard mask layer as a polishing stop position, the scheme takes the top of the stop layer as the polishing stop position, thereby being beneficial to reducing the damage of the stop layer in the process of removing the partition material layer higher than the stop layer, reducing the height difference of the stop layer around the partition structure, improving the top surface flatness of the stop layer, providing a better process platform for the subsequent process, and correspondingly being beneficial to improving the performance of the semiconductor structure.

Drawings

Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

FIGS. 5-7 are schematic diagrams illustrating a semiconductor structure according to an embodiment of the present invention;

fig. 8 to 18 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

The performance of current semiconductor structures is to be improved. The reason why the performance of a semiconductor structure is to be improved is now analyzed in conjunction with a method of forming the semiconductor structure.

Fig. 1 to 4 are schematic structural views corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a substrate 10 is provided, including a substrate 11 and a fin portion 12 protruding from the substrate 11, the fin portion 12 extends along a first direction and is arranged in parallel along a second direction, a gate structure 20 crossing the fin portion 12 is formed on the substrate 10, the gate structure 20 covers a part of top and a part of side wall of the fin portion 12, the gate structure 20 extends along the second direction and is arranged in parallel along the first direction, a dielectric layer covering the fin portion 12 and the side wall of the gate structure 20 is further formed on the substrate 10, a hard mask layer 30 is further formed on the dielectric layer and the gate structure 20, and the first direction is perpendicular to the second direction.

Referring to fig. 2, a partition opening 52 extending in the first direction and penetrating the hard mask layer 30 and the gate structure 20 between adjacent fins 12 is formed on the substrate 11.

Referring to fig. 3, a partition material layer 51 filling the partition openings 52 and covering the top of the hard mask layer 30 is formed.

Referring to fig. 4, the partition material layer 51 higher than the hard mask layer 30 is removed, leaving the partition material layer 51 located in the partition openings 52 as the partition structure 50.

The isolation material layer 51 higher than the hard mask layer 30 is removed by a polishing process, and during the polishing process, the polishing rate of the material of the isolation material layer 51 is similar to the polishing rate of the material of the hard mask layer 30, in particular, the isolation material layer 51 is usually made of silicon nitride material, and the hard mask layer 30 is usually made of silicon oxide material, so that during the polishing process, the problem that the hard mask layer 30 near the isolation structure 50 is excessively polished is easily caused, and after the isolation material layer 51 higher than the hard mask layer 30 is removed, a recess (loading) defect is easily caused in the hard mask layer 30 at the contact position between the top of the isolation structure 50 and the hard mask layer 30, which results in poor flatness of the top surfaces of the isolation structure 50 and the hard mask layer 30, affecting the subsequent manufacturing process of the semiconductor structure, and further affecting the performance of the semiconductor structure.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, where a stop layer is formed on a first hard mask layer, the polishing rate of the stop layer is smaller than that of the first hard mask layer, a partition material layer filling a partition opening and covering the top of the stop layer is formed, the partition material layer in the partition opening is used as a partition structure, the partition material layer higher than the stop layer is removed, and the partition structure is reserved; in the embodiment of the invention, the polished rate of the stop layer is smaller than that of the first hard mask layer, so in the step of removing the partition material layer higher than the stop layer, compared with the step of taking the top of the first hard mask layer as a polishing stop position, the scheme takes the top of the stop layer as the polishing stop position, thereby being beneficial to reducing the damage of the stop layer in the process of removing the partition material layer higher than the stop layer, reducing the height difference of the stop layer around the partition structure, improving the top surface flatness of the stop layer, providing a better process platform for the subsequent process, and correspondingly being beneficial to improving the performance of the semiconductor structure.

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 5 to 7 are schematic structural views corresponding to an embodiment of the semiconductor structure of the present invention.

Referring to fig. 5 to 7 in combination, fig. 5 is a top view, fig. 6 is a cross-sectional view along AA direction of fig. 5, fig. 7 is a cross-sectional view along BB direction of fig. 5, and the semiconductor structure includes: the substrate 101 comprises a substrate 111 and a fin portion 121 protruding from the substrate 111, the fin portion 121 extends along a first direction and is arranged in parallel along a second direction, a grid structure 201 crossing the fin portion 121 is formed on the substrate 101, the grid structure 201 covers part of the top and part of the side wall of the fin portion 121, the grid structure 201 extends along the second direction and is arranged in parallel along the first direction, a first dielectric layer 141 covering the fin portion 121 and the side wall of the grid structure 201 is also formed on the substrate 101, a hard mask layer 301 is also formed on the first dielectric layer 141 and the grid structure 201, and the first direction is perpendicular to the second direction; a stop layer 401 on the hard mask layer 301, wherein the polishing rate of the stop layer 401 is smaller than that of the hard mask layer 301; a blocking structure (not labeled) extending in a first direction and penetrating the stop layer 401, the hard mask layer 301, and the gate structure 201 between adjacent gate structures 121, and/or extending in a second direction and penetrating the stop layer 401, the hard mask layer 301, and the fin structures 121 between adjacent gate structures 201.

The substrate 101 provides a process operation basis for the formation process of the semiconductor structure. Wherein the semiconductor structure comprises a fin field effect transistor (FinFET).

In this embodiment, the substrate 101 includes a device region (not shown) and a resistive region (not shown).

The device region is used to form a transistor device and the resistive region is used to form a resistor or a device and a resistor.

The present embodiment is described taking a semiconductor structure as a fin field effect transistor as an example.

In this embodiment, the material of the substrate 111 is silicon, and in other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or another type of substrate such as a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.

The fin 121 is used to provide a channel of the fin field effect transistor. In this embodiment, the material of fin 121 includes silicon, germanium, silicon germanium, or a group iii-v semiconductor material.

In this embodiment, the semiconductor structure further includes: an isolation layer 131 is located on the substrate 111 and covers a portion of the sidewalls of the fin 121. The isolation layer 131 is a shallow trench isolation (shallow trench isolation, STI) structure used to achieve isolation between different devices, such as in CMOS fabrication processes, STI structures are typically formed between NMOS and PMOS transistors. In this embodiment, the material of the isolation layer 131 is an insulating material. As an example, the material of the isolation layer 131 is silicon oxide.

The gate structure 201 is used to control the turning on and off of the channel of the transistor. In this embodiment, the gate structure 201 includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer.

The gate dielectric layer is used for isolating the gate structure 201 and fins. The gate dielectric layer material comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La (La) ₂ O ₃ One or more of the following. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer comprises HfO ₂ 、ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ Etc. The gate dielectric layer may further include a gate oxide layer, where the gate oxide layer is located between the high-k gate dielectric layer and the fin. Specifically, the material of the gate oxide layer may be silicon oxide.

In this embodiment, one or more of the materials TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC of the gate electrode layer.

In this embodiment, the gate structure 201 is a metal gate structure. Thus, the gate electrode layer includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer. The work function layer is used for adjusting the threshold voltage of the transistor, and the electrode layer is used for leading out the electricity of the metal gate structure.

In other embodiments, the gate structure may be a polysilicon gate structure, depending on the process requirements.

The first dielectric layer 141 is used to isolate adjacent devices, and the first dielectric layer 141 is also used to provide a process basis for forming the gate structure 201.

The material of the first dielectric layer 141 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

The hard mask layer 301 is used as an etch mask for forming a partition structure and also to provide a process basis for forming an interconnect plug in a subsequent process.

In this embodiment, the material of the hard mask layer 301 includes one or more of silicon oxide and silicon nitride, i.e., the hard mask layer 301 may have a single-layer structure or a stacked-layer structure. As an example, the material of the hard mask layer 301 is silicon oxide and silicon nitride, i.e., the hard mask layer 301 is a multi-layered structure including a silicon nitride layer and a silicon oxide layer covering the silicon nitride layer.

The stop layer 401 serves as a polishing stop when forming the partition structure.

In this embodiment, the step of forming the partition structure includes: forming a partition opening, forming a filling partition opening, covering a partition material layer on the top of a stop layer 401, removing the partition material layer higher than the stop layer 401, and forming a partition structure, wherein the polishing rate of the stop layer 401 is smaller than that of the hard mask layer 301, and in the step of removing the partition material layer higher than the stop layer 401, compared with the step of taking the top of the hard mask layer as a polishing stop position, the scheme takes the top of the stop layer 401 as the polishing stop position, thereby being beneficial to reducing the damage of the stop layer in the process of removing the partition material layer higher than the stop layer 401, reducing the height difference of the stop layer 401 around the partition structure, improving the top surface flatness of the stop layer 401, providing a better process platform for subsequent processing, and correspondingly being beneficial to improving the performance of a semiconductor structure.

In this embodiment, the material of the stop layer 401 includes a metal material.

The lower polishing rate of the metal material is advantageous in reducing damage to the stop layer 401 during removal of the partition material layer higher than the stop layer 401, thereby improving the flatness of the stop layer 401.

In this embodiment, the material of the stop layer 401 includes a titanium-containing metal material.

The low polishing rate of the titanium-containing metal material is advantageous in reducing damage to the stop layer 401 in removing the partition material layer higher than the stop layer 401, thereby improving the flatness of the stop layer 401, and the titanium-containing metal material as the stop layer 401 is advantageous in improving the accuracy of the opening dimension when forming the partition opening.

Specifically, in the present embodiment, the titanium-containing metal material includes titanium, titanium nitride, or titanium aluminum.

The grinding speed of titanium, titanium nitride or titanium aluminum is smaller, so that damage to the stop layer 401 is reduced in the process of removing the partition material layer higher than the stop layer 401, the flatness of the stop layer 401 is improved, meanwhile, titanium nitride can be used for forming a high-resistance structure in a subsequent middle-section process, and the process efficiency is correspondingly improved.

The thickness of the stop layer 401 is not too large or too small. If the thickness of the stop layer 401 is too large, the volume of the semiconductor structure is easily excessively large, and the development direction of high integration of the semiconductor structure is difficult to be complied with; if the thickness of the stop layer 401 is too small, it is difficult to achieve a good polishing stop effect when the top of the stop layer 401 is used as a polishing stop in the step of removing the partition material layer higher than the stop layer 401, so that it is difficult to reduce the height difference of the stop layer 401 around the partition structure, improve the flatness of the top surface of the stop layer 401, and further, provide a good process platform for subsequent processes, thereby affecting the performance of the semiconductor structure correspondingly. For this reason, in this embodiment, the thickness of the stopper layer 401 is 50nm to 200nm.

It should be noted that, in this embodiment, in the subsequent middle-stage process, the first hard mask layer 301 is also required to be used as a process platform to form the interconnection plug, and for this purpose, in this embodiment, the stop layer 401 is located on the first hard mask layer 301.

In this embodiment, the material of the stop layer 401 is titanium nitride, and the stop layer 401 is located in the resistive region.

In this embodiment, the stop layer 401 is made of titanium nitride, so that a higher resistance can be provided, and therefore, the stop layer 401 is located in the resistance region, so that a resistance meeting the process requirement can be formed by using the stop layer 401, further, the process cost is saved, and meanwhile, the process efficiency is improved.

In this embodiment, the isolation structure includes a gate isolation structure 501 extending in the first direction and penetrating the stop layer 401, the hard mask layer 301, and the gate structure 201 between adjacent fin structures 121, and a fin isolation structure 601 extending in the second direction and penetrating the stop layer 401, the hard mask layer 301, and the fin structures 121 between adjacent gate structures 201.

In other embodiments, the blocking structure may further include only gate blocking structures extending in the first direction and penetrating the stop layer, the hard mask layer, and the gate structure between adjacent fin structures, or the blocking structure may further include only fin blocking structures extending in the second direction and penetrating the stop layer, the hard mask layer, and the fin between adjacent gate structures.

The gate isolation structures 501 are used to achieve mutual insulation between the gate structures 201.

In this embodiment, the material of the gate isolation structure 501 includes silicon nitride, silicon carbide, or silicon carbonitride. The hardness of silicon nitride, silicon carbide or silicon carbonitride is high, the compactness is good, and the insulation property is good, so that the isolation performance of the gate isolating structure 501 is ensured.

Fin isolation structure 601 is a single diffusion break (SDB, single diffusion break) structure for electrically isolating devices on both sides of the SDB structure, which is advantageous for reducing polysilicon contact pitch (contact poly pitch, CPP).

In this embodiment, the fin isolation structure 601 includes silicon nitride, silicon carbide, or silicon carbonitride. The hardness of silicon nitride, silicon carbide or silicon carbonitride is high, the compactness is good, and the insulation property is good, so that the isolation performance of the fin isolation structure 601 is ensured.

In this embodiment, the semiconductor structure further includes: a second dielectric layer 701 covers the stop layer 401 and the isolation structure.

The second dielectric layer 701 is used to provide a process platform for a subsequent process, and is also used to isolate adjacent interconnect structures in the subsequent process.

The material of the second dielectric layer 701 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

Referring to fig. 8 and 9 in combination, fig. 8 is a top view, fig. 9 is a cross-sectional view along the AA direction of fig. 16, a substrate 100 is provided, including a substrate 110 and a fin 120 protruding from the substrate 110, the fin 120 extends along a first direction (as shown in the X direction in fig. 8) and is arranged in parallel along a second direction (as shown in the Y direction in fig. 8), a gate structure 200 is formed on the substrate 100 and spans the fin 120, the gate structure 200 covers a portion of the top and a portion of the sidewall of the fin 120, the gate structure 200 extends along the second direction and is arranged in parallel along the first direction, a first dielectric layer (not shown in fig. 8 and 9, as shown in fig. 140 corresponding to the cross-sectional view along the BB direction in fig. 8) is further formed on the substrate 100, and a first hard mask layer 300 is further formed on the first dielectric layer and the gate structure 200, and the first direction is perpendicular to the second direction.

The substrate 100 provides a process operation basis for the formation process of the semiconductor structure. Wherein the semiconductor structure comprises a fin field effect transistor (FinFET).

In this embodiment, the material of the substrate 110 is silicon, and in other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or another type of substrate such as a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.

In this embodiment, the semiconductor structure further includes: an isolation layer 130 is located on the substrate 110 and covers a portion of the sidewalls of the fin 120. The isolation layer 130 is a shallow trench isolation structure for achieving isolation between different devices, such as STI structures typically formed between NMOS transistors and PMOS transistors in CMOS fabrication processes. In this embodiment, the material of the isolation layer 130 is an insulating material. As an example, the material of the isolation layer 130 is silicon oxide.

In this embodiment, along the first direction, the substrate 110 includes the device regions 100a and the isolation regions 100b between adjacent device regions 100a, and the gate structures 200 are formed in the device regions 100a and the isolation regions 100b, respectively.

The gate structure 200 formed in the device region 100a is used to form a device, and then the fin 120 of the isolation region 100b is exposed by removing the gate structure 200 formed in the isolation region 100b, thereby forming a fin isolation structure penetrating the fin 120 between adjacent gate structures 200.

The fin 120 is used to provide a channel of the fin field effect transistor. In this embodiment, the material of fin 120 includes silicon, germanium, silicon germanium, or a group iii-v semiconductor material.

The gate structure 200 is used to control the turning on and off of the channel of the transistor. In this embodiment, the gate structure 200 includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer.

The gate dielectric layer is used to isolate the gate structure 200 from the fin. The gate dielectric layer material comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La (La) ₂ O ₃ One or more of the following. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer comprises HfO ₂ 、ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ Etc. The gate dielectric layer may further include a gate oxide layer, where the gate oxide layer is located between the high-k gate dielectric layer and the fin. Specifically, the material of the gate oxide layer may be silicon oxide.

In this embodiment, the gate structure 200 is a metal gate structure. Thus, the gate electrode layer includes a work function layer (not shown), and an electrode layer (not shown) on the work function layer. The work function layer is used for adjusting the threshold voltage of the transistor, and the electrode layer is used for leading out the electricity of the metal gate structure.

The first dielectric layer is used to isolate adjacent devices and also to provide a process basis for forming the gate structure 200.

The first dielectric layer is made of an insulating material and comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

The first hard mask layer 300 is used as an etch mask for forming a partition structure and also used as a process basis for forming an interconnect plug in a subsequent process.

In this embodiment, the material of the first hard mask layer 300 includes one or more of silicon oxide and silicon nitride, i.e., the first hard mask layer 300 may have a single-layer structure or a stacked-layer structure. As an example, the material of the first hard mask layer 300 is silicon oxide and silicon nitride, i.e., the first hard mask layer 300 is a multi-layered structure including a silicon nitride layer and a silicon oxide layer covering the silicon nitride layer.

Referring to fig. 10, a stop layer 400 is formed on the first hard mask layer 300, and the polishing rate of the stop layer 400 is smaller than that of the first hard mask layer 300.

The stop layer 400 is used as a polishing stop in the subsequent formation of the partition structure.

In this embodiment, the step of forming the partition structure subsequently includes: forming a partition opening, forming a filling partition opening, covering a partition material layer on the top of the stop layer 400, removing the partition material layer higher than the stop layer 400, and forming a partition structure, wherein the polishing rate of the stop layer 400 is smaller than that of the hard mask layer 300, and in the step of removing the partition material layer higher than the stop layer 400, compared with the step of taking the top of the hard mask layer as a polishing stop position, the scheme takes the top of the stop layer 400 as the polishing stop position, thereby being beneficial to reducing the damage of the stop layer in the process of removing the partition material layer higher than the stop layer 400, reducing the height difference of the stop layer 400 around the partition structure, improving the top surface flatness of the stop layer 400, providing a better process platform for subsequent processing, and correspondingly being beneficial to improving the performance of a semiconductor structure.

In this embodiment, the process of forming the stop layer 400 includes a plasma enhanced chemical vapor deposition process, a plasma enhanced atomic layer deposition process, or a physical vapor deposition process.

The film layer of the stop layer 400 formed by the ion-enhanced chemical vapor deposition process, the plasma-enhanced atomic layer deposition process or the physical vapor deposition process is relatively uniform, and the surface flatness is relatively good.

In this embodiment, the material of the stop layer 400 includes a metal material.

The lower polishing rate of the metal material is advantageous in reducing damage to the stop layer 400 in removing the partition material layer higher than the stop layer 400, thereby improving the flatness of the stop layer 400.

In this embodiment, the material of the stop layer 400 includes a titanium-containing metallic material.

The low polishing rate of the titanium-containing metal material is advantageous in that damage to the stopper layer 400 is reduced in removing the partition material layer higher than the stopper layer 400, thereby improving the flatness of the stopper layer 400, and the titanium-containing metal material as the stopper layer 401 is advantageous in improving the accuracy of the opening dimension when forming the partition opening.

The polishing rate of titanium, titanium nitride or titanium aluminum is smaller, which is beneficial to reducing the damage to the stop layer 400 in the process of removing the partition material layer higher than the stop layer 400, thereby improving the flatness of the stop layer 400, and simultaneously, the titanium nitride can be used for forming a high-resistance structure in the subsequent middle-section process, and correspondingly improving the process efficiency.

It should be noted that the thickness of the stop layer 400 is not too large or too small. If the thickness of the stop layer 400 is too large, the volume of the semiconductor structure is easily excessively large, and it is difficult to conform to the development direction of high integration of the semiconductor structure; if the thickness of the stop layer 400 is too small, it is difficult to achieve a good polishing stop effect when the top of the stop layer 400 is used as a polishing stop in the step of removing the partition material layer higher than the stop layer 400, so that it is difficult to reduce the height difference of the stop layer 400 around the partition structure, improve the flatness of the top surface of the stop layer 400, and further, provide a good process platform for subsequent processes, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the thickness of the stop layer 400 is 50nm to 200nm.

It should be noted that, in the present embodiment, in the subsequent middle-stage process, the first hard mask layer 300 is also required to be used as a process platform to form the interconnection plug, and for this purpose, the stop layer 400 is formed on the first hard mask layer 300 in the present embodiment.

Referring to fig. 10 to 17, a blocking process is performed to form a blocking structure (not shown) that extends in a first direction and penetrates the stop layer 400, the first hard mask layer 300, and the gate structure 200 between adjacent fin structures 120, and/or extends in a second direction and penetrates the stop layer 400, the first hard mask layer 300, and the fin structures 120 between adjacent gate structures 200.

In this embodiment, the isolation structures include a gate isolation structure 500 extending in a first direction and penetrating the stop layer 400, the first hard mask layer 300, and the gate structure 200 between adjacent fins 120, and a fin isolation structure 600 extending in a second direction and penetrating the stop layer 400, the first hard mask layer 300, and the fins 120 between adjacent gate structures 200.

The gate blocking structure 500 is used to achieve mutual insulation between the gate structures 200.

In this embodiment, the material of the gate isolation structure 500 includes silicon nitride, silicon carbide, or silicon carbonitride. The hardness of silicon nitride, silicon carbide or silicon carbonitride is high, the compactness is good, and the insulation property is good, so that the isolation performance of the grid isolation structure 500 is ensured.

Fin isolation structure 600 is a single diffusion break (SDB, single diffusion break) structure for electrically isolating devices on both sides of the SDB structure, which is advantageous for reducing polysilicon contact pitch (contact poly pitch, CPP).

In this embodiment, the fin isolation structure 600 comprises silicon nitride, silicon carbide, or silicon carbonitride. The hardness of silicon nitride, silicon carbide or silicon carbonitride is high, the compactness is good, and the insulation property is good, so that the isolation performance of the fin isolation structure 600 is ensured.

Accordingly, in this embodiment, the partition processing includes: forming a partition opening on the substrate 110 penetrating the stop layer 400 and the first hard mask layer 300, the partition opening further extending along the first direction and penetrating the gate structure 200 between adjacent gate structures 120, or extending along the second direction and penetrating the fin structures 120 between adjacent gate structures 200; forming a partition material layer filling the partition opening and covering the top of the stop layer 400, wherein the partition material layer in the partition opening is used as a partition structure; the partition material layer higher than the stop layer 400 is removed, and the partition structure is maintained.

Specifically, in the present embodiment, the partition processing includes: referring to fig. 10 to 12 and 17 in combination, the gate structures 200 between adjacent fin structures 120 are subjected to a first blocking process to form gate blocking structures 500, and referring to fig. 13 to 16 in combination, the fin structures 120 between adjacent gate structures 200 are subjected to a second blocking process to form fin blocking structures 600.

In this embodiment, after the partition material layer corresponding to the first partition process is formed, the second partition process is performed before the current partition material layer higher than the stop layer 400 is removed, and the partition material layer higher than the stop layer 400 is removed in the same step.

Referring to fig. 10 to 12 in combination, fig. 10 to 12 are views corresponding to cross-sectional views along the AA direction of fig. 8, and a partition material layer corresponding to a first partition process for forming a partition structure extending along the first direction and penetrating the stop layer 400, the first hard mask layer 300, and the gate structure 200 between adjacent fins 120 is formed.

The partition material layer is used for forming a partition structure. The first blocking process corresponds to a blocking material layer as the first blocking material layer 510 for forming the gate blocking structure 500.

Accordingly, in the present embodiment, the material of the first partition material layer 510 includes silicon nitride, silicon carbide, or silicon carbonitride.

Referring to fig. 10, the partition process further includes: a second hard mask layer is formed overlying the stop layer 400 prior to forming the partition openings.

Specifically, in this embodiment, the partition opening corresponding to the first partition process is taken as a first partition opening, and the second mask layer corresponding to the first partition process is taken as the first sub-mask layer 310, where the first partition process further includes: a first sub-mask layer 310 is formed overlying the stop layer 400 prior to forming the first partition openings.

The first sub-mask layer 310 is used as an etch mask for forming the first partition openings.

In this embodiment, the material of the first sub-mask layer 310 includes one or more of silicon oxide and silicon nitride, i.e., the first sub-mask layer 310 may have a single-layer structure or a stacked-layer structure. As an example, the material of the first sub-mask layer 310 is silicon oxide and silicon nitride, i.e., the first sub-mask layer 310 is a multi-layered structure including a silicon nitride layer and a silicon oxide layer covering the silicon nitride layer.

Referring to fig. 11, the second hard mask layer is patterned to form a first mask opening (not shown) exposing the top of the stop layer 400.

Specifically, in this embodiment, the first mask opening corresponding to the first partition process is used as a first sub-mask opening, and the first sub-mask layer 310 is patterned to form a first sub-mask opening exposing the top of the stop layer 400.

The first sub-mask opening is used as a mask opening for forming a first partition opening.

With continued reference to fig. 11, a partition opening is formed along the first mask opening through the stop layer 400, the first hard mask layer 400, and the gate structure 200.

Specifically, in this embodiment, a first partition opening 520 is formed along the first sub-mask opening, which penetrates the stop layer 400, the first hard mask layer 400, and the gate structure 200.

The first block opening 520 is used to provide a spatial location for forming the gate block structure 500.

In this embodiment, the first partition openings 520 are formed by using an anisotropic etching process.

Specifically, an anisotropic dry etching process is adopted, and has the characteristic of anisotropic etching, so that the damage to the substrate 110 at the bottom of the first partition opening 520 is reduced by selecting the anisotropic dry etching process, and meanwhile, the anisotropic dry etching process has more etching directionality, and is beneficial to improving the shape quality and the dimensional accuracy of the side wall of the first partition opening 520.

In this embodiment, the second mask layer is used as the mask to etch the stop layer 400, the first hard mask layer 400 and the gate structure 200, so that in the step of forming the partition opening penetrating the stop layer 400, the first hard mask layer 400 and the gate structure 200 along the first mask opening, a part of the thickness of the second hard mask layer is also etched and removed.

Specifically, in the present embodiment, in the step of forming the first partition opening 520 penetrating the stop layer 400, the first hard mask layer 400 and the gate structure 200 along the first sub-mask opening, a part of the thickness of the first sub-mask layer 310 is removed.

Referring to fig. 12, a partition material layer filling the partition openings and covering the top of the stop layer 400 is formed, and the partition material layer located in the partition openings serves as a partition structure.

Specifically, in the present embodiment, a first partition material layer 510 filling the first partition opening 520 and covering the top of the stop layer 400 is formed, and the first partition material layer 510 located in the first partition opening 520 serves as the gate partition structure 500.

The first barrier material layer 510 is used to form the gate barrier structure 500.

In this embodiment, in the step of forming the partition material layer filling the partition opening and covering the top of the stop layer 400, the partition material layer covers the remaining thickness of the second hard mask layer.

Specifically, in the present embodiment, in the step of forming the first partition material layer 510 filling the first partition opening 620 and covering the top of the stop layer 400, the first partition material layer 510 covers the remaining thickness of the first sub-hard mask layer 310.

Referring to fig. 13 to 15 in combination, fig. 13 is a view corresponding to a cross-sectional view of fig. 8 along the AA direction, and fig. 14 and 15 are views corresponding to a cross-sectional view of fig. 8 along the BB direction, a second partition process is formed to form a partition structure extending along the second direction and penetrating the stop layer 400, the first hard mask layer 300, and the fin 120 between adjacent gate structures 200.

The partition material layer is used for forming a partition structure. The second partition process corresponds to a partition material layer as the second partition material layer 610 for forming the fin partition structure 600.

Accordingly, in the present embodiment, the material of the second partition material layer 610 includes silicon nitride, silicon carbide, or silicon carbonitride.

Referring to fig. 13, the partition processing further includes: a second hard mask layer is formed overlying the stop layer 400 prior to forming the partition openings.

Specifically, in this embodiment, the partition opening corresponding to the second partition process is taken as a second partition opening, and the second mask layer corresponding to the second partition process is taken as the second sub-mask layer 320, where the second partition process further includes: a second sub-mask layer 320 is formed overlying the stop layer 400 prior to forming the second partition openings.

The second sub-mask layer 320 is used as an etch mask for forming the second partition openings.

In this embodiment, the material of the second sub-mask layer 320 includes one or more of silicon oxide and silicon nitride, i.e., the second sub-mask layer 320 may have a single-layer structure or a stacked-layer structure. As an example, the material of the second sub-mask layer 320 is silicon oxide and silicon nitride, i.e., the second sub-mask layer 320 is a multi-layered structure including a silicon nitride layer and a silicon oxide layer covering the silicon nitride layer.

Referring to fig. 14, the second hard mask layer is patterned to form a first mask opening (not shown) exposing the top of the stop layer 400.

Specifically, in this embodiment, the second sub-mask layer 320 is patterned with the first mask opening corresponding to the second isolation process as the second sub-mask opening, so as to form the second sub-mask opening exposing the top of the stop layer 400.

The second sub-mask opening is used as a mask opening for forming a second partition opening.

With continued reference to fig. 14, a partition opening is formed along the first mask opening that penetrates the stop layer 400, the first hard mask layer 300, and the fin 120.

Specifically, in this embodiment, a second isolation opening 620 is formed along the second sub-mask opening, which penetrates the stop layer 400, the first hard mask layer 400, and the fin 120.

The second partition openings 620 are used to provide spatial locations for forming fin partition structure 600.

In this embodiment, the second partition opening 620 is formed by using an anisotropic etching process.

Specifically, an anisotropic dry etching process is adopted, and has the characteristic of anisotropic etching, so that the damage to the substrate 110 at the bottom of the second partition opening 620 is reduced by selecting the anisotropic dry etching process, and meanwhile, the anisotropic dry etching process has more etching directionality, thereby being beneficial to improving the shape quality and the dimensional accuracy of the side wall of the second partition opening 620.

In this embodiment, the second mask layer is used as the mask to etch the stop layer 400, the first hard mask layer 400 and the fin 120, so that in the step of forming the partition opening penetrating the stop layer 400, the first hard mask layer 400 and the fin 120 along the first mask opening, part of the second hard mask layer is also etched and removed, or the second hard mask layer is removed to expose the top of the first partition material layer 510, so that the subsequent removal of the partition material layer higher than the stop layer 400 in the same step is also prepared.

Specifically, in the present embodiment, in the step of forming the second isolation opening 620 penetrating the stop layer 400, the first hard mask layer 400, and the fin 120 along the second sub-mask opening, a portion of the thickness of the second sub-mask layer 320 is removed, or the second sub-mask layer 320 is removed.

In this embodiment, the step of forming the partition opening includes: the gate structure 200 of the isolation region 100b is removed, and a trench (not shown) is formed in the first dielectric layer 140, the trench exposing a portion of the fin 120.

Specifically, in the present embodiment, the step of forming the second partition opening 620 includes: the gate structure 200 of the isolation region 100b is removed, and a trench is formed in the first dielectric layer 140, the trench exposing a portion of the fin 120.

The exposed portions of fin 120 are subsequently removed by the trenches.

In this embodiment, the gate structures 200 are first formed uniformly, and then the gate structures 200 of the isolation regions 100b are removed according to the process requirements, which is beneficial to improving the flexibility of forming the trenches and reducing the modification of the process of forming the gate structures 200.

In this embodiment, the exposed fin 120 is removed by the trench, and a partition opening is formed that partitions the fin 120 in the first direction. Specifically, in the present embodiment, the exposed fin 120 is removed by the trench, and the second partition opening 620 dividing the fin 120 along the first direction is formed.

Referring to fig. 15, a partition material layer filling the partition openings and covering the top of the stop layer 400 is formed, and the partition material layer located in the partition openings serves as a partition structure.

Specifically, in the present embodiment, the second partition material layer 610 filling the second partition opening 620 and covering the top of the stop layer 400 is formed, and the second partition material layer 610 located in the second partition opening 620 serves as the fin partition structure 600.

The second layer of partition material 610 is used to form the fin partition structure 600.

Specifically, in the present embodiment, the second partition material layer 610 covers the first partition material layer 510 located on the stop layer 400, in preparation for the subsequent removal of the first partition material layer 510 and the second partition material layer 610 together, which are higher than the stop layer 400.

In other embodiments, after forming the partition opening to be filled and covering the partition material layer on top of the stop layer in the partition process, before removing the partition material layer higher than the stop layer, the method may further include: a planar material layer is formed overlying the partition material layer.

The flat material layer is used for further improving the top surface flatness of the partition material layer, and is beneficial to further improving the top surface flatness of the partition structure and the stop layer after the partition material layer higher than the stop layer is removed later.

The material of the flat material layer can be the same as that of the partition material layer, so that the diversity of the material is reduced, the flat material layer and the partition material layer are better fused, and a top surface with higher flatness is formed.

Referring to fig. 16 and 17 in combination, fig. 16 is a view corresponding to a cross-sectional view of fig. 8 in the BB direction, and fig. 17 is a view corresponding to a cross-sectional view of fig. 8 in the AA direction, the partition material layer higher than the stop layer 400 is removed, and the partition structure remains.

In this embodiment, the polishing rate of the stop layer 400 is smaller than that of the first hard mask layer 300, so in the step of removing the partition material layer higher than the stop layer 400, compared with using the top of the first hard mask layer as a polishing stop, the method of using the top of the stop layer 400 as a polishing stop is beneficial to reducing the damage of the stop layer 400 in the process of removing the partition material layer higher than the stop layer 400, thereby reducing the height difference of the stop layer 400 around the partition structure, improving the top surface flatness of the stop layer 400, providing a better process platform for the subsequent process, and correspondingly facilitating the improvement of the performance of the semiconductor structure.

Specifically, in this embodiment, the first partition material layer 510 and the second partition material layer 610 higher than the stop layer 400 are removed in the same step, and the gate partition structure 500 and the fin partition structure 600 are reserved, so that the process flow is simplified, the process cost is saved, and the process efficiency is improved.

In this embodiment, a chemical mechanical polishing process is used to remove the partition material layer higher than the stop layer 400.

Specifically, in the present embodiment, the first and second partition material layers 510 and 610 higher than the stop layer 400 are removed using a chemical mechanical polishing process.

The cmp process combines the advantages of chemical polishing and mechanical polishing, and can ensure that the materials of the first partition material layer 510 and the second partition material layer 610 higher than the stop layer 400 are removed simultaneously and efficiently, and a preferable surface is obtained.

In the step of removing the partition material layer higher than the stop layer 400, the polishing selection ratio between the partition material layer and the stop layer 400 is not preferably too small. If the polishing selection ratio of the partition material layer to the stop layer 400 is set, excessive damage to the stop layer 400 is easily caused in the step of removing the partition material layer higher than the stop layer 400, and it is difficult to reduce the height difference of the stop layer 400 around the partition structure, so that it is difficult to improve the flatness of the top surface of the stop layer 400, and further it is difficult to provide a better process platform for the subsequent process, and accordingly, the performance of the semiconductor structure is affected. For this reason, in the step of removing the partition material layer higher than the stop layer 400 in this embodiment, the polishing selection ratio of the partition material layer to the stop layer 400 is 100 or more.

In this embodiment, in the step of removing the partition material layer higher than the stop layer 400, the remaining thickness of the second hard mask layer is removed.

Specifically, in the step of removing the first partition material layer 510 and the second partition material layer 610 higher than the stop layer 400 in this embodiment, the first sub-mask layer 310 with the remaining thickness is removed, so that the stop layer 400 is taken as a removal stop position, thereby achieving the effect of obtaining the top surface with higher flatness.

In other embodiments, a flat material layer covering the partition material layer is further formed, and correspondingly, the step of removing the partition material layer higher than the stop layer further includes: the planar material layer is removed.

In other embodiments, the second partition treatment may be performed after the partition structure corresponding to the first partition treatment is formed, or the first partition treatment may be performed after the partition structure corresponding to the second partition treatment is formed, or the first partition treatment may be performed before the current partition material layer higher than the stop layer is removed after the partition material layer corresponding to the second partition treatment is formed, and the partition material layer higher than the stop layer is removed in the same step.

Referring to fig. 18, after removing the partition material layer higher than the stop layer 400, the forming method further includes: a second dielectric layer 700 is formed covering the stop layer 400 and the partition structure.

The second dielectric layer 700 is used for providing a process platform for a subsequent process and also for isolating adjacent interconnect structures in the subsequent process.

The material of the second dielectric layer 700 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

It should be noted that, in another embodiment, the same points as those of the previous embodiment are not repeated, and the difference between the two embodiments is that: and forming an interconnection plug by taking the stop layer as an etching stop layer.

Specifically, the step of forming the interconnect plug includes: and patterning the second dielectric layer by taking the stop layer as an etching stop layer to form a second mask opening.

The second mask opening is used as a mask opening for the patterned stop layer.

The step of forming an interconnect plug further comprises: the stop layer is patterned along the second mask opening, forming a third mask opening separated by the stop layer.

The third mask opening is used as a mask opening for patterning the first hard mask layer and the first dielectric layer.

The stopping layer is used for carrying out graph transfer, so that the accuracy of graph transfer is improved.

The step of forming an interconnect plug further comprises: the first hard mask layer and the first dielectric layer are patterned along the third mask opening to form an interconnect opening that is isolated by the first hard mask layer under the stop layer or by the first hard mask layer under the stop layer and the first dielectric layer.

The interconnect openings are used to provide a spatial location for forming interconnect plugs.

The step of forming an interconnect plug further comprises: an interconnect plug is formed in the interconnect opening. The interconnection plug comprises a grid plug positioned at the top of the grid structure and used for leading out the electricity of the grid structure, and a source-drain plug positioned at the top of the source-drain doping layer and used for leading out the electricity of the source-drain doping layer.

After forming the interconnection plug, the second dielectric layer and the stop layer are removed to prepare for the subsequent process.

It should be further noted that, in yet another embodiment, the same points as those of the previous embodiment are not repeated, and the difference between them is that: patterning the stop layer, and keeping the stop layer in the resistor area.

Specifically, the substrate includes a device region (not shown) and a resistive region (not shown).

In the step of forming the stop layer, the material of the stop layer is titanium nitride; after removing the partition material layer higher than the stop layer, the forming method further includes: patterning the stop layer, and keeping the stop layer in the resistor area.

According to the embodiment, the stopping layer is made of titanium nitride, so that higher resistance can be provided, and therefore, the stopping layer is located in the resistance region, so that the stopping layer can be used for forming the resistance meeting the process requirement, further, the process cost is saved, and meanwhile, the process efficiency is improved.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

the substrate comprises a substrate and fin parts protruding from the substrate, the fin parts extend along a first direction and are arranged in parallel along a second direction, a grid structure crossing the fin parts is formed on the substrate, the grid structure covers part of the top and part of the side wall of the fin parts, the grid structure extends along the second direction and is arranged in parallel along the first direction, a first dielectric layer covering the fin parts and the side wall of the grid structure is also formed on the substrate, a hard mask layer is also formed on the first dielectric layer and the grid structure, and the first direction is perpendicular to the second direction;

The stopping layer is positioned on the hard mask layer, and the grinding rate of the stopping layer is smaller than that of the hard mask layer;

and the isolating structure extends along the first direction and penetrates through the stop layer, the hard mask layer and the grid structure between the adjacent grid structures, and/or extends along the second direction and penetrates through the stop layer, the hard mask layer and the grid structure between the adjacent grid structures.

2. The semiconductor structure of claim 1, wherein a material of the stop layer comprises a metallic material.

3. The semiconductor structure of claim 2, wherein the metallic material comprises a titanium-containing metallic material.

4. The semiconductor structure of claim 3, wherein the titanium-containing metallic material comprises titanium, titanium nitride, or titanium aluminum.

5. The semiconductor structure of claim 1, wherein the stop layer has a thickness of 50nm to 200nm.

6. The semiconductor structure of claim 1, wherein the material of the hard mask layer comprises one or more of silicon oxide, silicon nitride, amorphous silicon, or aluminum oxide.

7. The semiconductor structure of claim 1, wherein the substrate comprises a device region and a resistive region, the stop layer being of titanium nitride, the stop layer further being located in the resistive region.

8. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a substrate and fin parts protruding from the substrate, the fin parts extend along a first direction and are arranged in parallel along a second direction, a grid structure crossing the fin parts is formed on the substrate, the grid structure covers part of the top and part of the side wall of the fin parts, the grid structure extends along the second direction and is arranged in parallel along the first direction, a first dielectric layer covering the fin parts and the side wall of the grid structure is also formed on the substrate, a first hard mask layer is also formed on the first dielectric layer and the grid structure, and the first direction is perpendicular to the second direction;

forming a stop layer on the first hard mask layer, wherein the grinding rate of the stop layer is smaller than that of the first hard mask layer;

performing partition processing to form a partition structure, wherein the partition structure extends along the first direction and penetrates through the stop layer, the first hard mask layer and the gate structure between adjacent fin parts, and/or extends along the second direction and penetrates through the stop layer, the first hard mask layer and the fin parts between adjacent gate structures;

The partition processing includes: forming a partition opening penetrating through the stop layer and the first hard mask layer on the substrate, wherein the partition opening also extends along the first direction and penetrates through the gate structures between adjacent gate structures, or extends along the second direction and penetrates through the fin structures between adjacent gate structures;

forming a partition material layer filling the partition opening and covering the top of the stop layer, wherein the partition material layer in the partition opening is used as the partition structure;

and removing the partition material layer higher than the stop layer, and retaining the partition structure.

9. The method of forming a semiconductor structure of claim 8, wherein the isolating process comprises: performing a first blocking treatment on the grid structures between the adjacent fin parts, and performing a second blocking treatment on the fin parts between the adjacent fin parts; wherein,

after forming a partition structure corresponding to the first partition treatment, performing the second partition treatment;

or after forming a partition structure corresponding to the second partition treatment, performing the first partition treatment;

or after forming the partition material layer corresponding to the first partition treatment, performing the second partition treatment before removing the current partition material layer higher than the stop layer, and removing the partition material layer higher than the stop layer in the same step;

Or after forming the partition material layer corresponding to the second partition treatment, before removing the current partition material layer higher than the stop layer, performing the first partition treatment, and removing the partition material layer higher than the stop layer in the same step.

10. The method of forming a semiconductor structure of claim 8, wherein, along the first direction, the substrate includes device regions and isolation regions between adjacent device regions;

the grid structure is respectively formed in the device region and the isolation region;

the isolation treatment is used for forming an isolation structure which extends along the second direction and penetrates through the stop layer, the first hard mask layer and the fin part between the adjacent gate structures;

the step of forming the partition opening includes: removing the grid structure of the isolation region, and forming a groove in the first dielectric layer, wherein part of the fin part is exposed out of the groove;

and removing the exposed fin portion through the groove to form a partition opening for partitioning the fin portion along the first direction.

11. The method of forming a semiconductor structure of claim 8, wherein the isolating process further comprises: forming a second hard mask layer covering the stop layer before forming the partition opening;

Patterning the second hard mask layer to form a first mask opening exposing the top of the stop layer;

and forming a partition opening penetrating through the stop layer, the first hard mask layer and the fin portion along the first mask opening or forming a partition opening penetrating through the stop layer, the first hard mask layer and the gate structure.

12. The method of claim 11, wherein forming a partition opening along the first mask opening through the stop layer, the first hard mask layer, and the gate structure, or through the stop layer, the first hard mask layer, and the fin, removes a portion of the thickness of the second hard mask layer;

forming a partition material layer which fills the partition opening and covers the top of the stop layer, wherein the partition material layer covers the second hard mask layer with the residual thickness;

and in the step of removing the partition material layer higher than the stop layer, removing the residual thickness of the second hard mask layer.

13. The method of forming a semiconductor structure of claim 8, wherein after forming a spacer material layer filling the spacer opening and covering a top of the stop layer in the spacer process, before removing the spacer material layer higher than the stop layer, further comprising: forming a flat material layer covering the partition material layer;

The step of removing the partition material layer higher than the stop layer further includes: and removing the flat material layer.

14. The method of forming a semiconductor structure of claim 8, wherein after removing the layer of spacer material above the stop layer, the method further comprises: forming a second dielectric layer covering the stop layer and the partition structure;

using the stop layer as an etching stop layer, and patterning the second dielectric layer to form a second mask opening;

patterning the stop layer along the second mask opening to form a third mask opening isolated by the stop layer;

patterning the first dielectric layer and the first hard mask layer along the third mask opening to form an interconnection opening isolated by the first hard mask layer below the stop layer or the first dielectric layer below the stop layer;

forming an interconnect plug in the interconnect opening;

and removing the second dielectric layer and the stop layer after the interconnection plug is formed.

15. The method of forming a semiconductor structure of claim 8, wherein in the step of providing the substrate, the substrate includes a device region and a resistive region;

In the step of forming the stop layer, the material of the stop layer is titanium nitride;

after removing the partition material layer higher than the stop layer, the forming method further includes: and patterning the stop layer, and keeping the stop layer in the resistor region.

16. The method of forming a semiconductor structure of claim 8, wherein in the step of removing the partition material layer higher than the stop layer, a polishing selectivity of the partition material layer and the stop layer is greater than or equal to 100.

17. The method of forming a semiconductor structure of claim 8, wherein in the step of forming the stop layer, the material of the stop layer comprises a titanium-containing metallic material.

18. The method of forming a semiconductor structure of claim 17, wherein the titanium-containing metallic material comprises titanium, titanium nitride, or titanium aluminum.

19. The method of forming a semiconductor structure of claim 8, wherein the process of forming the stop layer comprises a plasma enhanced chemical vapor deposition process, a plasma enhanced atomic layer deposition process, or a physical vapor deposition process.

20. The method of claim 8, wherein a chemical mechanical polishing process is used to remove the layer of barrier material above the stop layer.