CN117316873A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN117316873A CN117316873A CN202210698096.8A CN202210698096A CN117316873A CN 117316873 A CN117316873 A CN 117316873A CN 202210698096 A CN202210698096 A CN 202210698096A CN 117316873 A CN117316873 A CN 117316873A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a method of forming the same, the semiconductor structure comprising: the substrate comprises a substrate and a fin part protruding from the substrate; a gate structure located on the substrate and crossing the fin, the gate structure covering part of the top and part of the side wall of the fin; the interlayer dielectric layer is positioned on the substrate at the side part of the grid structure and covers the side wall of the grid structure; a partition structure located between end portions of the adjacent gate structures, the partition structure being for dividing the gate structures in an extending direction of the gate structures; and the stop layer is positioned on the grid electrode structure, the partition structure and the interlayer dielectric layer. The embodiment of the invention is beneficial to the performance of the semiconductor device.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. The transistor is widely used as the most basic semiconductor device at present, so as to increase the element density and the integration level of the semiconductor device, the gate size of the planar transistor is also shorter and shorter, the control capability of the conventional planar transistor on channel current is weakened, a short channel effect is generated, a leakage current is generated, and the electrical performance of the semiconductor device is finally affected.
To better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the current process of forming the Gate, a Gate cutting (Gate Cut) technology is generally adopted to Cut off the strip-shaped Gate, and the Cut Gate corresponds to different transistors, so that the integration level of the transistors can be improved. In addition, when a plurality of gates are arranged in a row along the extending direction, the Gate cutting technique can reduce the pitch (Gate Cut CD) in the abutting direction between the disconnected gates after Gate cutting with high accuracy.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a substrate and a fin part protruding from the substrate; a gate structure on the substrate and crossing the fin, the gate structure covering a portion of the top and a portion of the sidewall of the fin; the interlayer dielectric layer is positioned on the substrate at the side part of the gate structure and covers the side wall of the gate structure; the isolating structure is positioned between the end parts of the adjacent grid structures and is used for dividing the grid structures in the extending direction of the grid structures; and the stop layer is positioned on the grid electrode structure, the partition structure and the interlayer dielectric layer.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding from the substrate, an interlayer dielectric layer is formed on the substrate, a gate opening is formed in the interlayer dielectric layer, and the gate opening spans across the fin part; forming a gate material layer in the gate opening, the gate material layer also covering the top of the inter-layer dielectric layer; forming a partition opening in the gate material layer, the partition opening dividing the gate material layer in an extending direction of the gate opening; forming a partition material layer in the partition opening; flattening the grid material layer and the partition material layer to form a grid structure and a partition structure, wherein the rest partition material layer is used as the partition structure; a stop layer is formed over the gate structure and the spacer structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the semiconductor structure provided by the embodiment of the invention, the stop layer is positioned on the gate structure and the partition structure, so that the stop layer is formed after the gate structure and the partition structure are formed in the forming process of the semiconductor structure, the stop layer is prevented from being damaged in the forming process of the partition structure, and accordingly, the performance of the semiconductor device is improved.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the gate material layer is formed in the gate opening, and the gate material layer also covers the top of the inter-layer dielectric layer, so that the stop position can be defined by using the gate material layer in the planarization process of the partition material layer, and the stop position is not required to be defined by using the stop layer, that is, the effect of the stop layer in forming the partition opening and the partition structure can be realized by using the gate material layer positioned on the top of the inter-layer dielectric layer, and the stop layer can be formed after the partition structure is formed, accordingly, the stop layer is prevented from being damaged in forming the partition structure, and the performance of the semiconductor device is improved.
Drawings
Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
FIGS. 7-9 are schematic diagrams illustrating an embodiment of a semiconductor structure according to the present invention;
fig. 10 to 20 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the performance of the current semiconductor structure needs to be improved. The reason why the performance of a semiconductor structure is to be improved is analyzed by combining a method for forming the semiconductor structure. Fig. 1 to 6 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1 and 2 in combination, fig. 1 is a top view of a fin and a gate structure, and fig. 2 is a cross-sectional view along an extension direction of the gate structure based on fig. 1, a base (not shown) is provided, including a substrate 100 and a fin 110 protruding from the substrate 100, a gate structure 120 is formed on the substrate 100 across the fin 110, and the gate structure 120 covers a top and a portion of a sidewall of the fin 110.
Referring to fig. 3, a stop layer 130 is formed on the gate structure 120.
Referring to fig. 4, a blocking opening 121 is formed in the gate structure 120 at a position to be cut in the gate structure 120.
Referring to fig. 5, a partition material layer 122 is formed in the partition openings 121, and a top surface of the partition material layer 122 is higher than a top surface of the stop layer 130.
Referring to fig. 6, the partition material layer 122 is planarized with the top surface of the stop layer 130 as a stop position, and the remaining partition material layer 122 serves as a partition structure 123.
The planarization process is performed on the partition material layer 122 with the top surface of the stop layer 130 as a stop position, and the partition material layer 122 and the stop layer 130 are removed at different rates, so that the stop layer 130 is damaged easily during the planarization process of the partition material layer 122 higher than the top surface of the stop layer 130, and in addition, the stop layer 130 is damaged easily during the formation of the partition opening 121, thereby degrading the performance of the semiconductor device.
In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: the substrate comprises a substrate and a fin part protruding from the substrate; a gate structure on the substrate and crossing the fin, the gate structure covering a portion of the top and a portion of the sidewall of the fin; the interlayer dielectric layer is positioned on the substrate at the side part of the gate structure and covers the side wall of the gate structure; the isolating structure is positioned between the end parts of the adjacent grid structures and is used for dividing the grid structures in the extending direction of the grid structures; and the stop layer is positioned on the grid electrode structure, the partition structure and the interlayer dielectric layer.
In the semiconductor structure provided by the embodiment of the invention, the stop layer is positioned on the gate structure and the partition structure, so that the stop layer is formed after the gate structure and the partition structure are formed in the forming process of the semiconductor structure, the stop layer is prevented from being damaged in the forming process of the partition structure, and accordingly, the performance of the semiconductor device is improved.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 7-9, schematic structural diagrams of an embodiment of the semiconductor structure of the present invention are shown.
Referring to fig. 7 to 9 in combination, fig. 7 is a cross-sectional view along an extension direction of the gate structure, fig. 8 is a cross-sectional view along an extension direction of the fin in the first region I, and fig. 9 is a cross-sectional view along an extension direction of the fin in the second region II, in which the semiconductor structure includes: a base (not shown) comprising a substrate 600 and a fin 610 protruding from the substrate 600; a gate structure 647 located on the substrate 600 and crossing the fin 610, the gate structure 647 covering a portion of the top and a portion of the sidewalls of the fin 610; an interlayer dielectric layer 621 on the substrate at the side of the gate structure 647, the interlayer dielectric layer 621 covering the side wall of the gate structure 647; a partition structure 648 between the end portions of the adjacent gate structures 648, the partition structure 648 being for dividing the gate structure 647 in the extending direction of the gate structure 647; a stop layer 664 is located over gate structure 647, isolation structure 648, and interlayer dielectric layer 621.
The substrate provides a process operation basis for the formation process of the semiconductor structure.
In this embodiment, the material of the substrate 600 is silicon, and in other embodiments, the material of the substrate may be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the substrate may be another type of substrate such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.
The fin 610 is used to provide a channel of a fin field effect transistor.
In this embodiment, the fin 610 and the substrate 600 are integrally formed. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
In this embodiment, the material of the fin 610 is the same as the material of the substrate 600, and the material of the fin 610 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the material of the fin may also be different from the material of the substrate.
In this embodiment, an isolation structure 697 is further formed on the substrate, and the isolation structure 697 covers a portion of the sidewall of the fin portion.
Isolation structures 697 are used to provide isolation between different devices, such as in a CMOS fabrication process, isolation structures 697 are typically formed between NMOS transistors and PMOS transistors. Specifically, the isolation structure 697 is a shallow trench isolation structure (Shallow Trench Isolation, STI).
The material of the isolation structure 697 is an insulating material. As an example, the material of the isolation structure 697 is silicon oxide.
Interlayer dielectric layer 621 serves to isolate adjacent devices from each other.
The material of the interlayer dielectric layer 621 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer is made of silicon oxide.
The gate structure is used to control the opening and closing of the conductive channel when the device is in operation. In this embodiment, the gate structure is a metal gate structure, and the gate structure includes a gate dielectric layer (not shown) and a gate electrode layer 660 covering the gate dielectric layer.
The gate electrode layer 660 is used as an external electrode for electrically connecting the gate structure to an external circuit.
The material of the gate electrode layer 660 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).
In this embodiment, the gate electrode layer 660 includes one or both of the work function layer 661 and the electrode layer 655.
In this embodiment, the work function layer 661 is used for adjusting the threshold voltage of the transistor. For example, when an NMOS transistor is formed, the work function layer 661 is an N-type work function layer, and a material of the N-type work function layer includes one or more of titanium aluminide and titanium aluminum carbide; when forming a PMOS transistor, the work function layer 661 is a P-type work function layer, and a material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.
The electrode layer 655 is used for electrical connection with an external circuit. The material of electrode layer 655 is a conductive material including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer 655 is tungsten.
The gate dielectric layer is used to electrically isolate the gate electrode layer 660 from the conductive channel.
In this embodiment, the gate dielectric layer material includes hafnium oxide (HfO 2 ) Zirconium oxide (ZrO) 2 ) Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al) 2 O 3 ) Silicon oxide (SiO) 2 ) And lanthanum oxide (La) 2 O 3 ) One or more of the following.
In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may be selected from zirconium oxide (ZrO 2 ) Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or aluminum oxide (Al) 2 O 3 ). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer, or the gate dielectric layer may include only the gate oxide layer.
Referring to fig. 8 and 9, in the step of providing a substrate in this embodiment, the substrate includes a first region I and a second region II, in which gate structures 647 are formed respectively, the first region I is used to form a short channel device, and the second region II is used to form a long channel device, and the device channel length of the first region I is smaller than the device channel length of the second region II.
In the present embodiment, in the first region I, the gate electrode layer 660 of the partial gate structure 647 includes only the work function layer 661, and the gate electrode layer 660 of the remaining gate structure 647 includes the work function layer 661 and the electrode layer 655 covering the work function layer 661, not including the work function layer.
The partition structure 648 serves to insulate the cut gate structures 647 from each other in the extending direction thereof.
In this embodiment, the material of the isolation structure 648 is silicon nitride, and in other embodiments, the material of the isolation structure may be one or more of silicon nitride and silicon oxide.
In a subsequent interrupt process, an interconnect structure (not shown) is formed on the stop layer 664. In forming an interconnect opening for receiving the interconnect structure, the stop layer 664 is used to define a stop position for the interconnect opening.
The stop layer 664 is disposed on the gate structures 647 and the isolation structures 648, so that the stop layer 664 is formed after the gate structures 647 and the isolation structures 648 are formed in the process of forming the semiconductor structures, thereby avoiding damage to the stop layer 664 in the process of forming the isolation structures 648, and accordingly improving the performance of the semiconductor device.
In this embodiment, the material of the stopping layer is silicon oxide, and in other embodiments, the material of the stopping layer may be one or more of silicon oxide, polysilicon, and titanium aluminide.
In this embodiment, the semiconductor structure includes an isolation layer 665, the isolation layer 665 being located between the stop layer 664 and the gate structure 647.
The isolation layer 665 serves to reduce the probability of oxidation of the gate structure 647 in a subsequent process.
For example, in this embodiment, the semiconductor structure further includes a conductive plug (not shown) on top of the gate structure and a dielectric layer (not shown) on a sidewall of the conductive plug, where the conductive plug is used to make an electrical connection between the semiconductor device and an external circuit. The dielectric layer is used for isolating adjacent conductive plugs.
In this embodiment, the material of the dielectric layer is silicon oxide, and oxygen is generally required to be introduced in the step of forming the dielectric layer, and the isolation layer 665 is used for isolating the introduced oxygen in the step of forming the dielectric layer, so as to prevent the gate structure 647 from being oxidized.
In this embodiment, the material of the isolation layer 665 is silicon nitride, and in other embodiments, the material of the isolation layer may be one or more of silicon nitride and silicon oxide.
Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 10 to 20 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.
Referring to fig. 10 and 11 in combination, fig. 10 is a top view of the fin and the interlayer dielectric layer, fig. 11 is a cross-sectional view taken along line AA1 based on fig. 10, and a base (not shown) is provided, including a substrate 800 and a fin 810 protruding from the substrate 800, the interlayer dielectric layer 821 being formed on the substrate 800, a gate opening 888 being formed in the interlayer dielectric layer 821, the gate opening 888 crossing the fin 810.
The substrate provides a process operation basis for the formation process of the semiconductor structure.
In this embodiment, the material of the substrate 800 is silicon, and in other embodiments, the material of the substrate may be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the substrate may be another type of substrate such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy integration.
The fin 810 is used to provide a channel of the fin field effect transistor.
In this embodiment, the fin 810 and the substrate 800 are integrally formed. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
In this embodiment, the material of the fin 810 is the same as the material of the substrate 800, and the material of the fin 810 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the material of the fin may also be different from the material of the substrate.
In this embodiment, an isolation structure 897 is further formed on the substrate, and the isolation structure 897 covers a portion of the side wall of the fin portion.
Isolation structures 897 are used to provide isolation between different devices, such as in a CMOS fabrication process, isolation structures 897 are typically formed between NMOS transistors and PMOS transistors. Specifically, the isolation structure 897 is a shallow trench isolation structure.
The material of the isolation structure 897 is an insulating material. As an example, the material of isolation structure 897 is silicon oxide.
The interlayer dielectric layer 821 is used for isolating adjacent devices.
The material of the interlayer dielectric layer 821 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer is made of silicon oxide.
The gate openings 888 are used to provide spatial locations for subsequent formation of a layer of gate material.
Referring to fig. 12 to 14 in combination, fig. 12 is a cross-sectional view along the extension direction of the gate material layer, fig. 13 is a cross-sectional view along the extension direction of the fin in the first region I, fig. 14 is a cross-sectional view along the extension direction of the fin in the second region II, a gate material layer 820 is formed in the gate opening 888, and the gate material layer 820 also covers the top of the inter-layer dielectric layer 821.
The gate material layer 820 is used to form a gate structure, and in addition, the gate material layer 820 is further used to define a stop position in the subsequent planarization process of the partition material layer, so that the stop position is not required to be defined by using the stop layer, that is, the effect of the stop layer in forming the partition opening and the partition structure can be achieved by using the gate material layer 820 located on the top of the interlayer dielectric layer 821, and further the stop layer can be formed after the partition structure is formed, accordingly, damage to the stop layer in forming the partition structure is avoided, and performance of the semiconductor device is improved.
Further, during the planarization process of the partition material layer, the partition material layer and the gate material layer 820 are easily made to have a selective ratio, thereby ensuring that the gate material layer 820 can define a stop position.
In this embodiment, in the step of forming the gate material layer 820 in the gate opening 888, the gate material layer 820 includes a gate dielectric layer (not shown) covering the bottom and the sidewall of the gate opening 888 and the top surface of the interlayer dielectric layer 821, and further includes a gate electrode layer 860 filled in the gate opening 888 where the gate dielectric layer is formed, and the gate electrode layer 860 further covers the gate dielectric layer located on the top surface of the interlayer dielectric layer 821.
The gate electrode layer 860 serves as an external electrode for electrically connecting the gate structure to an external circuit.
The material of the gate electrode layer 860 includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).
In this embodiment, the gate electrode layer 860 includes one or both of a work function layer 861 and an electrode layer 855.
In this embodiment, the work function layer 861 is used to adjust the threshold voltage of the transistor. For example, when an NMOS transistor is formed, the work function layer 861 is an N-type work function layer, the material of the N-type work function layer including one or more of titanium aluminum carbide; when forming a PMOS transistor, the work function layer 861 is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.
The electrode layer 855 is used for electrical connection with an external circuit. The material of the electrode layer 855 is a conductive material including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer 855 is tungsten.
The gate dielectric layer is used to electrically isolate the gate electrode layer 860 from the conductive channel.
In this embodiment, the gate dielectric layer material includes hafnium oxide (HfO 2 ) Zirconium oxide (ZrO) 2 ) Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al) 2 O 3 ) Silicon oxide (SiO) 2 ) And oxidationLanthanum (La) 2 O 3 ) One or more of the following.
In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer may be selected from zirconium oxide (ZrO 2 ) Hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or aluminum oxide (Al) 2 O 3 ). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer, or the gate dielectric layer may include only the gate oxide layer.
Specifically, the step of forming the gate material layer 820 in the gate opening 888 includes: forming an initial gate material layer (not shown) in the gate opening 888, the initial gate material layer also overlying the top of the inter-layer dielectric layer 821; after forming the initial gate material layer, the initial gate material layer is planarized until the thickness of the remaining initial gate material layer on the top surface of the interlayer dielectric layer 821 reaches the target thickness, and the remaining initial gate material layer serves as the gate material layer 820.
The initial gate material layer is used to form gate material layer 820.
Specifically, an initial gate material layer is formed by a chemical vapor deposition process.
The planarization process is performed, and the thickness of the remaining initial gate material layer reaches the target thickness, thereby facilitating the definition of a stop position for the gate material layer 820 to follow during the planarization process of the partition material layer,
in this embodiment, in the step of forming the gate material layer 820 in the gate opening 888, the thickness a (refer to fig. 12) of the gate material layer 820 on the top surface of the interlayer dielectric layer 821 should not be too small or too large, and if the thickness a of the gate material layer 820 is too small, it is not beneficial to define the stop position in the subsequent step of performing the first planarization process; if the thickness A of the gate material layer 820 is too large, the process time and the process cost are prolonged in the subsequent process of removing the gate material layer 820, and therefore, in this embodiment, the thickness A of the gate material layer 820 on the top surface of the interlayer dielectric layer 821 isTo->
In this embodiment, the planarization process includes a chemical mechanical polishing process, which is a global planarization process, which is beneficial to improving the overall flatness of the device plane and providing a flat and smooth surface for subsequent processes.
Referring to fig. 13 and 14, a gate material layer 820 is formed in a first region I for forming a short channel device and a second region II for forming a long channel device, respectively, and a device channel length of the first region I is smaller than a device channel length of the second region II.
In the present embodiment, in the first region I, the gate electrode layer 860 of the partial gate material layer 820 includes only the work function layer 861, and the gate electrode layer 860 of the remaining gate material layer 820 includes the work function layer 861 and the electrode layer 855 covering the work function layer 861, but does not include the work function layer.
Referring to fig. 15, after forming the gate material layer 820 and before forming the partition openings, further includes: a mask layer 873 is formed covering the gate material layer 820.
Mask layer 873 is used as an etch mask for subsequently forming a partition opening.
In this embodiment, the material of the mask layer 873 includes one or more of silicon oxide and silicon nitride, i.e., the mask layer 873 may have a single-layer structure or a stacked-layer structure. In this embodiment, the mask layer 873 is made of silicon oxide and silicon nitride, that is, the mask layer 873 has a multi-layer structure including a silicon oxide layer 870 and a silicon nitride layer 871 covering the silicon oxide layer 870.
In this embodiment, a carbon coating 864 and a photoresist layer 840 on the carbon coating 864 are formed on the silicon nitride layer 871.
The carbon coating 864 is used to provide a planar surface to achieve accurate image transfer.
The photoresist layer 840 is used for subsequent formation of a photoresist pattern layer.
Specifically, the photoresist layer 840 and the carbon coating layer 864 may be formed by coating.
Referring to fig. 16, a partition opening 841 is formed in the gate material layer 820, and the partition opening 841 partitions the gate material layer 820 in the extending direction of the gate opening 888.
The partition openings 841 are used to provide a spatial location for the subsequent formation of partition structures.
In the present embodiment, the partition openings 841 are formed in the gate material layer 820 at positions to be cut in the gate material layer 820, thereby facilitating the formation of the partition openings 841 according to the requirements.
Wherein, the gate material layer 820 is formed first, and the dividing is performed to facilitate the improvement of the process window of forming the gate material layer 820 in the gate opening.
Specifically, the photoresist layer 864 is converted into a photolithographic pattern layer (not shown) by means of exposure and development. The photolithographic pattern layer is formed with photolithographic openings (not shown) at the locations to be cut, which expose the top surface of the mask layer 873.
The photolithographic openings are used as mask openings for the subsequent formation of the partition openings 841.
After forming the photolithography opening, the carbon coating 864, the mask layer 873 and the gate material layer 820 at the bottom of the photolithography opening are sequentially etched to form the partition opening 841.
In this embodiment, the dry etching process is used to form the partition opening 841, and in other embodiments, the process of forming the partition opening may further include a wet etching process.
Referring to fig. 17, a partition material layer 850 is formed in a partition opening 841.
The partition material layer 850 is used to form a partition structure.
In this embodiment, a first deposition process is used to form a first partition material layer 851 in the partition opening 841, where the first partition material layer 851 covers the top surface of the gate material layer. A second partition material layer 852 is formed to cover the first partition material layer 851 using a second deposition process, and the second partition material layer 852 and the first partition material layer 851 constitute a partition material layer 850.
In this embodiment, the partition material layer 850 is formed by two different processes, so that the process is advantageously selected according to different requirements, and thus the quality of the formed partition material layer 850 can be improved, and the process cost can be saved.
The first partition material layer 851 is used for forming a partition structure later.
In this embodiment, the first deposition process includes an atomic layer deposition process, and the gap filling performance and the step coverage of the atomic layer deposition process are good, so that the filling capability of the first partition material layer 851 in the partition opening 841 is correspondingly improved, and the filling quality of the first partition material layer 851 is also improved.
In this embodiment, the second partition material layer 852 is removed in a subsequent step.
In this embodiment, the second deposition process includes a plasma enhanced chemical vapor deposition process, which is beneficial to quickly forming the second partition material layer 852, so as to reduce the time for forming the second partition material layer 852, and further save the process cost.
In this embodiment, the filling capability of the first deposition process is greater than that of the second deposition process, and the deposition rate of the second deposition process is greater than that of the first deposition process, so that a first partition material layer 851 with better filling quality and a second partition material layer 852 with faster forming speed can be formed, and the process cost is saved while the quality of the partition material layer 850 is ensured
In this embodiment, in the step of forming the partition material layer 850 in the partition opening 841, the materials of the first partition material layer 851 and the second partition material layer 852 are the same and are both silicon nitride, and in other embodiments, the materials of the first partition material layer and the second partition material layer may be different, and the first partition material layer and the second partition material layer may also be one or more of silicon nitride and silicon oxide.
Referring to fig. 18 and 19, the gate material layer 820 and the partition material layer 850 are planarized to form a gate structure 847 and a partition structure 848. The partition structure 848 serves to insulate the cut gate structures 847 from each other in the extending direction thereof.
In this embodiment, the planarization process is performed on the gate material layer 820 and the partition material layer 850 to form the gate structure 847 and the partition structure 848, including: the gate material layer 820 and the spacer material layer 850 are planarized until the height of the remaining gate material layer 820 reaches the target height, the remaining gate material layer 820 functioning as the gate structure 847 and the remaining spacer material layer 850 functioning as the spacer structure 848.
Specifically, the gate material layer 820 and the spacer material layer 850 are planarized until the height of the remaining gate material layer 820 reaches the target height, thereby facilitating the formation of the gate structures 847 and the spacer structures 848 reaching the target height, thereby providing a process basis for subsequent processes.
Referring to fig. 18, the step of planarizing the gate material layer 820 and the partition material layer 850 includes: the partition material layer 850 is first planarized with the top surface of the gate material layer 820 as a stop position.
The first planarization removes the spacer material layer 850 over the gate material layer 820, which advantageously provides a relatively planar surface for subsequent second planarization.
The gate material layer 820 is used to define the stop position, so that the stop position is not required to be defined by the stop layer, that is, the gate material layer 820 on top of the interlayer dielectric layer 821 can be used to realize the function of the stop layer in forming the partition opening 841 and the partition structure 848, and further the stop layer can be formed after the partition structure 848 is formed, accordingly, the stop layer is prevented from being damaged in forming the partition structure 848, and the performance of the semiconductor device is improved.
In the present embodiment, in the first planarization process, the ratio of the removal rates of the partition material layer 850 and the gate material layer 820 is not preferably too small, and if the ratio of the removal rates of the partition material layer 850 and the gate material layer 820 is too small, the gate material layer 820 is easily damaged when the partition material layer 850 is removed, so that it is difficult to define the stop position of the first planarization process by the top surface of the gate material layer 820. For this reason, in the present embodiment, in the first planarization process, the ratio of the removal rates of the partition material layer 850 and the gate material layer 820 is greater than 20.
Note that, the gate material layer 820 includes a gate dielectric layer and a gate electrode layer 860 covering the gate dielectric layer, and the material of the gate electrode layer 860 includes a metal or a metal compound, so that the hardness of the gate electrode layer is relatively high, the stop position of the first planarization process can be relatively well controlled, and the loss of the first planarization process to the gate material layer 820 is relatively small.
In other embodiments, the material of the gate material layer may be polysilicon, and when the partition material layer 850 is planarized, the selection ratio of the partition material layer to polysilicon (i.e., the ratio of the removal rates of the partition material layer 850 and the gate material layer 820) is also larger, so that a stop position of the first planarization process can be defined.
Referring to fig. 19, after the first planarization process, a second planarization process is performed on the gate material layer 820 with the top surface of the interlayer dielectric layer 821 as a stop position.
The second planarization removes the gate material layer 820 over the interlayer dielectric layer 821, which is advantageous for providing a relatively flat surface for the subsequent third planarization.
In the present embodiment, in the second planarization process, the ratio of the removal rates of the gate material layer 820 and the interlayer dielectric layer 821 is not preferably too small, and if the ratio of the removal rates of the gate material layer 820 and the interlayer dielectric layer 821 is too small, the interlayer dielectric layer 821 is easily damaged when the gate material layer 820 is removed, so that it is difficult to define the stop position of the second planarization process by the top surface of the interlayer dielectric layer 821. For this reason, in the present embodiment, in the second planarization process, the ratio of the removal rates of the gate material layer 820 and the interlayer dielectric layer 821 is greater than 50.
With continued reference to fig. 19, after the second planarization process, a third planarization process is performed on the gate material layer 820 and the partition material layer 850 until the height of the gate material layer 820 reaches the target height.
The third planarization process brings the height of the gate material layer 820 to the target height, thereby providing a relatively flat surface for subsequent processing.
In the present embodiment, in the third planarization process, the ratio of the removal rates of the gate material layer 820 and the partition material layer 850 is not preferably too small nor too large. If the ratio of the removal rates of the gate material layer 820 and the partition material layer 850 is too small, the removal rate of the gate material layer 820 is low, the removal rate of the partition material layer 850 is high, and the removal rates of the gate material layer 820 and the partition material layer 850 are inconsistent, thereby being unfavorable for the effect of the third planarization process; similarly, the ratio of the removal rates of the gate material layer 820 and the partition material layer 850 is too large, and the removal rates of the gate material layer 820 and the partition material layer 850 are not uniform, which is also disadvantageous to the effect of the third planarization process. For this reason, in the present embodiment, in the third planarization process, the ratio of the removal rates of the gate material layer 820 and the partition material layer 850 is 0.8 to 1.5, thereby facilitating the approaching of the removal rates of the gate material layer 820 and the partition material layer 850.
In this embodiment, the planarization process is a chemical mechanical polishing process, which is beneficial to improving the overall flatness of the device plane and providing a flat and smooth surface for subsequent processes.
Referring to fig. 20, a stop layer 864 is formed on the gate structure 847 and the partition structure 848.
In a subsequent interrupt process, an interconnect structure (not shown) is formed on the stop layer 864, and the stop layer 864 is used to define a stop location for the interconnect opening during formation of the interconnect opening for receiving the interconnect structure. In this embodiment, the stop layer 864 is formed by a chemical vapor deposition process, and in other embodiments, the process of forming the stop layer may be a furnace process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, in the step of forming the stop layer 864 on the gate structure 847 and the partition structure 848, the material of the stop layer is silicon oxide, and in other embodiments, the material of the stop layer may be one or more of silicon oxide, polysilicon, and titanium aluminide.
In this embodiment, before the stop layer 864 is formed, a spacer layer 865 is formed over the gate structure 847 and the isolation structure 848.
In this embodiment, the method for forming a semiconductor structure further includes: after the stop layer 864 and isolation layer 865 are formed over the gate structure 847 and the break structure 848, conductive plugs (not shown) for making electrical connection between the semiconductor device and external circuitry and dielectric layers (not shown) on the sidewalls of the conductive plugs are formed on top of the gate structure. The dielectric layer is used for isolating adjacent conductive plugs.
In this embodiment, the dielectric layer is made of silicon oxide, oxygen is generally required to be introduced in the step of forming silicon oxide, and the isolation layer 865 is used to isolate the introduced oxygen in the step of forming silicon oxide, so as to prevent the gate structure 847 from being oxidized.
The isolation layer 865 is used to isolate the incoming oxygen from oxidation of the gate structure 847 during subsequent formation of an oxide layer on both sides of the plug.
In this embodiment, the material of the isolation layer 865 is silicon nitride, and in other embodiments, the material of the isolation layer may be one or more of silicon nitride and silicon oxide.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (18)
1. A semiconductor structure, comprising:
the substrate comprises a substrate and a fin part protruding from the substrate;
a gate structure located on the substrate and crossing the fin, the gate structure covering part of the top and part of the side wall of the fin;
the interlayer dielectric layer is positioned on the substrate at the side part of the grid structure and covers the side wall of the grid structure;
a partition structure located between end portions of the adjacent gate structures, the partition structure being for dividing the gate structures in an extending direction of the gate structures;
and the stop layer is positioned on the grid electrode structure, the partition structure and the interlayer dielectric layer.
2. The semiconductor structure of claim 1, wherein the gate structure is a metal gate structure.
3. The semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric layer, and a gate electrode layer overlying the gate dielectric layer;
the material of the gate dielectric layer comprises one or more of hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, aluminum oxide, silicon oxide and lanthanum oxide; the material of the gate electrode layer includes one or more of titanium nitride, tantalum, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.
4. The semiconductor structure of claim 1, wherein the material of the isolation structure comprises one or more of silicon nitride and silicon oxide.
5. The semiconductor structure of claim 1, wherein the material of the stop layer comprises one or more of silicon oxide, polysilicon, and titanium aluminide.
6. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a fin part protruding from the substrate, an interlayer dielectric layer is formed on the substrate, a grid opening is formed in the interlayer dielectric layer, and the grid opening spans across the fin part;
forming a gate material layer in the gate opening, wherein the gate material layer also covers the top of the interlayer dielectric layer;
forming a partition opening in the gate material layer, the partition opening dividing the gate material layer in an extending direction of the gate opening;
forming a partition material layer in the partition opening;
flattening the grid material layer and the partition material layer to form a grid structure and a partition structure;
a stop layer is formed over the gate structure and the partition structure.
7. The method of forming a semiconductor structure of claim 6, wherein forming a layer of gate material in the gate opening comprises: forming an initial gate material layer in the gate opening, wherein the initial gate material layer also covers the top of the interlayer dielectric layer;
and flattening the initial gate material layer until the thickness of the residual initial gate material layer positioned on the top surface of the interlayer dielectric layer reaches the target thickness, wherein the residual initial gate material layer is used as the gate material layer.
8. The method of forming a semiconductor structure according to claim 6 or 7, wherein in the step of forming a gate material layer in the gate opening, a thickness of the gate material layer on the top surface of the interlayer dielectric layer isTo the point of
9. The method of claim 6 or 7, wherein the planarization process comprises a chemical mechanical polishing process.
10. The method of forming a semiconductor structure of claim 6, wherein planarizing the gate material layer and the spacer material layer to form a gate structure and a spacer structure comprises: and flattening the grid material layer and the partition material layer until the height of the rest grid material layers reaches the target height, wherein the rest grid material layers are used as grid structures, and the rest partition material layers are used as partition structures.
11. The method of forming a semiconductor structure of claim 10, wherein planarizing said gate material layer and said spacer material layer comprises: taking the top surface of the grid electrode material layer as a stop position, and carrying out first planarization treatment on the partition material layer;
after the first planarization treatment is carried out, carrying out second planarization treatment on the grid material layer by taking the top surface of the interlayer dielectric layer as a stop position;
and after the second planarization treatment, performing third planarization treatment on the grid material layer and the partition material layer until the height of the grid material layer reaches the target height.
12. The method of forming a semiconductor structure of claim 11, wherein a ratio of removal rates of the partition material layer and the gate material layer in the first planarization process is greater than or equal to 20;
in the second planarization process, a ratio of removal rates of the gate material layer and the interlayer dielectric layer is greater than or equal to 50;
in the third planarization process, a ratio of removal rates of the partition material layer and the gate material layer is 0.8 to 1.5.
13. The method of forming a semiconductor structure of claim 6, wherein in the step of forming a gate material layer in the gate opening, the gate material layer includes a gate dielectric layer covering a bottom and sidewalls of the gate opening and a top surface of the interlayer dielectric layer, and further including a gate electrode layer filled in the gate opening where the gate dielectric layer is formed, the gate electrode layer further covering the gate dielectric layer on the top surface of the interlayer dielectric layer.
14. The method of forming a semiconductor structure of claim 13, wherein the material of the gate dielectric layer comprises one or more of hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, aluminum oxide, silicon oxide, and lanthanum oxide; the material of the gate electrode layer includes one or more of titanium nitride, tantalum, titanium chloride, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.
15. The method of forming a semiconductor structure of claim 6, wherein forming a layer of partition material in the partition opening comprises: forming a first partition material layer in the partition opening by adopting a first deposition process, wherein the first partition material layer covers the top surface of the grid material layer;
forming a second partition material layer covering the first partition material layer by adopting a second deposition process, wherein the second partition material layer and the first partition material layer form a partition material layer;
wherein the filling capacity of the first deposition process is greater than that of the second deposition process, and the deposition speed of the second deposition process is greater than that of the first deposition process.
16. The method of forming a semiconductor structure of claim 15, wherein the first deposition process comprises an atomic layer deposition process and the second deposition process comprises a plasma enhanced chemical vapor deposition process.
17. The method of forming a semiconductor structure of claim 6, wherein in the step of forming a partition material layer in the partition opening, a material of the partition material layer includes: one or more of silicon nitride and silicon oxide.
18. The method of forming a semiconductor structure of claim 6, wherein in the step of forming a stop layer over the gate structure and the blocking structure, a material of the stop layer comprises: one or more of silicon oxide, polysilicon, and titanium aluminide.
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