CN102800679B - The forming method of the memory cell of flash memory - Google Patents
The forming method of the memory cell of flash memory Download PDFInfo
- Publication number
- CN102800679B CN102800679B CN201210301659.1A CN201210301659A CN102800679B CN 102800679 B CN102800679 B CN 102800679B CN 201210301659 A CN201210301659 A CN 201210301659A CN 102800679 B CN102800679 B CN 102800679B
- Authority
- CN
- China
- Prior art keywords
- layer
- opening
- side wall
- memory cell
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
A kind of forming method of the memory cell of flash memory, including: Semiconductor substrate is provided, semiconductor substrate surface has floating gate layer, there is in floating gate layer the first opening, first opening exposes the surface of Semiconductor substrate, insulating barrier is passed through mutually isolated between floating gate layer and Semiconductor substrate, floating gate layer surface has control grid layer, interlayer dielectric layer is passed through mutually isolated between control grid layer and floating gate layer, control grid layer surface has mask layer, there is the second opening, the second opening and the first opening through in mask layer, and the second opening exposes control grid layer surface；Sidewall at the first opening forms the first side wall；Sidewall at the second opening forms the second side wall, and the second side coping flushes with mask layer surface；Using selective epitaxial depositing operation to form source line layer in the first opening and the second opening, the top of source line layer is not higher than the surface of mask layer.The memory cell stable performance of the flash memory formed.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the formation of the memory cell of a kind of flash memory
Method.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type: analog circuit,
Digital circuit and D/A hybrid circuit, an important kind during wherein memory device is digital circuit.Closely
Nian Lai, in memory device, the development of flash memory (flash memory) is the rapidest.The main spy of flash memory
Point is the information that can keep storage in the case of not powered for a long time；And there is integrated level height, access speed
Hurry up, be prone to the advantages such as erasing and rewriting, thus obtained extensively in the multinomial field such as microcomputer, Automated condtrol
General application.
In prior art, the memory cell of flash memory refer to Fig. 1, including:
Semiconductor substrate 100；It is positioned at the floating gate layer 101 on described Semiconductor substrate 100 surface, described floating boom
Having the first opening (not shown) in layer 101, described first opening exposes the table of Semiconductor substrate 100
Face, mutually isolated by insulating barrier 103 between described floating gate layer 101 and Semiconductor substrate 100；It is positioned at
The control grid layer 104 on described floating gate layer 101 surface is logical between described control grid layer 104 and floating gate layer 101
Cross interlayer dielectric layer 105 mutually isolated；It is positioned at the mask layer 106 on described control grid layer 104 surface, described
Having the second opening (not shown) in mask layer 106, described second opening and the first opening are through, and institute
State the second opening and expose control grid layer 104 surface；It is positioned at the source line layer of the first opening and the second opening
108, electrically insulate between described source line layer 108 and control grid layer 104 and floating gate layer 101；It is positioned at mask layer
106, control grid layer 104 and the word line layer 111 of floating gate layer 101 both sides, described word line layer 111 and floating boom
Layer 101, between control grid layer 104 and Semiconductor substrate 100 by oxide layer 112 mutually isolated；Institute
State word line layer 111 both sides and form side wall 113；It is positioned at the Semiconductor substrate 100 below described source line layer 108
Interior source region 110；It is positioned at the drain region 114 of the Semiconductor substrate 100 of described side wall 109 both sides.
But, in the memory cell of the flash memory that prior art is formed, the size of source line layer 108 is difficult to control
System, causes the unstable properties of flash memory.
Memory cell of more flash memories and forming method thereof refer to Publication No. US 2005/0181563A1
U.S. patent documents.
Summary of the invention
The problem that the present invention solves is to provide the forming method of memory cell of a kind of flash memory, makes to be formed
The size composite design standard of source line layer, makes the memory cell stable performance of formed flash memory.
For solving the problems referred to above, the present invention provides the forming method of the memory cell of a kind of flash memory, including:
Thering is provided Semiconductor substrate, described semiconductor substrate surface has floating gate layer, has first in described floating gate layer
Opening, described first opening exposes the surface of Semiconductor substrate, described floating gate layer and Semiconductor substrate it
Between mutually isolated by insulating barrier, described floating gate layer surface has a control grid layer, described control grid layer and floating
Between gate layer by interlayer dielectric layer mutually isolated, described control grid layer surface has mask layer, described in cover
Having the second opening in film layer, described second opening and the first opening are through, and described second opening exposes
Go out control grid layer surface；Sidewall at described first opening forms the first side wall；At described second opening
Sidewall forms the second side wall, and described second side coping flushes with described mask layer surface；Use and select
Property epitaxial deposition process forms source line layer, the top of described source line layer in described first opening and the second opening
Portion is not higher than the surface of described mask layer.
Alternatively, the material of described source line layer is polysilicon, and height is 2000 angstroms ~ 3000 angstroms.
Alternatively, described selective epitaxial depositing operation is: deposition gases includes silicon source gas and carrier gas,
The flow of described silicon source gas be 1 standard milliliters per minute ~ 1000 standard milliliters are per minute, described carrier gas
Flow is 0.1 Standard Liters per Minute ~ 50 Standard Liters per Minute, and temperature is 500 ~ 800 degrees Celsius, and pressure is
1 torr ~ 100 torr, the time is 0.1 hour ~ 1 hour.
Alternatively, described silicon source gas is SiH4Or SiH2Cl2, described carrier gas is nitrogen or hydrogen.
Alternatively, also include: after the line layer of the source that formed, at described floating gate layer, control grid layer and mask
Layer both sides form word line layer, have between described word line layer and floating gate layer, control grid layer and Semiconductor substrate
Oxide layer is mutually isolated；The 3rd side wall is formed in described word line layer both sides.
Alternatively, the material of described word line layer is polysilicon, the material of described 3rd side wall be silica,
Silicon nitride or silicon nitride and silica multiple-layer overlapped.
Alternatively, ion note is carried out in described source line layer, the second side wall, mask layer and the 3rd side wall both sides
Enter, form drain region.
Alternatively, the material of described floating gate layer and control grid layer is polysilicon.
Alternatively, the material of described mask layer is silicon nitride
Alternatively, the material of described first side wall and the second side wall is silica.
Alternatively, the material of described insulating barrier is silica, described interlayer dielectric layer be silicon oxide-silicon nitride-
The laminated construction of silica.
Alternatively, described floating gate layer, control grid layer, mask layer, the first side wall and the formation of the second side wall
Method is: sequentially form insulation film, floating boom film, inter-level dielectric at described semiconductor substrate surface thin
Film, control gate film and mask film；Etched portions mask film also exposes control gate film surface,
Form the second opening and mask layer；Sidewall at described second opening forms the second side wall；With described second
Side wall and mask layer are mask, etch described control gate film, interlayer medium film, floating boom film and absolutely
Edge film also exposes semiconductor substrate surface, forms the first opening；Formed at described first opening sidewalls
First side wall.
Alternatively, before forming the first side wall, the Semiconductor substrate of described first open bottom is carried out
Ion implanting, forms source region.
Alternatively, the material of described Semiconductor substrate is silicon, SiGe, carborundum or silicon-on-insulator.
Compared with prior art, technical scheme has the advantage that
When using selective epitaxial depositing operation to form source line layer in described first opening and the second opening,
The Semiconductor substrate of described first open bottom is as Seed Layer, and upwards gives birth to from described first open bottom
Long source line layer, the height of the source line layer therefore formed can be by controlling described selective epitaxial deposition work
The parameter of skill and be controlled, it is possible to make the size composite design standard of formed source line layer；And,
Use described selective epitaxial process in same semiconductor substrate surface forms the memory cell of different flash memory
Source line layer time, consistent size between the line layer of each source, the resistance of the most described each source line layer is consistent, makes institute's shape
The stable performance of the flash memory become.
Further, after using described selective epitaxial depositing operation to form source line layer, due to described source line
The consistent size of layer, and meet design standard, it is possible to make subsequent technique in same semiconductor substrate surface institute
Consistent size between each complete memory cell formed, the stable performance of the flash memory therefore formed.
Accompanying drawing explanation
Fig. 1 is the structural representation of the memory cell of the flash memory of prior art；
Fig. 2 is the schematic flow sheet of the method for the memory cell of flash memory described in the embodiment of the present invention；
Fig. 3 to Fig. 7 is the cross-section structure of the forming process of the memory cell of flash memory described in the embodiment of the present invention
Schematic diagram.
Detailed description of the invention
As stated in the Background Art, in the memory cell of the flash memory that prior art is formed, the size of source line layer
It is difficult to control to, causes the unstable properties of flash memory.
Through the research discovery of inventor, owing to, in prior art, refer to Fig. 1, described source line layer 108
Forming method is: use chemical vapor deposition method or physical gas-phase deposition at described first opening and
In second opening and the line film of formation source, described mask layer 106 surface；Use chemically mechanical polishing work
Skill, removes the source line film higher than described mask layer 106 surface, forms source line layer 108；Described source line layer
The formation process of 108 is complicated, affects the manufacturing cycle of product.
And, prior art can be at the storage list forming some flash memories on same semi-conductive substrate 100 surface
Unit；When using CMP process that the source line film of different memory cell is planarized, by
Inconsistent for the grinding rate of whole Semiconductor substrate 100 in described CMP process, cause
The height of the source line layer 108 being positioned at Semiconductor substrate 100 surface diverse location after planarization is different, makes institute
The size stating source line layer 108 is difficult to control to, and is not inconsistent with design standard；Concrete, described chemical machinery
Glossing is relatively low at the grinding rate of the center and peripheral of described Semiconductor substrate 100, and other regions
Grinding rate higher, be therefore formed at the source line layer 108 of described Semiconductor substrate 100 center and peripheral
Higher, and the source line layer height in other regions is relatively low；Thus, make the size of formed source line layer 108
It is difficult to control to；Due to the difference between line layer 108 size of each source, in described each source line layer 108 can be caused
Resistance inconsistent, make formed flash memory performance unstable.
Additionally, when described source line film is planarized, can carry out a certain degree of overground, smooth
Change described mask layer 106；Owing to described CMP process is to whole Semiconductor substrate 100 surface
Grinding rate is inconsistent, mask layer 106 and source line layer 108 after causing planarizing between each memory cell
Height inconsistent, thus cause the size of each memory cell being ultimately formed inconsistent.
Further study show that through inventor, when using selective epitaxial depositing operation, and with described
The Semiconductor substrate of the first open bottom is as silicon seed layer, shape in described first opening and the second opening
During the source line layer become, the height of the source line layer formed can be entered by described selective epitaxial depositing operation
Row controls, and is formed and the source line floor height in the memory cell of the different flash memories of same semiconductor substrate surface
Degree is consistent；Therefore, the size of the source line layer formed is easily controlled, and not size between homology line layer
Unanimously, make formed flash memory performance stable.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.
Fig. 2 is the schematic flow sheet of the method for the memory cell of flash memory described in the embodiment of the present invention, including step
Rapid:
Step S101, sequentially forms insulation film, floating boom film, interlayer at described semiconductor substrate surface
Dielectric film, control gate film and mask film；
Step S102, removes part mask film and exposes control gate film surface, forming the second opening
And mask layer；Sidewall at described second opening forms the second side wall；
Step S103, with described second side wall and mask layer as mask, removes described control gate film, layer
Between dielectric film, floating boom film and insulation film expose semiconductor substrate surface, form the first opening；
The first side wall is formed at described first opening sidewalls；
Step S104, uses selective epitaxial depositing operation to be formed in described first opening and the second opening
Source line layer, the top of described source line layer is not higher than the surface of described mask layer；
Step S105, after the line layer of the source that formed, in described floating gate layer, control grid layer and mask layer both sides
Form word line layer, between described word line layer and floating gate layer, control grid layer and Semiconductor substrate, pass through oxide layer
Mutually isolated；The 3rd side wall is formed in described word line layer both sides.
Below with reference to accompanying drawing, the forming method of the memory cell of flash memory described in the embodiment of the present invention is said
Bright, Fig. 3 to Fig. 7 is the cross-section structure of the forming process of the memory cell of flash memory described in the embodiment of the present invention
Schematic diagram.
Refer to Fig. 3, sequentially form insulation film 201, floating boom on described Semiconductor substrate 200 surface thin
Film 202, interlayer medium film 203, control gate film 204 and mask film 205.
Described Semiconductor substrate 200 is for providing workbench, described Semiconductor substrate 200 for subsequent technique
Material be monocrystalline silicon, SiGe, carborundum or silicon-on-insulator；Owing to forming source line layer at subsequent technique
Time, use selective epitaxial depositing operation using the silicon on described Semiconductor substrate 200 surface as Seed Layer,
Growing single-crystal silicon in described first opening and the second opening, in order to form highly controllable source line layer, because of
The material of this described Semiconductor substrate 200 need to comprise silicon atom；In the present embodiment, described semiconductor lining
The end 200, through p-type ion implanting, forms p-type well region, the source region being subsequently formed and the conductive-type in drain region
Type is N-shaped；In other embodiments, described Semiconductor substrate 200, through N-shaped ion implanting, forms n
Type well region, the source region being subsequently formed and the conduction type in drain region are p-type.
The material of described insulation film 201 is silica, and formation process is chemical vapor deposition method, thing
Physical vapor deposition technique or thermal oxidation technology, described insulation film 201 is for isolation of semiconductor substrate 200
With floating boom film 202；The material of described floating boom film 202 and control gate film 204 is polysilicon, described
Interlayer medium film 203 is the laminated construction of oxide-nitride-oxide；Described mask film 205
Material is silicon nitride, and the thickness of described mask film 205 is 1500 angstroms ~ 3000 angstroms；Described floating boom film
202, the formation process of interlayer medium film 203, control gate film 204 and mask film 205 is chemistry
Gas-phase deposition or physical gas-phase deposition；Described floating boom film 202 and control gate film 204 are used
In forming floating gate layer and control grid layer in subsequent technique.
The thickness of described mask film 205 determines the height of the source line layer being subsequently formed, and flash memory
The size of memory cell, and described mask film 205 uses chemical vapor deposition method or physical vapor to sink
Long-pending technique is formed, and the thickness of the most described mask film 205 is controlled, so the storage of the flash memory formed
The size of unit is controlled.
Refer to Fig. 4, remove part mask film 205(such as Fig. 3) and expose control gate film 204
Surface, forms the second opening 206 and mask layer 205a；Sidewall at described second opening 206 forms the
Two side walls 207.
The formation process of described second opening 206 is: form photoresist on described mask film 205 surface
Layer, described photoresist layer exposes the position needing to form the second opening 206；With described photoresist layer it is
Mask film 205 described in mask, dry etching or wet etching, exposes described control gate film 204 table
Face, forms mask layer 205a；Formed mask layer 205a determines the size of floating gate layer and control grid layer,
And the thickness of described mask layer 205a determines the height of the source line layer being subsequently formed, and described mask layer
205a thickness accurately can be controlled by depositing operation.
The material of described second side wall 207 is silica, and the formation process of described second side wall 207 is:
Use the good physical gas-phase deposition of chemical vapor deposition method at described mask layer 205a surface, Yi Ji
Second side wall film is formed on the sidewall of two openings 206 and bottom；Employing is etched back to technique etching described second
Side wall film, removes the second side wall film bottom described mask layer 205a and the second opening 206, shape
Become the second side wall 207；Described second side wall 207 is in order to isolate described control gate film 204 and to be subsequently formed
Source line layer.
Refer to Fig. 5, with described second side wall 207 and mask layer 205a as mask, remove described control
Grid film 204, interlayer medium film 203, floating boom film 202 and insulation film 201 exposing partly is led
Body substrate 200 surface, forms the first opening 208, and control grid layer 204a, interlayer dielectric layer 203a,
Floating gate layer 202a and insulating barrier 201a；The first side wall 209 is formed at described first opening 208 sidewall.
The formation process of described first opening 208 is dry etching or wet etching；In the present embodiment,
While forming described first opening 208, remove with described mask layer 205a for mask and need to form storage
Control gate film 204, interlayer medium film 203, floating boom film 202 beyond cell position and insulate thin
Film 201；The first opening 208 formed is through with the second opening 206, described first opening 208 and
It is used for forming source line layer in subsequent technique in two openings 206.
After forming the first opening 208, to the Semiconductor substrate 200 bottom described first opening 208
Carry out ion implanting, form source region；In the present embodiment, described source region is N-shaped；In other embodiments
In, when described well region is N-shaped, described source region is p-type.
Being formed after source region, the sidewall at described first opening 208 forms the first side wall 209, and described first
The material of side wall 209 is silica, the formation process of described first side wall 209 and the second side wall 207 phase
With, therefore not to repeat here.
Refer to Fig. 6, use selective epitaxial depositing operation at described first opening 208(such as Fig. 5) and
Second opening 206(such as Fig. 6) interior formation source line layer 210, the top of described source line layer 210 is not higher than institute
State the surface of mask layer 205a.
The material of described source line layer 210 is polysilicon；The height of described source line layer 210 is by mask layer 205a
Thickness determine, the height of described source line layer 210 is 2000 angstroms ~ 3000 angstroms；Described selective epitaxial sinks
Long-pending technique is: deposition gases includes that silicon source gas and carrier gas, the flow of described silicon source gas are 1 standard milli
Liter Per Minute ~ 1000 standard milliliters is per minute, and the flow of described carrier gas is 0.1 Standard Liters per Minute ~ 50 mark
Quasi-Liter Per Minute, temperature is 500 ~ 800 degrees Celsius, and pressure is 1 torr ~ 100 torr, and the time is 0.1 hour
~ 1 hour；Wherein, described silicon source gas includes SiH4、SiH2Cl2In one or both, described carrier gas
Including one or both in nitrogen, hydrogen.
Semiconductor lining in described selective epitaxial deposition process, bottom described first opening 206
Surface, the end 200 as the Seed Layer of growing single-crystal silicon, by bottom described first opening 206 the most upward
Formed and fill full described first opening 208 and the source line layer 210 of the second opening 206；Therefore, formed
The height of source line layer 210 accurately can be controlled by described selective epitaxial depositing operation；And,
Source line layer 210 in the memory cell of the flash memory being formed at same semi-conductive substrate 200 surface diverse location
Highly consistent, make the resistance of the source line layer 210 of each memory cell formed identical, formed is each
During memory cell work, operating current is stable, thus the memory cell stable performance of the flash memory formed；
Additionally, selecting property epitaxial deposition process described in Cai Yonging forms source line layer 210 technique simply, and can saving
Learn the processing step of mechanical polishing, so that the technique forming the memory cell of flash memory simplifies, cost reduces,
And output capacity is high.
Secondly as the height of described source line layer 210 can accurately control, therefore, subsequent technique is with institute
The height stating source line layer 210 is reference, and the wordline formed and the size of the 3rd side wall also are able to be able to
Control, and enable wordline and the 3rd side wall to meet pre-set dimension, thus each memory cell formed
Consistent size, and meet design standard, be suitable to integrated.
Refer to Fig. 7, after the source that formed line layer 210, at described floating gate layer 202a, control grid layer 204a
Word line layer 211, described word line layer 211 and floating gate layer 202a, control gate is formed with mask layer 205a both sides
Oxide layer 212 is passed through mutually isolated between layer 204a and Semiconductor substrate 200；At described word line layer 211
Both sides form the 3rd side wall 213.
The material of described word line layer 211 is polysilicon, described word line layer 211 and the formation of oxide layer 212
Technique is: use depositing operation, it is preferred that chemical vapor deposition method described Semiconductor substrate 200,
Floating gate layer 202a, control grid layer 204a, mask layer 205a and Xian Ceng210 surface, source form silicon oxide film
With word line layer film；Use and be etched back to the technique described mask layer 205a of removal and the oxygen on Xian Ceng210 surface, source
SiClx film and word line layer film, at described floating gate layer 202a, control grid layer 204a and mask layer 205a
Both sides form silicon oxide layer 212 and word line layer 211；Therefore, the size of described word line layer 211 is by described source
The height of line layer 210 determines, and the height of described source line layer 210 can sink by adjusting selective epitaxial
Long-pending technique accurately controls, and makes the size of described word line layer 211 be easily controlled.
Described 3rd side wall 213 is made up of the individual layer of silica or silicon nitride, or by silicon nitride and silica
Multiple-layer overlapped is constituted；The formation process of described 3rd side wall 213 and described first side wall 209 and the second side
The formation process of wall 207 is identical, does not repeats them here.
In the present embodiment, after forming described 3rd side wall 213, with described 3rd side wall 213, wordline
Layer 211, mask layer 205a and source line layer 210 are mask, carry out in described 3rd side wall 213 both sides from
Son injects, and forms drain region；In the present embodiment, described drain region is N-shaped；When in Semiconductor substrate 200
When well region is N-shaped, described drain region is p-type.
In other embodiments, formed before described 3rd side wall layer 213, with described word line layer 211,
Mask layer 205a and source line layer 210 are mask, carry out in described word line layer 211 both sides ion note is lightly doped
Enter；After forming the 3rd side wall 213, carry out heavy doping ion note in described 3rd side wall 213 both sides
Enter, form drain region.
In the present embodiment, use the source line layer of the memory cell of selective epitaxial depositing operation formation flash memory
210, enable the height of described source line layer 210 by the described selective epitaxial deposition process parameters of regulation
Accurately control, and be positioned at the source line layer of the memory cell of same semi-conductive substrate 200 surface diverse location
210 highly consistent, so that the stable performance of the flash memory formed；Additionally, due to each source line layer 210
Highly consistent, be with reference to the word line layer 211 formed and the 3rd side wall with the height of described source line layer 210
The size of 213 also keeps consistent, so that the size uniformity of each memory cell formed, is suitable to integrated.
In sum, selective epitaxial depositing operation is used to be formed in described first opening and the second opening
During the line layer of source, the Semiconductor substrate of described first open bottom is as Seed Layer, and from described first opening
Bottom up growth source line layer, the height of the source line layer therefore formed can be by controlling described selectivity
The parameter of epitaxial deposition process and be controlled, it is possible to make that the size of formed source line layer is compound relates to mark
Accurate；And, use described selective epitaxial process to form different flash memory at same semiconductor substrate surface
During source line layer in memory cell, consistent size between the line layer of each source, the resistance one of the most described each source line layer
Cause, make the stable performance of formed flash memory.
Further, after using described selective epitaxial depositing operation to form source line layer, due to described source line
The consistent size of layer, and meet design standard, it is possible to make subsequent technique in same semiconductor substrate surface institute
Consistent size between each complete memory cell formed, the stable performance of the flash memory therefore formed.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, appoints
What those skilled in the art without departing from the spirit and scope of the present invention, may be by the disclosure above
Technical solution of the present invention is made possible variation and amendment by method and technology contents, therefore, every does not takes off
From the content of technical solution of the present invention, it is any that above example is made by the technical spirit of the foundation present invention
Simple modification, equivalent variations and modification, belong to the protection domain of technical solution of the present invention.
Claims (14)
1. the forming method of the memory cell of a flash memory, it is characterised in that including:
Thering is provided Semiconductor substrate, described semiconductor substrate surface has floating gate layer, has in described floating gate layer
First opening, described first opening exposes the surface of Semiconductor substrate, and described floating gate layer serves as a contrast with semiconductor
Passing through insulating barrier mutually isolated, described floating gate layer surface has control grid layer, described control grid layer at the end
And mutually isolated by interlayer dielectric layer between floating gate layer, described control grid layer surface has mask layer, institute
Having the second opening in stating mask layer, described second opening and the first opening are through, and described second opening
Expose control grid layer surface；
Sidewall at described first opening forms the first side wall；
Sidewall at described second opening forms the second side wall, described second side coping and described mask
Layer surface flushes；
Selective epitaxial depositing operation is used to form source line layer, institute in described first opening and the second opening
State the Semiconductor substrate of the first open bottom as Seed Layer, and grow up from described first open bottom
Source line layer, the top of described source line layer is not higher than the surface of described mask layer.
2. the forming method of the memory cell of flash memory as claimed in claim 1, it is characterised in that described source line layer
Material be polysilicon, height be 2000 angstroms～3000 angstroms.
3. the forming method of the memory cell of flash memory as claimed in claim 2, it is characterised in that described selectivity
Epitaxial deposition process is: deposition gases includes that silicon source gas and carrier gas, the flow of described silicon source gas are
1 standard milliliters is per minute～1000 standard milliliters are per minute, and the flow of described carrier gas is that 0.1 standard rises often
Minute～50 Standard Liters per Minute, temperature is 500～800 degrees Celsius, and pressure is 1 torr～100 torr, time
Between be 0.1 hour～1 hour.
4. the forming method of the memory cell of flash memory as claimed in claim 3, it is characterised in that described silicon source gas
Body is SiH4Or SiH2Cl2, described carrier gas is nitrogen or hydrogen.
5. the forming method of the memory cell of flash memory as claimed in claim 1, it is characterised in that also include:
After the line layer of formation source, form word line layer, institute in described floating gate layer, control grid layer and mask layer both sides
State that to have oxide layer between word line layer and floating gate layer, control grid layer and Semiconductor substrate mutually isolated；?
Described word line layer both sides form the 3rd side wall.
6. the forming method of the memory cell of flash memory as claimed in claim 5, it is characterised in that described word line layer
Material be polysilicon, the material of described 3rd side wall is silica, silicon nitride or silicon nitride and oxygen
SiClx multiple-layer overlapped.
7. the forming method of the memory cell of flash memory as claimed in claim 5, it is characterised in that at described source line
Layer, the second side wall, mask layer, word line layer and the 3rd side wall both sides carry out ion implanting, form drain region.
8. the forming method of the memory cell of flash memory as claimed in claim 1, it is characterised in that described floating gate layer
It is polysilicon with the material of control grid layer.
9. the forming method of the memory cell of flash memory as claimed in claim 1, it is characterised in that described mask layer
Material be silicon nitride.
10. the forming method of the memory cell of flash memory as claimed in claim 1, it is characterised in that described first side
The material of wall and the second side wall is silica.
The forming method of the memory cell of 11. flash memories as claimed in claim 1, it is characterised in that described insulating barrier
Material be silica, described interlayer dielectric layer is the laminated construction of oxide-nitride-oxide.
The forming method of the memory cell of 12. flash memories as claimed in claim 1, it is characterised in that described floating gate layer,
The forming method of control grid layer, mask layer, the first side wall and the second side wall is: serve as a contrast at described semiconductor
Basal surface sequentially forms insulation film, floating boom film, interlayer medium film, control gate film and mask
Film；Etched portions mask film also exposes control gate film surface, forms the second opening and mask
Layer；Sidewall at described second opening forms the second side wall；With described second side wall and mask layer for covering
Film, etches described control gate film, interlayer medium film, floating boom film and insulation film and exposes
Semiconductor substrate surface, forms the first opening；The first side wall is formed at described first opening sidewalls.
The forming method of the memory cell of 13. flash memories as claimed in claim 12, it is characterised in that forming first
Before side wall, the Semiconductor substrate of described first open bottom is carried out ion implanting, forms source region.
The forming method of the memory cell of 14. flash memories as claimed in claim 1, it is characterised in that described semiconductor
The material of substrate is silicon, SiGe, carborundum or silicon-on-insulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210301659.1A CN102800679B (en) | 2012-08-22 | 2012-08-22 | The forming method of the memory cell of flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210301659.1A CN102800679B (en) | 2012-08-22 | 2012-08-22 | The forming method of the memory cell of flash memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102800679A CN102800679A (en) | 2012-11-28 |
| CN102800679B true CN102800679B (en) | 2016-08-17 |
Family
ID=47199740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210301659.1A Active CN102800679B (en) | 2012-08-22 | 2012-08-22 | The forming method of the memory cell of flash memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102800679B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103346127B (en) * | 2013-06-28 | 2017-09-29 | 上海华虹宏力半导体制造有限公司 | Flash memory device structure and preparation method |
| CN104465664A (en) * | 2014-12-30 | 2015-03-25 | 上海华虹宏力半导体制造有限公司 | Split-gate flash memory and manufacturing method thereof |
| CN106206453B (en) * | 2016-08-30 | 2019-05-14 | 上海华虹宏力半导体制造有限公司 | The forming method of memory |
| CN106298790B (en) * | 2016-09-18 | 2018-11-27 | 上海华虹宏力半导体制造有限公司 | The forming method of flash memory |
| CN107230678B (en) * | 2017-08-09 | 2020-04-10 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory |
| CN111613618A (en) * | 2020-05-26 | 2020-09-01 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN112838008B (en) * | 2021-01-08 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | Process method of floating gate split gate flash memory device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101155648A (en) * | 2005-01-31 | 2008-04-02 | 应用材料公司 | Low temperature etchant for treatment of silicon-containing surfaces |
| CN102315252A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Flash memory unit for shared source line and forming method thereof |
| CN102637696A (en) * | 2012-04-25 | 2012-08-15 | 上海宏力半导体制造有限公司 | Memory cell of flash memory, and formation method thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005191489A (en) * | 2003-12-26 | 2005-07-14 | Sharp Corp | Semiconductor memory and manufacturing method for the same |
| KR100703984B1 (en) * | 2006-03-22 | 2007-04-09 | 삼성전자주식회사 | Fabrication method of semiconductor integrated circuit device and resultant structure |
-
2012
- 2012-08-22 CN CN201210301659.1A patent/CN102800679B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101155648A (en) * | 2005-01-31 | 2008-04-02 | 应用材料公司 | Low temperature etchant for treatment of silicon-containing surfaces |
| CN102315252A (en) * | 2011-09-28 | 2012-01-11 | 上海宏力半导体制造有限公司 | Flash memory unit for shared source line and forming method thereof |
| CN102637696A (en) * | 2012-04-25 | 2012-08-15 | 上海宏力半导体制造有限公司 | Memory cell of flash memory, and formation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102800679A (en) | 2012-11-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102800679B (en) | The forming method of the memory cell of flash memory | |
| TWI647857B (en) | Integrated circuits with programmable memory and methods for producing the same | |
| CN105097704B (en) | Flush memory device and forming method thereof | |
| CN104051535B (en) | Transistor containing the gate electrode for extending around one or more channel regions | |
| CN103426826B (en) | Flash cell and forming method thereof | |
| US20170110464A1 (en) | Ultrathin semiconductor channel three-dimensional memory devices | |
| CN104124210B (en) | The forming method of semiconductor structure | |
| WO2017058299A1 (en) | Epitaxial source region for uniform threshold voltage of vertical transistors in 3d memory devices | |
| US20130341701A1 (en) | Vertical Semiconductor Memory Device and Manufacturing Method Thereof | |
| US9583499B1 (en) | Devices with embedded non-volatile memory and metal gates and methods for fabricating the same | |
| CN104103516B (en) | Fleet plough groove isolation structure and forming method thereof | |
| CN103579126A (en) | Semi-floating gate component of U-shaped structure and manufacturing method thereof | |
| CN106206598B (en) | Gate-division type flash memory device making method | |
| TWI743784B (en) | Processes for forming 3-dimensional horizontal nor memory arrays | |
| CN111627918A (en) | 3D NAND memory and manufacturing method thereof | |
| KR102423884B1 (en) | Silicon precursor, method of forming a layer using the same and method of fabricating a semiconductor device using the same | |
| US9240482B2 (en) | Asymmetric stressor DRAM | |
| CN110349967B (en) | Three-dimensional memory and forming method thereof | |
| US8643123B2 (en) | Method of making a semiconductor structure useful in making a split gate non-volatile memory cell | |
| CN104681494A (en) | Semiconductor memory device and preparation method thereof | |
| CN103855098B (en) | Method for forming storage unit of flash memory | |
| US7084043B2 (en) | Method for forming an SOI substrate, vertical transistor and memory cell with vertical transistor | |
| CN111710713B (en) | Fin type field effect transistor, manufacturing method thereof and electronic equipment | |
| CN110880472A (en) | Semiconductor device with shallow trench isolation structure and preparation method thereof | |
| CN102637647B (en) | The forming method of the memory cell of flash memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140410 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140410 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: Zuchongzhi road in Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 1399 201203 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |