CN107230678B - Method for manufacturing flash memory - Google Patents
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- CN107230678B CN107230678B CN201710677510.6A CN201710677510A CN107230678B CN 107230678 B CN107230678 B CN 107230678B CN 201710677510 A CN201710677510 A CN 201710677510A CN 107230678 B CN107230678 B CN 107230678B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 36
- 238000005530 etching Methods 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000003647 oxidation Effects 0.000 claims abstract description 7
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 13
- 239000002253 acid Substances 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 9
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 4
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 4
- 239000008367 deionised water Substances 0.000 claims description 4
- 229910021641 deionized water Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 2
- 230000007797 corrosion Effects 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 7
- 238000002161 passivation Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 239000002131 composite material Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacturing method of a flash memory, which comprises the steps of sequentially forming a floating gate oxide layer, a floating gate layer, a control gate layer and a dielectric layer on a substrate, etching the dielectric layer to expose the control gate layer, forming a first side wall on the side wall of an opening generated by etching, etching the control gate layer at the bottom of the opening by taking the first side wall as a mask, reducing the thickness of the first side wall, enabling the first side wall to retreat to expose the tip of the control gate layer generated by etching, carrying out oxidation treatment on the tip of the control gate layer to enable the passivation to be round and smooth, avoiding the problems that a high electric field is formed between a word wire grid and a control gate and the tip of the control gate discharges to break down a device when data is erased, and improving the reliability and the stability of the device.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a flash memory.
Background
Flash memory (Flash) is a non-volatile memory, i.e. power-off data can not be lost, and has the advantages of high integration level, high access speed, good reliability, easy erasing and rewriting and the like, so that the Flash memory is widely applied to mobile communication equipment such as mobile phones, notebooks, personal computers and the like.
In the existing manufacturing method of the flash memory, a floating gate oxide layer, a floating gate layer, an isolation layer, a control gate layer and a dielectric layer are generally formed on a semiconductor substrate in sequence, then a dry etching method is adopted to remove a local dielectric layer, an opening is formed to expose the control gate layer, in order to ensure that no polysilicon remains after etching, enough etching time is generally required to be kept, over-etching of the control gate layer is formed, and therefore the control gate layer has a bent profile, and the tip of the control gate layer between a word line grid and a control gate is formed. In erasing data, a higher positive voltage is typically required on the word line gate, a lower negative voltage is applied on the control gate, and a high electric field is eventually formed between the word line gate and the control gate, with the potential risk of device breakdown.
Disclosure of Invention
The invention aims to provide a manufacturing method of a flash memory, which aims to solve the problems that in the prior art, the tip of a control grid layer is generated due to over-etching of the control grid layer, and when data is erased, a high electric field is formed between a word line grid and a control grid, so that a device is easy to break down.
In order to achieve the above object, the present invention provides a method for manufacturing a flash memory, comprising:
providing a substrate, wherein a floating gate oxide layer, a floating gate layer, a control gate layer and a dielectric layer are sequentially formed on the substrate;
etching the dielectric layer to form an opening to expose the control gate layer;
forming a first side wall on the side wall of the opening;
etching the control gate layer in the opening, wherein a control gate layer tip is formed due to over-etching in the step, and a control gate layer tip is formed;
transversely thinning the first side wall to expose the tip of the control gate layer;
carrying out oxidation treatment on the tip of the control gate layer;
optionally, the step of laterally thinning the first sidewall to expose the tip of the control gate layer includes:
thinning the first side wall by adopting an acid liquor corrosion method;
cleaning by adopting a first standard cleaning solution;
optionally, the acid solution contains diluted hydrofluoric acid;
optionally, the first standard cleaning solution comprises hydrogen peroxide, ammonia water and deionized water;
optionally, the time for etching by using the acid liquor is 100s-5 min;
optionally, the temperature for performing oxidation treatment on the tip of the control gate layer is 700-1000 ℃;
optionally, the time for performing oxidation treatment on the tip of the control gate layer is 5s-120 s;
optionally, the step of forming a first sidewall on the sidewall of the opening includes:
forming a silicon oxide layer on the dielectric layer and the inner wall of the opening;
etching to remove the silicon oxide layer on the dielectric layer and the bottom wall of the opening to form the first side wall;
optionally, the thickness of the silicon oxide layer is 1000 angstroms to 1500 angstroms;
optionally, after the oxidizing treatment is performed on the tip of the control gate layer, the method for manufacturing the floating gate further includes:
forming a second side wall on the side wall of the control gate layer in the opening;
etching the floating gate layer by taking the second side wall as a mask;
forming a tunnel oxide layer and a word line polysilicon layer;
optionally, an isolation layer is formed between the floating gate layer and the control gate layer;
optionally, the material of the dielectric layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride;
optionally, the dielectric layer is etched by a dry etching process.
The invention provides a method for manufacturing a flash memory, which comprises the steps of sequentially forming a floating gate oxide layer, a floating gate layer, a control gate layer and a dielectric layer on a substrate, etching the dielectric layer to expose the control gate layer, forming a first side wall on the side wall of an opening generated by etching, etching the control gate layer on the bottom wall of the opening by taking the first side wall as a mask, in order to prevent the control gate from remaining after the control gate is etched, the control gate is generally over-etched, the over-etching of the control gate layer can cause the generation of the tip of the control gate layer, the thickness of the first side wall is transversely thinned, so that the first side wall is retracted to expose the tip of the control gate layer, the tip of the control gate layer is oxidized to ensure that the passivation of the tip becomes smooth, so that the phenomenon that when data is erased, high electric field is formed between the word line grid and the control grid, and the point discharge of the control grid layer breaks down the device.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a flash memory according to an embodiment;
FIGS. 2-7 are cross-sectional views of semiconductor structures formed using the flash memory fabrication method;
the method comprises the following steps of 1-a substrate, 2-a floating gate oxide layer, 3-a floating gate layer, 4-a control gate layer, 41-a tip of the control gate layer, 5-a dielectric layer, 6-an opening, 61-a first side wall, 62-a second side wall and 7-an isolation layer.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, a flow chart of a method for manufacturing a flash memory according to an embodiment is shown. As shown in fig. 1, the method for manufacturing the flash memory includes:
s1: providing a substrate, wherein a floating gate oxide layer, a floating gate layer, a control gate layer and a dielectric layer are sequentially formed on the substrate;
s2: etching the dielectric layer to expose the control gate layer and form an opening;
s3: forming a first side wall on the side wall of the opening;
s4: etching the control gate layer in the opening to form a tip of the control gate layer;
s5: transversely thinning the first side wall to expose the tip of the control gate layer;
s6: and carrying out oxidation treatment on the tip of the control gate layer.
When the control grid layer in the opening is etched, the control grid layer is usually required to be over-etched, so that the control grid layer has a bent outline, the tip of the control grid layer is formed, the first side wall on the side wall of the opening is transversely thinned to expose the tip of the control grid layer, the tip of the control grid layer is oxidized, the passivation of the control grid layer is made to be round, and the problem that when data are erased, a high electric field is formed between the word line grid and the control grid, and the tip of the control grid layer discharges to break down a device is solved.
Specifically, please refer to fig. 2 to 7, which are schematic cross-sectional views of a semiconductor structure formed by the flash memory manufacturing method. Next, a method for manufacturing the flash memory will be further described with reference to fig. 2 to 7.
First, referring to fig. 2, a substrate 1 is provided, and a floating gate oxide layer 2, a floating gate layer 3, a control gate layer 4 and a dielectric layer 5 are sequentially formed on the substrate 1. The material of the substrate 1 is preferably silicon, and may be germanium, silicon germanium, gallium arsenide, silicon on insulator, or the like. The substrate in this embodiment is a silicon substrate, and an active region is formed by an ion implantation process. The floating gate oxide layer 2, the floating gate layer 3, the control gate layer 4 and the dielectric layer 5 are sequentially formed, the material of the floating gate oxide layer 2 is preferably silicon dioxide and is used for isolating the substrate 1 from the floating gate layer 3, and the floating gate layer 3 and the control gate layer 4 are used for forming a floating gate and a control gate in a subsequent process. The floating gate layer 3 and the control gate layer 4 can be made of polysilicon; the dielectric layer 5 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric, and ultra-low-K dielectric.
It should be noted that in the embodiment of the present application, an isolation layer is further included between the floating gate layer 3 and the control gate layer 4. Specifically, referring to fig. 3, an isolation layer 7 is included between the floating gate layer 3 and the control gate layer 4 for isolating the floating gate from the control gate, and the isolation layer 7 may be a composite structure layer of oxide-nitride-oxide (ONO).
Continuing with fig. 2, the dielectric layer 5 is dry etched to expose the control gate layer 4 (a portion of the control gate layer 4 may be etched) to form an opening 6.
And then, forming a first side wall 61 on the side wall of the opening 6, preferably, depositing a silicon oxide layer with a certain thickness on the inner wall of the opening 6 and the dielectric layer 5 by using a low-pressure vapor deposition method, preferably, performing rapid annealing after deposition to enhance the step coverage and compactness of the side wall, and finally etching the silicon oxide layer on the bottom wall of the opening 6 and the dielectric layer 5 to form the first side wall 61. Preferably, the thickness of the silicon oxide layer is between 1000 angstroms and 1500 angstroms, for example, the thickness of the silicon oxide layer is 1300 angstroms, 1350 angstroms and 1400 angstroms, and in this embodiment, the thickness of the silicon oxide layer is 1400 angstroms.
With continued reference to fig. 4 and 5, the control gate layer 4 in the opening 6 may be etched by anisotropic etching, and due to over-etching of the control gate layer 4 (to prevent the control gate from remaining after the control gate etching, the control gate is typically over-etched), the control gate layer 4 may cause the formation of a control gate tip 41 after etching.
Continuing to refer to fig. 5, the first sidewall 61 is thinned to expose the tip 41 of the control gate layer. Preferably, the first sidewall 61 is etched to a reduced thickness by wet chemical etching. Preferably, the first side wall 61 is subjected to acid etching using diluted hydrofluoric acid (HF) for 100s to 5min, for example, 100s, 2min, 3min, 4min and 5min, and in this embodiment, the first side wall 61 is subjected to acid etching using diluted hydrofluoric acid (water: hydrofluoric acid: 100:1) for 2 min. Of course, those skilled in the art should appreciate that the acid solution has a high selectivity for the first sidewall 61, and can etch the first sidewall 61 without affecting other layers, not just hydrofluoric acid.
In order to reduce the influence of impurities, after the first side wall 61 is corroded by the acid solution, preferably, a first standard cleaning solution can be used for cleaning, and the first standard cleaning solution is a combination of hydrogen peroxide, ammonia water and deionized water, wherein the ammonia water: hydrogen peroxide: the volume ratio of the deionized water is 1:2: 40.
After the first side wall 61 is thinned, the tip 41 of the control gate layer is exposed, and then the tip 41 of the control gate layer is oxidized to be passivated, so that the shape becomes round and smooth, as shown in fig. 6. Preferably, the device is placed into a rapid thermal processing device for oxidation, the time for oxidizing the tip 41 of the control gate layer is 5s-120s, for example, 20s, 50s, 70s and 100s, and the time for oxidizing the tip 41 of the control gate layer is 100s in this embodiment; the temperature for oxidizing the tip 41 of the control gate layer is 700 degrees to 1000 degrees, such as 800 degrees, 850 degrees, 900 degrees, and 1000 degrees, and the temperature for oxidizing the tip 41 of the control gate layer in this embodiment is 850 degrees. The tip 41 of the oxidized control grid layer becomes round, so that the problem that the device is broken down due to discharge of the tip of the control grid caused by high electric field formed between the word grid and the control grid when data is erased is avoided.
Further, referring to fig. 7, a second sidewall 62 is formed on the sidewall of the control gate layer in the opening 6, and the material and the forming method of the second sidewall 62 are the same as those of the first sidewall 61, except the thickness is different. Next, the floating gate layer 3 is etched by using the second sidewalls 62 as a mask, and then a tunnel oxide layer and a word line polysilicon layer are formed.
In summary, in the method for manufacturing a flash memory according to the embodiment of the present invention, a floating gate oxide layer, a floating gate layer, a control gate layer, and a dielectric layer are sequentially formed on a substrate, the dielectric layer is etched to expose the control gate layer, a first sidewall is formed on a sidewall of an opening generated by etching, the control gate layer on a bottom wall of the opening is etched using the first sidewall as a mask, a thickness of the first sidewall is laterally reduced to make the first sidewall recede to expose a tip of the control gate layer, and the tip of the control gate layer is oxidized to passivate the control gate layer to be smooth, so that a problem that a high electric field is formed between a word line and a control gate when data is erased and the tip of the floating gate layer discharges to break down a device is avoided.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (13)
1. A method for manufacturing a flash memory, the method comprising:
providing a substrate, wherein a floating gate oxide layer, a floating gate layer, a control gate layer and a dielectric layer are sequentially formed on the substrate;
etching the dielectric layer to form an opening to expose the control gate layer;
forming a first side wall on the side wall of the opening;
etching the control gate layer in the opening to form a tip of the control gate layer;
transversely thinning the first side wall to expose the tip of the control gate layer;
and carrying out oxidation treatment on the tip of the control gate layer.
2. The method of claim 1, wherein laterally thinning the first sidewall spacers to expose the tips of the control gate layer comprises:
thinning the first side wall by adopting an acid liquor corrosion method;
and cleaning by adopting a first standard cleaning solution.
3. The method of claim 2, wherein the acid solution contains diluted hydrofluoric acid.
4. The method according to claim 2, wherein the first standard cleaning solution comprises hydrogen peroxide, ammonia water and deionized water.
5. The method of claim 2, wherein the etching with the acid solution is performed for 100s-5 min.
6. The method of claim 1, wherein the temperature for oxidizing the tip of the control gate layer is 700-1000 degrees.
7. The method of claim 6, wherein the time for oxidizing the tip of the control gate layer is 5s to 120 s.
8. The method of claim 1, wherein the step of forming a first sidewall on the sidewall of the opening comprises:
forming a silicon oxide layer on the dielectric layer and the inner wall of the opening;
and etching to remove the silicon oxide layer on the dielectric layer and the bottom wall of the opening so as to form the first side wall.
9. The method of claim 8, wherein the silicon oxide layer has a thickness of 1000 a to 1500 a.
10. The method of manufacturing a flash memory of claim 1, wherein after the oxidizing process is performed on the tip of the control gate layer, the method further comprises:
forming a second side wall on the side wall of the control gate layer in the opening;
etching the floating gate layer by taking the second side wall as a mask;
and forming a tunnel oxide layer and a word line polysilicon layer.
11. The method of claim 1, wherein an isolation layer is formed between the floating gate layer and the control gate layer.
12. The method of claim 1, wherein the dielectric layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride.
13. The method of claim 1, wherein the dielectric layer is etched using a dry etching process.
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CN110429035A (en) * | 2019-09-06 | 2019-11-08 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of flash memory and flash memory |
CN111613618A (en) * | 2020-05-26 | 2020-09-01 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
CN112164655B (en) * | 2020-09-29 | 2024-03-15 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory device |
CN112908859B (en) * | 2021-03-24 | 2024-04-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memory |
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