CN107437547B

CN107437547B - Manufacturing method of semiconductor device

Info

Publication number: CN107437547B
Application number: CN201610356716.4A
Authority: CN
Inventors: 李敏
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-05-26
Filing date: 2016-05-26
Publication date: 2020-03-10
Anticipated expiration: 2036-05-26
Also published as: CN107437547A

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, and forming a plurality of floating gates arranged at intervals and a hard mask layer positioned on the floating gates on the semiconductor substrate; forming a side wall on the side walls of the floating gate and the hard mask layer, wherein the side wall is made of amorphous carbon; forming a shallow trench isolation structure in the semiconductor substrate between the adjacent floating gates; and removing the hard mask layer and the side wall to expose the floating gate. According to the manufacturing method, the side walls of the floating gate and the tunneling oxide layer are protected by the amorphous carbon side walls, so that the side walls are prevented from being corroded and damaged in the etching process, and the ashing removal method of the amorphous carbon can not damage the oxide, so that the performance and the reliability of the device can be improved by the manufacturing method.

Description

Manufacturing method of semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.

Background

In the current semiconductor industry, integrated circuit products can be divided into three major categories: logic, memory, and analog circuits, where memory devices represent a significant proportion of the products of integrated circuits. Among the memory devices, flash memory (flash memory) has been developed particularly rapidly in recent years. The method is mainly characterized in that the stored information can be kept for a long time under the condition of no power-on, and the method has the advantages of high integration level, higher access speed, easy erasing and rewriting and the like, thereby being widely applied to fields of microcomputer, automatic control and the like.

As the integration density of integrated circuits continues to increase, flash cells are scaled down dramatically. According to the reduction of the NAND flash memory dimension, it is necessary to increase the area of the ONO layer composed of the oxide-nitride-oxide three-layer structure in total to improve the control gate-to-floating gate coupling ratio (coupling ratio). For flash memories, a high coupling ratio (high coupling) means a low operating voltage and low power consumption. Typically, the floating gate profile is very vertical and the sidewalls of the floating gate are easily damaged during etching and wet processing, which may lead to retention problems, too slow programming, or even program failures.

Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to solve the above technical problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to overcome the existing problems, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:

providing a semiconductor substrate, and forming a plurality of floating gates arranged at intervals and a hard mask layer positioned on the floating gates on the semiconductor substrate;

forming a side wall on the side walls of the floating gate and the hard mask layer, wherein the side wall is made of amorphous carbon;

forming a shallow trench isolation structure in the semiconductor substrate between the adjacent floating gates;

and removing the hard mask layer and the side wall to expose the floating gate.

Further, the hard mask layer includes a first hard mask layer and a second hard mask layer which are stacked in sequence.

Further, the step of forming the shallow trench isolation structure includes:

etching the semiconductor substrate to form a shallow trench by taking the hard mask layer as a mask;

depositing an isolation material to fill the shallow trench, and performing chemical mechanical polishing until the isolation material is stopped in the first hard mask layer;

and etching back to remove part of the isolation material so as to form a shallow trench isolation structure, wherein the top surface of the shallow trench isolation structure is flush with the surface of the semiconductor substrate.

Further, a buffer layer is formed between the hard mask layer and the floating gate.

Further, the side wall is removed by an oxygen ashing method.

Further, after removing the hard mask layer and the side walls, a step of forming an inter-gate dielectric layer on the floating gate and the surface of the semiconductor substrate is also included.

Further, the inter-gate dielectric layer includes an ONO layer composed of oxide-nitride-oxide.

Further, the first hard mask layer is made of nitride, and the second hard mask layer is made of oxide.

Furthermore, the thickness range of the side wall is 100-500 angstroms.

Further, a tunneling oxide layer is formed between the floating gate and the semiconductor substrate.

In summary, according to the manufacturing method of the present invention, the amorphous carbon sidewall is used to protect the floating gate and the sidewall of the tunneling oxide layer from being damaged by corrosion in the etching process, and the ashing removal method of the amorphous carbon does not damage the oxide.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

fig. 1A to 1I are schematic cross-sectional views showing structures obtained by sequentially carrying out a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 2 shows a flow chart of steps of a method of fabricating a semiconductor device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain the technical solutions proposed by the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

In order to solve the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, and fig. 2 shows a flowchart of steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention, which mainly includes the following steps:

in step S201, providing a semiconductor substrate, and forming a plurality of floating gates arranged at intervals on the semiconductor substrate and a hard mask layer on the floating gates;

in step S202, forming a sidewall spacer on the sidewalls of the floating gate and the hard mask layer, wherein the material of the sidewall spacer includes amorphous carbon;

in step S203, a shallow trench isolation structure is formed in the semiconductor substrate between adjacent floating gates;

in step S204, the hard mask layer and the sidewall spacers are removed to expose the floating gate.

The manufacturing method can effectively avoid the damage to the side wall of the floating gate, thereby improving the performance of the device.

Example one

Next, a method for manufacturing a semiconductor device of the present invention is described in detail with reference to fig. 1A to 1I. Fig. 1A to 1I are schematic cross-sectional views showing structures obtained by sequentially carrying out a method of manufacturing a semiconductor device according to an embodiment of the present invention;

first, as shown in fig. 1A, a semiconductor substrate 100 is provided, and a tunnel oxide layer 101, a floating gate material layer 102a, a buffer layer 103, and a hard mask layer 104 are sequentially deposited and formed on the semiconductor substrate 100.

Specifically, the semiconductor substrate 100 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.

The material of the tunnel oxide layer 101 may be silicon oxide, and the method for forming the tunnel oxide layer may be thermal oxidation, or other suitable deposition method such as a chemical vapor deposition process, etc., and the thickness of the tunnel oxide layer is about several tens of angstroms, and in one example, the thickness of the tunnel oxide layer 101 may be 70 to 150 angstroms.

The floating gate material layer 102a may be made of a semiconductor material, such as silicon, polysilicon, Ge, or the like, but is not limited to a certain material, and in this embodiment, the floating gate material layer 102a is made of polysilicon.

The floating gate material layer 102a may be deposited by one of Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG).

Alternatively, the thickness of the floating gate material layer 102a may be in a range of 300 a to 600 a, which is only an example and is not a limitation on the thickness of the floating gate material layer of the present invention, and the thickness of the floating gate material layer 102a may be set to a reasonable value according to the size requirement of a specific device.

The buffer layer 103 is deposited on the surface of the floating gate material layer 102a, and may be made of an oxide, such as silicon oxide, or other suitable materials, and may be formed by any deposition technique known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, etc., or by thermal oxidation. The thickness of the buffer layer 103 may be in a range from 100 angstroms to 200 angstroms, and may be adjusted as needed.

The hard mask layer 104 may be a single film layer or a stack of multiple film layers, and when the hard mask layer is a single film layer, the hard mask layer may be made of silicon oxide, silicon nitride, silicon carbonitride, silicon carbide, or the like.

The hard mask layer 104 may also be formed by using a first hard mask layer 1041 and a second hard mask layer 1042 of different materials, where the first hard mask layer 1041 may be made of silicon nitride, silicon carbonitride, silicon carbide, or the like, in this embodiment, the first hard mask layer 1041 is made of silicon nitride, and the second hard mask layer 1042 is made of silicon oxide.

Methods including, but not limited to: the first hard mask layer 1041 and the second hard mask layer 1042 are sequentially formed by a chemical vapor deposition method and a physical vapor deposition method. Typically, the first hard mask layer 1041 has a thickness of from about 500 to about 1000 angstroms and the second hard mask layer 1042 has a thickness of from about 2000 to about 4000 angstroms.

Next, as shown in fig. 1B, the hard mask layer 104, the buffer layer 103, the floating gate material layer 102a and the tunnel oxide layer 101 are patterned until the semiconductor substrate 100 is exposed to form the floating gate 102.

Specifically, a patterned photoresist layer (not shown) may be formed on the surface of the hard mask layer 104 through a photolithography process, where the area covered by the photoresist layer corresponds to the size of a floating gate to be formed, and then the hard mask layer 104, the buffer layer 103, the floating gate material layer 102a, and the tunnel oxide layer 101 are sequentially etched through an etching process until the semiconductor substrate 100 is exposed to form the floating gate 102, where the etching process may use a dry etching process or a wet etching process, and the dry etching process includes, but is not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. Preferably, the dry etching is performed by one or more RIE steps. Finally, the photoresist layer can be removed by ashing or wet cleaning.

Next, as shown in fig. 1C, a sidewall spacer 105 is formed on each sidewall of the tunnel oxide layer 101, the floating gate 102, the buffer layer 103 and the hard mask layer 104, wherein a material of the sidewall spacer 105 includes Amorphous Carbon (AC).

Specifically, amorphous carbon may be deposited to cover the surface of the semiconductor substrate, and then the excess amorphous carbon may be removed using an etching process, which may be a blanket etching process to form the sidewall spacers 105. The sidewalls 105 may have different thicknesses, but the thickness of the sidewalls 105 may be formed in a range of 100 a to 500 a as measured from the side surfaces, which is merely exemplary and not intended to limit the present invention.

By decomposing the reaction gas C₃H₆、C₂H₄Or CH₄Equal carbon and hydrogen containing gas to obtain amorphous carbon for decomposition of C₃H₆For example, the process conditions for forming the amorphous carbon layer include: introducing C into the reaction chamber₃H₆Control of C₃H₆The flow range of (A) is 800 sccm-2500 sccm, and a buffer gas is introduced into the reaction chamber, wherein the buffer gas can contain He and N₂One or a combination thereof, and the reaction temperature range can be 350-500 ℃.

Next, as shown in fig. 1F, a shallow trench isolation structure 107 is formed in the semiconductor substrate 100 between adjacent floating gates 102, wherein a top surface of the shallow trench isolation structure is flush with the surface of the semiconductor substrate 100.

In one example, the step of forming the shallow trench isolation structure 107 includes:

first, as shown in fig. 1D, the hard mask layer 104, particularly the second hard mask layer 1042, is used as a mask to etch the semiconductor substrate 100 to form the shallow trench 106, the etching may use dry etching or wet etching, and a portion of the second hard mask layer 1042 is etched during the etching process, so that the thickness range of the second hard mask layer 1042 remaining after the formation of the shallow trench may be 100 angstroms to 500 angstroms.

Subsequently, as shown in fig. 1E, an isolation material 107a is deposited to fill the shallow trench 106, the isolation material 107a further overflows over the second hard mask layer 1042, and a Chemical Mechanical Polishing (CMP) is performed to stop in the first hard mask layer 1041, wherein the isolation material 107a may be silicon oxide, silicon oxynitride, fluorine-doped glass and/or other conventional low-k materials, and may be formed by any deposition process known to those skilled in the art, such as chemical vapor deposition, etc.

Subsequently, as shown in fig. 1F, an etch back removes a portion of the isolation material to form a shallow trench isolation structure 107, wherein the remaining isolation material completely fills the shallow trench.

The method for etching back to remove part of the isolation material may be etching or other suitable methods. The etching can be either dry etching or wet etching. The dry etching can employ an anisotropic etching method based on a carbon fluoride gas. The wet etching method can use a hydrofluoric acid solution, such as a Buffered Oxide Etchant (BOE) or a buffered hydrofluoric acid (BHF).

Further, the top surface of the shallow trench isolation structure 107 is made flush with the surface of the semiconductor substrate 100 after etching back, as shown in fig. 1F.

In the etching and etching back processes, the side walls 105 protect the floating gate 102 and the tunnel oxide layer 101 thereunder from being damaged.

Next, as shown in fig. 1G and fig. 1H, the hard mask layer and the sidewall spacers 105 are removed to expose the floating gate 102.

First, as shown in fig. 1G, the hard mask layer is removed, in this embodiment, in the foregoing step, the first hard mask layer 1041 remains, and is removed in this step, and a specific removing method of the first hard mask layer 1041 may select a suitable etching method according to a material thereof, including but not limited to dry etching or wet etching. Illustratively, when the material of the first hard mask layer 1041 is silicon nitride, it can be removed using a wet etchant such as hot phosphoric acid.

Next, the spacers 105 are removed to expose the floating gate 102 and the tunnel oxide layer 101.

The sidewall 105 is made of amorphous carbon, and the sidewall 105 of amorphous carbon may be removed by an oxygen ashing process. Wherein the reaction temperature of the oxygen ashing process can be 200-500 ℃. The amorphous carbon is removed by adopting an ashing method, so that damage to the oxide can be avoided.

Further, the buffer layer 103 may be selectively removed, and the buffer layer 103 may remain to be used as a portion of the inter-gate dielectric layer later.

Subsequently, as shown in fig. 1I, an inter-gate dielectric layer 108 is formed on the floating gate 102 and the surface of the semiconductor substrate 100.

Specifically, the intergate dielectric layer 108 may be an ONO layer. Specifically, the inter-gate dielectric layer 108 may be an ONO sandwich structure of three layers of oxide-nitride-oxide, and it should be understood by those skilled in the art that the inter-gate dielectric layer 108 may also be an insulating structure of a nitride layer, an oxide layer, or an oxide layer formed on a nitride layer. Methods including, but not limited to: the inter-gate dielectric layer 108 is formed by a low pressure chemical vapor deposition method, a chemical vapor deposition method, and a physical vapor deposition method. Taking the material of the inter-gate dielectric layer 108 as ONO for example, a uniform silicon oxide layer is formed by a low pressure chemical vapor deposition method, then a silicon nitride layer is formed on the silicon oxide layer by a low pressure chemical vapor deposition method, and then another silicon oxide layer is formed by a low pressure chemical vapor deposition method.

Thereafter, a control gate (not shown) is formed on the inter-gate dielectric layer 108.

The material of the control gate may include various materials including, but not limited to: certain metals, metal alloys, metal nitrides and metal silicides, and laminates and composites thereof. The material of the control gate may also include doped polysilicon and polysilicon-germanium alloy materials as well as polysilicon metal silicide materials (doped polysilicon/metal silicide stack materials). Similarly, any of several methods may be employed to form the foregoing materials. Non-limiting examples include chemical vapor deposition methods and physical vapor deposition methods, and the material of the control gate in this embodiment is a polysilicon layer.

The polysilicon is formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process. The process conditions for forming the polysilicon include: the reaction gas is Silane (SiH)₄) The flow rate of the silane can be 100-200 cubic centimeters per minute (sccm), such as 150 sccm; the temperature in the reaction cavity can be 700-750 ℃; the pressure in the reaction chamber can be 250 to 350 millimeters of mercury (mTorr), such as 300 mTorr; the reaction gas can also comprise a buffer gas, the buffer gas can be helium or nitrogen, and the flow range of the helium and the nitrogen can be 5-20 liters per minute (slm), such as 8slm, 10slm or 15 slm.

The main steps of the method of manufacturing a semiconductor device of the present invention have been completed up to this point, but it is conceivable that a plurality of preceding steps, intermediate steps and subsequent steps are required for the manufacture of the complete device.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate, forming a plurality of floating gates arranged at intervals on the semiconductor substrate, and forming a hard mask layer positioned on the floating gates, wherein the hard mask layer comprises a first hard mask layer and a second hard mask layer positioned on the first hard mask layer;

forming a shallow trench isolation structure in the semiconductor substrate between adjacent floating gates, the step of forming the shallow trench isolation structure comprising: etching the semiconductor substrate by taking the hard mask layer and the side wall as masks to form a shallow trench in the semiconductor substrate; depositing an isolation material to fill the shallow trench, and performing chemical mechanical polishing until the isolation material stops on the surface of the first hard mask layer; etching back to remove part of the isolation material so as to form a shallow trench isolation structure;

and after the shallow trench isolation structure is formed, removing the hard mask layer and the side wall to expose the floating gate.

2. The method of claim 1, wherein a top surface of the shallow trench isolation structure is flush with a surface of the semiconductor substrate.

3. The method of claim 1, further comprising forming a buffer layer between the hard mask layer and the floating gate.

4. The method of claim 1, wherein the sidewall is removed by oxygen ashing.

5. The method of claim 1, further comprising a step of forming an inter-gate dielectric layer on the floating gate and the surface of the semiconductor substrate after removing the hard mask layer and the spacers.

6. The method of claim 5, wherein the inter-gate dielectric layer comprises an oxide-nitride-oxide (ONO) layer.

7. The method of claim 1, wherein the first hard mask layer is a nitride and the second hard mask layer is an oxide.

8. The method as claimed in claim 1, wherein the thickness of the sidewall spacer is in the range of 100-500 angstroms.

9. The method of claim 1, further comprising forming a tunnel oxide layer between the floating gate and the semiconductor substrate.