CN104752363A - Forming method of flash memory - Google Patents
Forming method of flash memory Download PDFInfo
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- CN104752363A CN104752363A CN201310754246.3A CN201310754246A CN104752363A CN 104752363 A CN104752363 A CN 104752363A CN 201310754246 A CN201310754246 A CN 201310754246A CN 104752363 A CN104752363 A CN 104752363A
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- 230000015654 memory Effects 0.000 title claims abstract description 49
- 239000010410 layer Substances 0.000 claims abstract description 429
- 238000005530 etching Methods 0.000 claims abstract description 63
- 238000007667 floating Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000011241 protective layer Substances 0.000 claims abstract description 34
- 239000003989 dielectric material Substances 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims description 86
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 52
- 230000015572 biosynthetic process Effects 0.000 claims description 52
- 229920002120 photoresistant polymer Polymers 0.000 claims description 38
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 34
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 28
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 21
- 238000001039 wet etching Methods 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 19
- 238000004140 cleaning Methods 0.000 claims description 16
- 229910052757 nitrogen Inorganic materials 0.000 claims description 14
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910021529 ammonia Inorganic materials 0.000 claims description 6
- 239000003795 chemical substances by application Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 2
- 238000009832 plasma treatment Methods 0.000 claims description 2
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- 230000002093 peripheral effect Effects 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 2
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- 101000678879 Homo sapiens Atypical chemokine receptor 1 Proteins 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
A forming method of a flash memory comprises the following steps: providing a substrate; forming floating grids of a core region on the substrate, first trenches in the substrate among the floating grids, grid electrodes of a peripheral region, second trenches in the substrate among the grid electrodes, a stop layer on the floating grids and the grid electrodes, and a hard mask layer on the stop layer; forming a dielectric material layer; chemically and mechanically grinding the dielectric layer and the hard mask layer, using the dielectric material layer between adjacent floating grids as a first dielectric layer, and using the dielectric material layer between adjacent grid electrodes as a second dielectric layer; forming a protective layer on the second dielectric layer, then using the protective layer as a mask, rinsing to remove the residual hard mask layer in the peripheral region; etching to remove the stop layer, wherein the protective layer is also removed by etching during the process; patterning the first dielectric layer to form a shallow trench isolating structure. The flash memory formed thereby is better in performance, with a product yield meeting the requirements of mass production.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of flash memory.
Background technology
At present, flash memory (Flash Memory), also known as flash memory, has become the main flow memory of non-volatility memorizer.Different according to structure, flash memory can be divided into or non-flash (NOR Flash) and with non-flash (NAND Flash).The main feature of flash memory is the information that can keep for a long time when not powering up storing; And have that integrated level is high, access speed is fast, be easy to the advantages such as erasing and rewriting, be thus widely used in the multinomial field such as microcomputer, Automated condtrol.
Existing flash memory comprises the peripheral circuit (Peripheral Circuit) being positioned at suprabasil core memory circuit (Cell Circuit) and being positioned at around core memory circuit.Described core memory circuit comprises some and has transistor compared with small-feature-size, and peripheral circuit mainly comprises the conventional MOS transistor with some high pressure compared with large-feature-size and mesolow circuit, if embedded, also have corresponding low voltage logic circuit.Wherein, the distance between the grid of the adjacent two transistor in core memory circuit is very little, and distance between the grid of two transistor in peripheral circuit is relatively large.
The formation method of existing flash memory comprises:
With reference to Fig. 1, substrate 10 is provided, described substrate 10 is divided into core space I and external zones II, be formed with floating boom multiple spaced apart from each other (the Floating Gate of core space I on the substrate 10, FG) 11 and the grid 12 multiple spaced apart from each other of external zones II, and be positioned at the stop-layer 13 on described floating boom 11, grid 12, the hard mask layer 14 be positioned on stop-layer 13, the material of stop-layer 13 is silicon nitride, the material of hard mask layer 14 is silica, and the width of floating boom 11 is less than the live width of grid 12 and the spacing W between adjacent two grids 12
2be greater than the spacing W between adjacent two floating booms 11
1, the spacing between arbitrary neighborhood two grid 12 is also not quite similar.In addition, when etching formation hard mask layer 14, because floating boom live width is less than grid live width, the etching of hard mask layer 14 side of core space I be can not ignore, and causes the hard mask layer of external zones II thinner, thinner than the hard mask layer of core space I;
With hard mask layer 14 for mask, etch segment thickness substrate between adjacent two floating booms 11 and form the first groove (in figure non-label), and between adjacent two grids 12 of etching, segment thickness substrate forms the second groove (in figure non-label), due to W
2>W
1, between adjacent two grids 12, the etch rate of substrate is greater than the etch rate of substrate between adjacent two floating booms 11, makes the degree of depth D of described second groove
2be greater than the degree of depth D of the first groove
1;
With reference to Fig. 2, on the substrate 10 deposited oxide silicon material layer 15, silica material layer 15 covers hard mask layer 14, fills full first groove and the second groove, and the silica material layer in the first groove, the second groove has the part exceeding hard mask layer 14.
With reference to Fig. 3, cmp silica material layer 15(with reference to Fig. 2), stop to stop-layer 13 upper surface, in process of lapping, the hard mask layer of core space I is polished, but the hard mask layer 14 of external zones II has residual.Between adjacent two floating booms 11, remaining silica material layer maintains an equal level as the first silicon oxide layer 16, first silicon oxide layer 16 upper surface and stop-layer 13 upper surface; Between adjacent two grids 12, remaining silica material layer is as the second silicon oxide layer 17.In addition due to W
2>W
1, the grinding rate of the silica material layer segment of corresponding second grooved position is greater than the grinding rate of the silica material layer segment of the first grooved position, and the second silicon oxide layer 17 upper surface therefore after grinding is a little less than stop-layer 13 upper surface, and recessed.In figure 3, the second silicon oxide layer 17 upper surface after empty wire frame representation grinding.
With reference to Fig. 4, the residual hard mask layer 14(of cleaning external zones II is with reference to Fig. 3) to guarantee that stop-layer 13(is with reference to Fig. 3) on do not have hard mask layer residual and to cause follow-up stop-layer to remove unclean.But in cleaning process, the second silicon oxide layer 17 is also cleaned, the height of the second silicon oxide layer 17 is reduced further, in conjunction with reference to Fig. 2, make the second silicon oxide layer 17 lower than grid 12, and the second silicon oxide layer 17 upper surface continue depression and form the first groove 18;
Do not use mask, etching removes stop-layer 13.
With reference to Fig. 5, the first silicon oxide layer 16(of patterned part height is with reference to Fig. 4), remain the first silicon oxide layer part higher than substrate 10 upper surface, as fleet plough groove isolation structure;
On floating boom 11 upper surface and sidewall, fleet plough groove isolation structure upper surface, grid 12 and the first groove surfaces form insulating barrier 19;
Formation control gate material layer 20 on insulating barrier 19;
Control gate material layer 20 is formed amorphous carbon layer 21, the silicon oxynitride layer 22 be positioned on amorphous carbon layer 21, silicon oxynitride layer 22 is as dielectric anti-reflective layer (Dielectric Anti-Reflection Coating, DARC), amorphous carbon layer 21 can improve the fineness of subsequent etching quality and figure;
The patterned photoresist layer 24 silicon oxynitride layer 22 being formed bottom anti-reflection layer (Bottom Anti-Reflection Coating, BARC) 23 and is positioned in bottom anti-reflection layer 23, patterned photoresist layer 24 defines control gate position.
With reference to Fig. 6, with patterned photoresist layer for mask, etching bottom anti-reflecting layer 23, silicon oxynitride layer 22, amorphous carbon layer 21 and control gate material layer 20(are with reference to Fig. 5), stop to insulating barrier 19, formation control grid 25.Remove patterned photoresist layer and residue bottom anti-reflection layer, silicon oxynitride layer, amorphous carbon layer afterwards.
But the performance of the flash memory using prior art to be formed is not good.
Summary of the invention
The problem that the present invention solves is, the performance of the flash memory using prior art to be formed is not good.
For solving the problem, the invention provides a kind of formation method of flash memory, the formation method of this flash memory comprises:
Form the first groove between the multiple floating boom of core space, adjacent two floating booms in substrate on the substrate, and multiple grids of described external zones, the second groove between adjacent two grids in substrate, with the stop-layer be positioned on described floating boom, on grid, the hard mask layer be positioned on described stop-layer, described floating gate width is less than grid width and the first groove width is less than the second groove width;
Form dielectric materials layer, described dielectric materials layer covers described hard mask layer, fills full first groove and the second groove, and the dielectric materials layer in described first groove, the second groove has the part exceeding hard mask layer;
Described in cmp, dielectric materials layer, hard mask layer stop to described stop-layer, and between adjacent two floating booms, remaining dielectric material layer segment is as the first dielectric layer, and between adjacent two grids, remaining dielectric material layer segment is as the second dielectric layer;
Described second dielectric layer forms protective layer, afterwards with described protective layer for mask, the residual hard mask layer part in described external zones is removed in cleaning;
Etching removes described stop-layer, and in this process, also etching removes described protective layer;
After etching removes stop-layer, graphically described first dielectric layer forms fleet plough groove isolation structure.
Alternatively, described dielectric material is silica, and the material of described hard mask layer is silica, and described stop-layer material is silicon nitride.
Alternatively, described protective layer material is silicon oxynitride.
Alternatively, Rapid Thermal Nitrided, the process of decoupled plasma nitrogen or microwave nitrogen plasma treatment are carried out to described second dielectric layer upper surface, described second dielectric layer forms silicon oxynitride.
Alternatively, the gas that described Rapid Thermal Nitrided process uses is ammonia, and temperature range is 700 DEG C ~ 1000 DEG C, and the duration is 30s ~ 90s, and the range of flow of ammonia is 1000sccm ~ 10000sccm.
Alternatively, in nitrogen environment, the process of decoupled plasma nitrogen is carried out.
Alternatively, the thickness range of described protective layer is
.
Alternatively, etching removes the method for stop-layer is wet etching.
Alternatively, the etching agent that described wet etching uses is phosphoric acid solution.
Alternatively, use wet etching or dry etching, the residual hard mask layer part in described external zones is removed in cleaning.
Alternatively, the etching agent that described wet etching process uses is dilute hydrofluoric acid solution.
Alternatively, described fleet plough groove isolation structure is higher than upper surface of substrate.
Alternatively, the formation method of described floating boom, the first groove, grid, the second groove, hard mask layer and stop-layer comprises:
Form gate material layer on the substrate, the stopping material layer being positioned in gate material layer, described stop-layer forms layer of hard mask material;
Described layer of hard mask material forms patterned photoresist layer, the position of described patterned photoresist layer definition floating boom, grid;
With described patterned photoresist layer for mask, the gate material layer of gate material layer formation floating boom and etching external zones that etch hard mask materials layer forms hard mask layer and etching stopping material layer formation stop-layer and etching core space forms grid;
Remove patterned photoresist layer;
With described hard mask layer for the substrate of mask etching segment thickness forms the first groove, the second groove.
Alternatively, the method for etched portions thickness first dielectric layer is dry etching, or wet etching, or first dry etching, rear wet etching.
Alternatively, after the first dielectric layer of etched portions thickness, between adjacent two floating booms, form the 3rd groove;
The formation method of described flash memory also comprises: form insulating barrier and the multiple control gates being positioned at described core space laid out in parallel, described insulating barrier covers described 3rd trenched side-wall and bottom, the second dielectric layer and grid, and each control gate fills full multiple 3rd groove, the insulating barrier part covered on described floating boom.
Alternatively, on described insulating barrier, the method for formation control grid comprises:
Chemical vapour deposition (CVD) insulating barrier, the control gate material layer be positioned on insulating barrier;
Graphical formation control grid are carried out to described control gate material layer.
Alternatively, carrying out patterned method to described control gate material layer is self-alignment duplex pattern method.
Alternatively, described self-alignment duplex pattern method comprises:
Described control gate material layer forms hard mask layer;
Described hard mask layer is formed the first amorphous carbon layer, the first dielectric anti-reflective layer be positioned on described first amorphous carbon layer;
Described first dielectric anti-reflective layer forms the second amorphous carbon layer, the second dielectric anti-reflective layer be positioned on described second amorphous carbon layer;
Described second dielectric anti-reflective layer forms bottom anti-reflection layer, the photoresist layer be positioned in bottom anti-reflection layer;
Described photoresist layer is carried out graphically, and with the photoresist layer after graphical be mask etching bottom anti-reflection layer, the second dielectric anti-reflective layer and the second amorphous carbon layer form multiple first strip piece;
Side wall is formed, the position of the corresponding control gate of described side wall in described first strip piece two side;
With described side wall be mask etching first strip piece, the first dielectric anti-reflective layer and the first amorphous carbon layer, hard mask layer, form the second strip piece;
Remove residue first dielectric anti-reflective layer, the first amorphous carbon layer, afterwards, to remain hard mask layer for mask etching control gate material layer formation control grid.
Compared with prior art, technical scheme of the present invention has the following advantages:
After chemical mechanical polishing, external zones remains hard mask layer part.Second dielectric layer forms protective layer, and when cleaning the hard mask layer part that removal external zones remains, protective layer protects the second dielectric layer to exempt from cleaning loss.Like this, compared with prior art, the difference in height between the second dielectric layer upper surface and gate upper surface is less, and the second dielectric layer upper surface can not form darker groove, also would not have an impact to follow-up formation control grid process.Like this, the second dielectric layer of external zones can not produce pseudo-control gate defect, the Signal transmissions between each transistor of Absorbable organic halogens external zones, promote read/write speed and the read/write quality of flash memory, the performance of flash memory is better.And external zones, would not parameter measure on interfering line without pseudo-control gate defect, and final products yield meets volume production requirement.
Accompanying drawing explanation
Fig. 1 ~ Fig. 6 is the cross-sectional view of flash memory in forming process of prior art;
Fig. 7 ~ Figure 16 is the cross-sectional view of flash memory in forming process of the specific embodiment of the invention.
Embodiment
Analyze for prior art, find: with reference to Fig. 4, the second silicon oxide layer 17 upper surface is lower than grid 12 upper surface, and difference in height between larger the second silicon oxide layer 17 of width and grid 12 is larger, is greater than
, the second silicon oxide layer 17 upper surface in darker be the first darker groove 18.
With reference to Fig. 4, Fig. 5, there is the control gate layer material sections upper surface on the first groove 18 of less width and the control gate layer material sections on grid 12 remains basically stable, and there is the control gate layer material sections of the control gate layer material sections on the first groove 18 of larger width lower than surrounding, in control gate material layer 20, namely form the second groove (in figure non-label).Second groove pattern passes to amorphous carbon layer 21, silicon oxynitride layer 22 successively, in amorphous carbon layer 21, form the 3rd groove and form the 4th groove (in figure non-label) in silicon oxynitride layer 22, but from the first groove, the second groove, the 3rd groove to the 4th groove, width reduces gradually.Bottom anti-reflection layer 23 upper surface is smooth, but the thickness H of the bottom anti-reflective layer segment of corresponding 4th groove location
2the 4th groove is greater than the thickness H1 of the bottom anti-reflective layer segment of surrounding, this is because can assemble more bottom anti-reflective material compared to plane.
Like this, with reference to Fig. 5, Fig. 6, be mask etching bottom anti-reflection layer 23 with patterned photoresist layer 24, expose to silicon oxynitride layer 22, the silicon oxynitride layer segment of the 4th bottom portion of groove is not also removed completely, has residual.Then, continue etching silicon oxynitride layer 22 to amorphous carbon layer 21, in this process, the bottom anti-reflective layer segment of the 4th bottom portion of groove is removed, and the silicon oxynitride layer segment under the 4th bottom portion of groove is not removed completely, has residual.And then etching amorphous carbon layer 21, under the condition of etching amorphous carbon layer 21, amorphous carbon is compared silicon oxynitride and is had higher etching selection ratio, remain silicon oxynitride layer part under 4th bottom portion of groove substantially not etched, and the amorphous carbon layer segment under the 4th bottom portion of groove is not etched.Afterwards, etching control gate material layer 20 process, the control gate material layer under the 4th bottom portion of groove is not etched.At the patterned photoresist layer of removal with after remaining bottom anti-reflection layer, silicon oxynitride layer, amorphous carbon layer, form pseudo-control gate 26 in corresponding 4th bottom portion of groove position.Pseudo-control gate 26 may cause the signal cross-talk between each transistor in external zones, causes flash memory read/write speed, even causes read/write errors, cause flash memory performance not good.And during defective workmanship detects on line, pseudo-control gate is considered to the source of defect, and pseudo-control gate causes interference to defective workmanship testing process, causes and be difficult to even cannot other defect be detected, cause product yield to decline.
For solving prior art Problems existing, technical solution of the present invention proposes a kind of formation method of new flash memory.Use the formation method of this flash memory, after cmp dielectric materials layer forms the first dielectric layer and the second dielectric layer, the second dielectric layer forms protective layer.Like this, cleaning remains in the hard mask layer partial routine on stop-layer, and protective layer protects the second dielectric layer to exempt from cleaning loss.Protective layer prevents the second dielectric layer surface from suffering more losses, guarantees that the second dielectric layer suffers less etching.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to Fig. 7, provide substrate 100, substrate 100 comprises core space I and external zones II.In the present embodiment, will the piled grids formula transistor of core memory circuit be formed at core space I, will the MOS transistor of peripheral circuit be formed at external zones II.
In a particular embodiment, substrate 100 is silicon base, germanium substrate or silicon-on-insulator substrate etc.; Or the III-V such as the material of substrate 100 can also comprise other material, such as GaAs.Those skilled in the art can select substrate according to the transistor types that substrate 100 is formed, and the type of therefore substrate should not limit the scope of the invention.
With reference to Fig. 8, substrate 100 is formed the floating boom 101 multiple spaced apart from each other of core space I and the grid 102 multiple spaced apart from each other of external zones II, and the width of floating boom 101 is less than the width of grid 102, the spacing W between adjacent two floating booms 101
1be less than the spacing W between adjacent two grids 102
2, make the distribution density of floating boom 101 be greater than the distribution density of grid 102.Floating boom 101, grid 102 are formed with stop-layer 105, the hard mask layer 115 be positioned on stop-layer 105.Wherein, between floating boom 101 and substrate, between grid 102 and substrate, gate dielectric layer 106 is formed with.
It should be noted that, the spacing between each grid live width of external zones II, adjacent two grids is also not quite similar.
In a particular embodiment, the formation method of gate dielectric layer 106, floating boom 101, grid 102, hard mask layer 115 and stop-layer 105 comprises:
Substrate 100 is formed gate dielectric material layer, and the material of this gate dielectric material layer is silica, specifically can use chemical vapour deposition (CVD) or thermal oxide growth technique;
Gate dielectric material layer is formed gate material layer, the stopping material layer being positioned in gate material layer, is positioned at the layer of hard mask material stopped on material layer, grid material is polysilicon, hard mask material is silica, and stop-layer material is silicon nitride, specifically can use chemical vapor deposition method;
Described layer of hard mask material forms patterned photoresist layer, the position of patterned photoresist layer definition floating boom, grid;
With described patterned photoresist layer for mask, the gate material layer of gate material layer formation floating boom 101 and etching external zones II that etch hard mask materials layer forms hard mask layer 115 and etching stopping material layer formation stop-layer 105 and etching core space I forms grid 102 and etches gate dielectric material layer and forms gate dielectric layer 106;
Remove patterned photoresist layer.When etch hard mask materials layer, the hard mask layer side under patterned photoresist layer also can be etched.Width due to floating boom 101 is less than the width of grid 102, at external zones II, the etch amount of the hard mask layer side under patterned photoresist layer is insignificant compared with its width, and the thickness of the hard mask layer 115 of external zones II is substantially equal with the thickness of layer of hard mask material.And at core space I, the etch amount of the hard mask layer side under patterned photoresist layer, compared with its width, can not be ignored, the thickness of the hard mask layer 115 of final core space I is caused to be less than the thickness of layer of hard mask material.So the thickness of the hard mask layer 115 of external zones II is greater than the thickness of the hard mask layer 115 of core space I.
With reference to Fig. 9, with hard mask layer 115 for mask, etching substrate 100 forms the second groove 104 between the first groove 103 between adjacent two floating booms 101 in substrate and adjacent two grids 102 in substrate.The degree of depth D of the second groove 104
2be greater than the degree of depth D of the first groove 103
1.
With reference to Figure 10, form dielectric materials layer 107, dielectric materials layer 107 covers hard mask layer 115, fills full first groove 103 and the second groove 104(reference Fig. 9), and the dielectric materials layer in the first groove, the second groove has the part exceeding hard mask layer 115.
In a particular embodiment, the material of dielectric materials layer 107 is silica, and chemical vapour deposition (CVD) can be used to be formed.
With reference to Figure 11, cmp dielectric materials layer 107, hard mask layer 115(are with reference to Fig. 9), stop to stop-layer 105.Wherein, the hard mask layer 115 of core space I is thinner and be polished, and the hard mask layer 115 of external zones II is thicker and have residual.After grinding, between adjacent two floating booms 101, remaining dielectric material layer segment is as the first dielectric layer 108, and between adjacent two grids 102, remaining dielectric material layer segment is as the second dielectric layer 109.
Due to W
2>W
1second dielectric layer 109 upper surface area is greater than the first dielectric layer 108 upper surface area, therefore, in chemical mechanical planarization process, the grinding rate of the dielectric material layer segment of corresponding second grooved position is greater than the grinding rate of the dielectric material layer segment of the first grooved position, make the second dielectric layer 109 is indicated a little less than stop-layer 105, and the second dielectric layer 109 upper surface is groove-like.
With reference to Figure 12, the second dielectric layer 109 forms protective layer 110.
In a particular embodiment, the material of protective layer 110 is silicon oxynitride.Particularly; Rapid Thermal Nitrided (Rapid Thermal Nitridation is carried out to the second dielectric layer 109 upper surface; RTN), decoupled plasma nitrogen process (Decoupled Plasma Nitridation; DPN) or microwave nitrogen plasma (MicrowaveGenerated Nitrogen Plasma) process; second dielectric layer 109 forms silicon oxynitride, and this silicon oxynitride is as protective layer 110.Wherein, in nitrogen environment, the process of decoupled plasma nitrogen is carried out.
In the present embodiment, first form photoresist layer at core space I, this photoresist layer covers the first dielectric layer 108, the stop-layer 105 of core space I; Afterwards, use rapid thermal nitridation process, the second dielectric layer 110 forms protective layer 110.Described Rapid Thermal Nitrided refers to carries out quick thermal annealing process, and passes into ammonia simultaneously, and in Rapid Thermal Nitrided process, the silica on nitrogen and the second dielectric layer 110 surface reacts and generates silicon oxynitride.In Rapid Thermal Nitrided process, keep temperature to be 700 DEG C ~ 1000 DEG C, the duration is 30s ~ 90s, and the range of flow of ammonia is 1000sccm ~ 10000sccm.If the duration is less than 30s, then cannot form the protective layer of minimum predetermined thickness; If the duration is greater than 90s, then the protective layer formed is blocked up, is unfavorable for removing in subsequent technique.
In the present embodiment, the thickness range of protective layer 110 is
.If the thickness of protective layer 110 is less than
, remove in follow-up cleaning in the process of residual hard mask layer part, protective layer may can not be played the effect of protection second dielectric layer 109 by comparatively fast washing, and produces prior art Problems existing further.If the thickness of protective layer 110 is greater than
, protective layer 110 is removed in stop-layer process in etching and is difficult to be removed.
With reference to Figure 13, with protective layer 110 for mask, cleaning removes the residual hard mask layer 115(of external zones II with reference to Figure 12) part, in cleaning process, protective layer 110 protects the second dielectric layer 109 to exempt from cleaning loss.
In a particular embodiment, use dry etching or wet etching, the residual hard mask layer part of external zones II is removed in cleaning.In the present embodiment, use wet etching, the etching agent used in wet etching process is dilute hydrofluoric acid solution.
Compared to prior art, the second dielectric layer 109 can not suffer to clean loss, and the thickness of the second dielectric layer 109 can not become lower, and the difference in height between the second dielectric layer upper surface and gate upper surface is less than
, and the difference in height between the second dielectric layer upper surface of prior art after the residual hard mask layer part of cleaning and gate upper surface is greater than
.Like this, the groove of the second dielectric layer upper surface is more shallow, can not have an impact, the second dielectric layer can not produce pseudo-control gate defect to follow-up formation control grid process.
With reference to Figure 14, etching removes stop-layer 105(with reference to Figure 13).In etching stop layer 105 process, do not form mask layer, stop-layer 105, protective layer 107 and the first dielectric layer 108 all directly contact with etching atmosphere.Due under etching stop layer 105 condition, protective layer and etching stop layer have close etching selection ratio, and therefore, when etching stop layer, protective layer is also etched removal.
In a particular embodiment, etching removes the method for stop-layer is wet etching.The etching agent used in wet etching process is phosphoric acid solution, and this technique be well known to those skilled in the art is not described in detail in this.
With reference to Figure 15, after etching removes stop-layer, graphical first dielectric layer 108(is with reference to Figure 14) form fleet plough groove isolation structure 111, and the 3rd groove 112 is formed between adjacent two floating booms 101.In the present embodiment, fleet plough groove isolation structure 111 has the part exceeding upper surface of substrate, and this can increase the distance between control gate and active area, realizes control gate and more effectively controls floating boom.
In a particular embodiment, the method for graphical first dielectric layer comprises: first form patterned photoresist layer, the position of described patterned photoresist layer definition core space I; With patterned photoresist layer for mask, the first dielectric layer of etched portions thickness forms fleet plough groove isolation structure; Afterwards, patterned photoresist layer is removed.
In a particular embodiment, the method for the first dielectric layer of etched portions thickness is dry etching or wet etching.In the present embodiment, first dry etching, rear wet-etching technology is used.Dry etching has good anisotropic etching, and the etch rate of wet etching to the first dielectric layer portions of floating boom 101 sidewall is less, make the angle between fleet plough groove isolation structure 111 upper surface and the 3rd groove 112 become round and smooth, which further increases the distance between control gate and active area.
With reference to Figure 16, after formation fleet plough groove isolation structure 111, form insulating barrier 113 and the control gate 114 multiple arranged side by side being positioned at core space I, insulate 113 layers and cover the 3rd groove 112(with reference to Figure 15) sidewall and bottom, the second dielectric layer 109 and grid 102, each control gate 114 fills full multiple the 3rd groove, insulating barrier part covered on floating boom 101 be located along the same line.
In a particular embodiment, the method for formation control grid comprises on the insulating layer:
Chemical vapour deposition (CVD) insulating barrier, the control gate material layer be positioned on insulating barrier, insulating barrier is silica, be positioned at the silicon nitride on silica and be positioned at the laminated construction of the silica on silicon nitride, control gate material is polysilicon, when depositional control gate material layer, because the groove of the second dielectric layer upper surface is more shallow, the upper surface of control gate layer material sections of corresponding second dielectric layer position and the upper surface of the control gate layer material sections of surrounding remain basically stable;
Graphical formation control grid are carried out to control gate material layer.
In the present embodiment, carrying out patterned method to control gate material layer is self-alignment duplex pattern method.The graphical method of described autoregistration comprises:
Control gate material layer forms hard mask layer;
Hard mask layer is formed the first amorphous carbon layer, the first dielectric anti-reflective layer be positioned on the first amorphous carbon layer, the material of the first dielectric anti-reflective layer is SiON;
First dielectric anti-reflective layer forms the second amorphous carbon layer, the second dielectric anti-reflective layer be positioned on the second amorphous carbon layer, the material of the second dielectric anti-reflective layer is SiON;
Second dielectric anti-reflective layer forms bottom anti-reflection layer, the photoresist layer be positioned in bottom anti-reflection layer;
Carry out graphically to photoresist layer, at patterned exposure process, bottom anti-reflection layer be used for reducing below each layer to the reflection of exposure light, afterwards with the photoresist layer after graphical be mask etching bottom anti-reflection layer, the second dielectric anti-reflective layer, the second amorphous carbon layer form multiple first strip piece.In this process, the photoresist layer after graphical also can suffer part or all of etching, if suffer partial etching, then after formation first strip piece, removes remaining photoresist layer part.
Side wall is formed, the corresponding control gate position of side wall in the first strip piece two side;
Take side wall as mask etching first strip piece, the first dielectric anti-reflective layer and the first amorphous carbon layer, hard mask layer, form the second strip piece;
Remove residue first dielectric anti-reflective layer, the first amorphous carbon layer, afterwards, to remain hard mask layer for mask etching control gate material layer formation control grid.The control gate figure using self-alignment duplex pattern method to be formed is meticulousr, and size conforms is expected.
Like this, the stack grid structure of the control gate 114 that comprises on floating boom 101, floating boom 101 and the insulating barrier between control gate 114 and floating boom 101 is formed at core space I.Afterwards, in floating boom 101 both sides substrate, the medium-sized source electrode of grid 102 both sides substrate, drain electrode (not shown).
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (18)
1. a formation method for flash memory, is characterized in that, comprising:
There is provided substrate, described substrate comprises core space and external zones;
Form the first groove between the multiple floating boom of core space, adjacent two floating booms in substrate on the substrate, and multiple grids of described external zones, the second groove between adjacent two grids in substrate, with the stop-layer be positioned on described floating boom, on grid, the hard mask layer be positioned on described stop-layer, described floating gate width is less than grid width and the first groove width is less than the second groove width;
Form dielectric materials layer, described dielectric materials layer covers described hard mask layer, fills full first groove and the second groove, and the dielectric materials layer in described first groove, the second groove has the part exceeding hard mask layer;
Described in cmp, dielectric materials layer, hard mask layer stop to described stop-layer, and between adjacent two floating booms, remaining dielectric material layer segment is as the first dielectric layer, and between adjacent two grids, remaining dielectric material layer segment is as the second dielectric layer;
Described second dielectric layer forms protective layer, afterwards with described protective layer for mask, the residual hard mask layer part in described external zones is removed in cleaning;
Etching removes described stop-layer, and in this process, also etching removes described protective layer;
After etching removes stop-layer, graphically described first dielectric layer forms fleet plough groove isolation structure.
2. the formation method of flash memory as claimed in claim 1, it is characterized in that, described dielectric material is silica, and the material of described hard mask layer is silica, and described stop-layer material is silicon nitride.
3. the formation method of flash memory as claimed in claim 2, it is characterized in that, described protective layer material is silicon oxynitride.
4. the formation method of flash memory as claimed in claim 3, is characterized in that, carry out Rapid Thermal Nitrided, the process of decoupled plasma nitrogen or microwave nitrogen plasma treatment, described second dielectric layer forms silicon oxynitride to described second dielectric layer upper surface.
5. the formation method of flash memory as claimed in claim 4, it is characterized in that, the gas that described Rapid Thermal Nitrided process uses is ammonia, and temperature range is 700 DEG C ~ 1000 DEG C, duration is 30s ~ 90s, and the range of flow of ammonia is 1000sccm ~ 10000sccm.
6. the formation method of flash memory as claimed in claim 4, is characterized in that, carry out the process of decoupled plasma nitrogen in nitrogen environment.
7. the formation method of flash memory as claimed in claim 1, it is characterized in that, the thickness range of described protective layer is
.
8. the formation method of flash memory as claimed in claim 3, is characterized in that, the method that etching removes stop-layer is wet etching.
9. the formation method of flash memory as claimed in claim 8, is characterized in that, the etching agent that described wet etching uses is phosphoric acid solution.
10. the formation method of flash memory as claimed in claim 2, is characterized in that, uses wet etching or dry etching, and the residual hard mask layer part in described external zones is removed in cleaning.
The formation method of 11. flash memories as claimed in claim 10, is characterized in that, the etching agent that described wet etching process uses is dilute hydrofluoric acid solution.
The formation method of 12. flash memories as claimed in claim 1, it is characterized in that, described fleet plough groove isolation structure is higher than upper surface of substrate.
The formation method of 13. flash memories as claimed in claim 1, it is characterized in that, the formation method of described floating boom, the first groove, grid, the second groove, hard mask layer and stop-layer comprises:
Form gate material layer on the substrate, the stopping material layer being positioned in gate material layer, described stop-layer forms layer of hard mask material;
Described layer of hard mask material forms patterned photoresist layer, the position of described patterned photoresist layer definition floating boom, grid;
With described patterned photoresist layer for mask, the gate material layer of gate material layer formation floating boom and etching external zones that etch hard mask materials layer forms hard mask layer and etching stopping material layer formation stop-layer and etching core space forms grid;
Remove patterned photoresist layer;
With described hard mask layer for the substrate of mask etching segment thickness forms the first groove, the second groove.
The formation method of 14. flash memories as claimed in claim 1, is characterized in that, the method for etched portions thickness first dielectric layer is dry etching, or wet etching, or first dry etching, rear wet etching.
The formation method of 15. flash memories as claimed in claim 1, is characterized in that, after the first dielectric layer of etched portions thickness, between adjacent two floating booms, forms the 3rd groove;
The formation method of described flash memory also comprises: form insulating barrier and the multiple control gates being positioned at described core space laid out in parallel, described insulating barrier covers described 3rd trenched side-wall and bottom, the second dielectric layer and grid, and each control gate fills full multiple 3rd groove, the insulating barrier part covered on described floating boom.
The formation method of 16. flash memories as claimed in claim 15, it is characterized in that, on described insulating barrier, the method for formation control grid comprises:
Chemical vapour deposition (CVD) insulating barrier, the control gate material layer be positioned on insulating barrier;
Graphical formation control grid are carried out to described control gate material layer.
The formation method of 17. flash memories as claimed in claim 16, is characterized in that, carrying out patterned method to described control gate material layer is self-alignment duplex pattern method.
The formation method of 18. flash memories stated as claim 17, is characterized in that, described self-alignment duplex pattern method comprises:
Described control gate material layer forms hard mask layer;
Described hard mask layer is formed the first amorphous carbon layer, the first dielectric anti-reflective layer be positioned on described first amorphous carbon layer;
Described first dielectric anti-reflective layer forms the second amorphous carbon layer, the second dielectric anti-reflective layer be positioned on described second amorphous carbon layer;
Described second dielectric anti-reflective layer forms bottom anti-reflection layer, the photoresist layer be positioned in bottom anti-reflection layer;
Described photoresist layer is carried out graphically, and with the photoresist layer after graphical be mask etching bottom anti-reflection layer, the second dielectric anti-reflective layer and the second amorphous carbon layer form multiple first strip piece;
Side wall is formed, the position of the corresponding control gate of described side wall in described first strip piece two side;
With described side wall be mask etching first strip piece, the first dielectric anti-reflective layer and the first amorphous carbon layer, hard mask layer, form the second strip piece;
Remove residue first dielectric anti-reflective layer, the first amorphous carbon layer, afterwards, to remain hard mask layer for mask etching control gate material layer formation control grid.
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