CN110854120A - Method for forming semiconductor - Google Patents
Method for forming semiconductor Download PDFInfo
- Publication number
- CN110854120A CN110854120A CN201911183899.4A CN201911183899A CN110854120A CN 110854120 A CN110854120 A CN 110854120A CN 201911183899 A CN201911183899 A CN 201911183899A CN 110854120 A CN110854120 A CN 110854120A
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- Prior art keywords
- layer
- floating gate
- etching
- patterned
- forming
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- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000005530 etching Methods 0.000 claims abstract description 32
- 238000001039 wet etching Methods 0.000 claims abstract description 19
- 230000005641 tunneling Effects 0.000 claims abstract description 14
- 238000001312 dry etching Methods 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a method for forming a semiconductor, which comprises the following steps: providing a semiconductor; forming a tunneling oxide layer on the semiconductor; etching the tunneling oxide layer and the substrate to form a shallow trench isolation structure; sequentially forming a floating gate layer and a mask layer on the tunneling oxide layer and the shallow trench isolation structure; etching the mask layer and the floating gate layer to form a groove, a patterned floating gate layer and a patterned mask layer; filling oxide into the trench by taking the patterned mask layer as a mask; removing the patterned mask layer; wet etching the patterned floating gate layer to enable corners of the patterned floating gate layer to be rounded corners; dry etching part of the oxide in the groove; and wet etching the rest part of the oxide in the groove. In the semiconductor forming method provided by the invention, after the right-angled cylindrical patterned floating gate layer is formed, wet etching and dry etching humidification etching methods are adopted, so that the etching amount can be balanced, the deviation of the etching amount is reduced, and the programming and reading and writing of a semiconductor device are finally improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor forming method.
Background
In the existing 19NAND project, the process for etching the ST I oxide layer on the side edge of the floating gate is a wet etching and dry etching process, so that the top of the floating gate is smooth, the side wall part of the floating gate is consumed, the space is increased, and the bottom of the U-shaped groove is smooth to prevent point discharge. The wet etching and dry etching process has the problem that the etching precision is greatly influenced by the size consistency of the active area, and the control of key etching precision parameters is specifically shown as follows: small area etching is relatively slow, and large area etching is fast. The invention deeply analyzes the fundamental reason causing the fluctuation of the etching precision, namely that the dry etching process is very sensitive to the etching area, the small-area etching speed is relatively slow, the large area is fast, and finally the problems of abnormal reading and writing, crosstalk and the like of the array are caused because the deviation of the etching precision far exceeds the range of +/-20A.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor, which can balance etching amount, reduce deviation of the etching amount and finally improve programming and reading and writing of a semiconductor device in etching after a right-angle columnar patterned floating gate layer is formed.
In order to achieve the above object, the present invention provides a method of forming a semiconductor, comprising:
providing a semiconductor;
forming a tunneling oxide layer on the semiconductor;
etching the tunneling oxide layer and the substrate to form a shallow trench isolation structure;
sequentially forming a floating gate layer and a mask layer on the tunneling oxide layer and the shallow trench isolation structure;
etching the mask layer and the floating gate layer to form a groove, a patterned floating gate layer and a patterned mask layer;
filling oxide into the groove by taking the patterned mask layer as a mask;
removing the patterned mask layer;
wet etching the patterned floating gate layer to enable corners of the patterned floating gate layer to be round corners;
dry etching part of the oxide in the groove;
and wet etching the rest part of the oxide in the groove.
Optionally, in the method for forming a semiconductor, the method for forming a semiconductor further includes: and forming an ONO layer on the floating gate and in the groove, wherein the ONO layer covers the side wall of the floating gate and the surface of the oxide in the groove.
Optionally, in the method for forming a semiconductor, the method for forming a semiconductor further includes: and forming a control gate layer on the ONO layer, and etching the control gate layer to form a control gate.
Optionally, in the method for forming a semiconductor, the ONO layer is a combination of silicon oxide-silicon nitride-silicon oxide.
Optionally, in the method for forming a semiconductor, the tunneling oxide layer is made of silicon dioxide.
Optionally, in the semiconductor forming method, the floating gate layer and the control gate layer are made of polysilicon.
Optionally, in the semiconductor forming method, the mask layer is made of silicon nitride.
Optionally, in the method for forming a semiconductor, the patterned floating gate layer is a columnar structure, and a trench is formed between the plurality of columnar structures.
Optionally, in the method for forming a semiconductor, a corner of the patterned floating gate layer is a right angle.
In the method for forming the semiconductor, after the right-angle columnar patterned floating gate layer is formed, the right-angle columnar patterned floating gate layer is etched by using wet etching, so that the angle of the columnar patterned floating gate layer is changed from a right angle to a round angle, then the oxide in the groove is etched by further using dry etching, and finally the residual oxide in the groove is etched by using wet etching, so that the residual oxide reaches the required height.
Drawings
Fig. 1 is a flow chart of a method of forming a semiconductor of an embodiment of the present invention;
FIGS. 2-6 are cross-sectional views of a method of forming a semiconductor in accordance with an embodiment of the present invention;
in the figure: 110-substrate, 120-tunneling oxide layer, 130-shallow trench isolation structure, 140-patterned floating gate layer, 150-patterned mask layer, 160-trench.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In the following, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Referring to fig. 1, the present invention provides a method for forming a semiconductor, including:
s11: providing a semiconductor, and forming a tunneling oxide layer on the semiconductor;
s12: etching the tunneling oxide layer and the substrate to form a shallow trench isolation structure;
s13: sequentially forming a floating gate layer and a mask layer on the tunneling oxide layer and the shallow trench isolation structure;
s14: etching the mask layer and the floating gate layer to form a groove, a patterned floating gate layer and a patterned mask layer;
s15: filling oxide into the groove by taking the patterned mask layer as a mask;
s16: removing the patterned mask layer;
s17: wet etching the patterned floating gate layer to enable corners of the patterned floating gate layer to be round corners;
s18: dry etching part of the oxide in the groove;
s19: and wet etching the rest part of the oxide in the groove.
Specifically, referring to fig. 2, a substrate 100 is provided, and the substrate 100 may be a silicon substrate. Forming a tunnel oxide layer 110 on the substrate 100, etching the tunnel oxide layer 110 and the substrate 100 and filling the oxide to form a shallow trench isolation structure 130.
Referring to fig. 3, a floating gate layer and a mask layer are sequentially formed on the oxide layer 110 and the shallow trench isolation structure 130, the mask layer may be made of silicon nitride, and the floating gate layer may be made of polysilicon. The mask layer and the floating gate layer are etched to form a patterned floating gate layer 140 and a patterned mask layer 150 to form a trench 160, the trench 160 exposes the surface of the shallow trench isolation structure 130, the patterned floating gate layer 140 and the patterned mask layer 150 are formed after etching, the patterned floating gate layer 140 is in a columnar structure, and the angle of the patterned floating gate layer 140 is a right angle. An oxide is deposited in the trench using the patterned masking layer 150 as a mask.
Please refer to fig. 4 to 6 to remove the patterned mask layer 150. The patterned floating gate layer 150 is wet etched to form a pillar-shaped floating gate in a rounded shape. The remaining oxide in the trench 160 continues to be dry etched, and finally the remaining oxide in the trench 160 continues to be etched to a suitable height using a wet etching process. In the prior art, the above steps are completed only by using a wet etching and dry etching process, that is, after a patterned floating gate layer in a columnar shape is formed, the patterned floating gate layer in a right-angle columnar shape is directly etched by using the wet etching, so that the corner of the patterned floating gate layer in the columnar shape is changed from a right angle to a rounded corner, and then the oxide in the trench is etched by further using the dry etching so as to reach the required height. However, due to the influence of the etching precision, the etched size is difficult to grasp, so that the height deviation after etching is too much, and because a plurality of devices can be manufactured on the whole wafer, a plurality of patterned floating gate layers exist, and due to the deviation, the heights of the oxides in the etched grooves are inconsistent, so that the programming and reading and writing of the semiconductor device are influenced. According to the embodiment of the invention, the wet etching and dry etching humidification method etching methods are adopted after the patterned floating gate layer is formed, so that the etching amount can be balanced, the deviation of the etching amount is reduced, and the programming and reading and writing of the semiconductor device are finally improved.
And finally, forming an ONO layer in the floating gate and the groove, wherein the ONO layer covers the side walls of the floating gate and the groove, a groove is formed in the groove, and a control gate layer is continuously formed on the ONO layer, is made of silicon oxide-silicon nitride-silicon oxide and is made of polysilicon. Since the floating gate is formed in the last step in a rounded shape, the area of the control gate corresponding to the floating gate can be increased. Thereby increasing the electrical coupling voltage on the floating gate.
In summary, in the method for forming a semiconductor according to the embodiment of the present invention, after the right-angled cylindrical patterned floating gate layer is formed, the right-angled cylindrical patterned floating gate layer is etched by wet etching, so that the corner of the cylindrical patterned floating gate layer is changed from a right angle to a rounded corner, the oxide in the trench is etched by dry etching, and finally the remaining oxide in the trench is etched by wet etching, so that the remaining oxide reaches a required height.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (9)
1. A method of forming a semiconductor, comprising:
providing a semiconductor;
forming a tunneling oxide layer on the semiconductor;
etching the tunneling oxide layer and the substrate to form a shallow trench isolation structure;
sequentially forming a floating gate layer and a mask layer on the tunneling oxide layer and the shallow trench isolation structure;
etching the mask layer and the floating gate layer to form a groove, a patterned floating gate layer and a patterned mask layer;
filling oxide into the groove by taking the patterned mask layer as a mask;
removing the patterned mask layer;
wet etching the patterned floating gate layer to enable corners of the patterned floating gate layer to be round corners;
dry etching part of the oxide in the groove;
and wet etching the rest part of the oxide in the groove.
2. The method of forming a semiconductor of claim 1, further comprising: and forming an ONO layer on the floating gate and in the groove, wherein the ONO layer covers the side wall of the floating gate and the surface of the oxide in the groove.
3. The method for forming a semiconductor according to claim 2, further comprising: and forming a control gate layer on the ONO layer, and etching the control gate layer to form a control gate.
4. The method of claim 2, wherein the ONO layer is a combination of silicon oxide-silicon nitride-silicon oxide.
5. The method of claim 1, wherein the tunneling oxide layer is formed of silicon dioxide.
6. The method for forming a semiconductor according to claim 3, wherein a material of the floating gate layer and the control gate layer is polysilicon.
7. The method for forming a semiconductor according to claim 1, wherein a material of the mask layer is silicon nitride.
8. The method of claim 1, wherein the patterned floating gate layer is a pillar structure, and a trench is formed between the pillar structures.
9. The method of claim 1, wherein corners of the patterned floating gate layer are right angles.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911183899.4A CN110854120A (en) | 2019-11-27 | 2019-11-27 | Method for forming semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911183899.4A CN110854120A (en) | 2019-11-27 | 2019-11-27 | Method for forming semiconductor |
Publications (1)
| Publication Number | Publication Date |
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| CN110854120A true CN110854120A (en) | 2020-02-28 |
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| CN201911183899.4A Pending CN110854120A (en) | 2019-11-27 | 2019-11-27 | Method for forming semiconductor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111326519A (en) * | 2020-03-10 | 2020-06-23 | 上海华力微电子有限公司 | Method for forming semiconductor |
| CN113299597A (en) * | 2021-06-29 | 2021-08-24 | 上海华力微电子有限公司 | Method for forming shallow trench isolation structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050255654A1 (en) * | 2004-05-11 | 2005-11-17 | Won-Jun Lee | Methods of forming non-volatile memory devices having floating gate electrodes |
| CN104752363A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of flash memory |
| CN105097681A (en) * | 2014-05-06 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof, and electronic device |
-
2019
- 2019-11-27 CN CN201911183899.4A patent/CN110854120A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050255654A1 (en) * | 2004-05-11 | 2005-11-17 | Won-Jun Lee | Methods of forming non-volatile memory devices having floating gate electrodes |
| CN104752363A (en) * | 2013-12-31 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Forming method of flash memory |
| CN105097681A (en) * | 2014-05-06 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, preparation method thereof, and electronic device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111326519A (en) * | 2020-03-10 | 2020-06-23 | 上海华力微电子有限公司 | Method for forming semiconductor |
| CN111326519B (en) * | 2020-03-10 | 2024-02-02 | 上海华力微电子有限公司 | Method for forming semiconductor |
| CN113299597A (en) * | 2021-06-29 | 2021-08-24 | 上海华力微电子有限公司 | Method for forming shallow trench isolation structure |
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Application publication date: 20200228 |