TW201611273A - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns as an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate. A semiconductor device is also provided.

Description

Semiconductor device and method of manufacturing same

A representative embodiment of the inventive concept relates to a semiconductor device and a method of fabricating the same. In particular, it relates to a fin field effect transistor and a method of manufacturing the same.

In order to realize a highly integrated semiconductor device, it is necessary to form a fine pattern. For example, each pattern should be formed to have as small an area or footprint as possible so that more and more devices can be provided per given area. In particular, the pattern should be formed in such a manner as to minimize the pattern pitch or minimize the width of the pattern and the sum of the gaps between the neighbors of the pattern. However, such patterns are typically formed using photolithography. Since the design rules of semiconductor devices have become substantially smaller, photolithography has reached its limit in terms of resolution that can be achieved. Therefore, as the pattern pitch of the semiconductor device becomes finer to satisfy a smaller design rule, it becomes more and more difficult to form a pattern.

In accordance with the inventive concept, a representative embodiment of a method of fabricating a semiconductor device is provided, the method comprising: providing a substrate across a first region, a second region, and a third region of the device; forming a first preliminary active pattern on the substrate And a second preliminary active pattern, such that the first preliminary active pattern and the second preliminary active pattern are protruded from the substrate, and the first preliminary active pattern extends from the first region to the third region to overlap the substrate in the third region, and a preliminary active pattern extending from the second region to the third region to also overlap the substrate in the third region; forming a mask pattern on the first and second regions but not on the substrate in the third region, thereby exposing the first a substrate in the three regions; performing a first etching process, including using the mask pattern as an etch mask to etch the first preliminary active pattern and the second preliminary active pattern to respectively from the first preliminary active pattern and the second preliminary active pattern Forming a first active pattern and a second active pattern; and forming a first gate structure crossing the first active pattern and forming a second gate crossing the second active pattern Structure. The first active patterns are formed to extend longitudinally in the first direction and to be spaced apart from each other in a second direction that intersects the first direction. The second active patterns are formed to extend in the first direction and to be spaced apart from each other in the second direction. The first direction is one direction extending across the first zone, the second zone, and the third zone. Further, in the second direction, the distance between the neighbors in the first active pattern is different from the distance between the neighbors in the second active pattern.

According to the inventive concept, a representative embodiment of a method of fabricating a semiconductor device is also provided, the method comprising: patterning a substrate to form a first trench defining a first preliminary active pattern and a second preliminary active pattern, a first preliminary The active patterns extend longitudinally in the first direction and are spaced apart from each other in a second direction crossing the first direction, the second preliminary active pattern extending longitudinally in the first direction and spaced apart from the first preliminary active pattern in the first direction Opening and spaced apart from each other in the second direction; forming a mask pattern exposing the first preliminary active pattern and the end portion of the second preliminary active pattern on the substrate; performing an etching process, wherein the mask pattern is used as an etch mask, The process removes the first preliminary active pattern and the end portions of the second preliminary active pattern and respectively forms a first active pattern and a second active pattern therefrom; and forms a first gate crossing the first active pattern on the substrate a structure and a second gate structure crossing the second active pattern. Also, the active pattern is formed such that the distance between the neighbors in the first preliminary active pattern in the second direction is different from the distance between the neighbors in the second preliminary active pattern in the second direction. Furthermore, the end portions of the first preliminary active pattern are collectively spaced apart from the end portions of the second preliminary active pattern in the first direction. Furthermore, the etching process forms a second trench having a bottom disposed at a level lower than the bottom of the first trench, and such that the width of the second trench in the first direction is equal to the set of all the first active patterns The distance in the first direction from the set of all second active patterns.

According to the inventive concept, there is also provided a representative embodiment of a method of fabricating a semiconductor device, the method comprising: forming a sacrificial layer on a substrate; performing a photolithography process to form a first photoresist pattern on the sacrificial layer and a patterned photoresist layer of a two photoresist pattern, wherein at least one of the first photoresist patterns extends from the memory cell region to the third region and at least one of the second photoresist patterns extends from the peripheral circuit region to a third region; the patterned photoresist layer is used as an etch mask to etch the sacrificial layer to form a patterned sacrificial material layer in the memory cell region, the peripheral circuit region, and the third region; forming a sacrifice along the patterning a sidewall surface spacer of a side surface of the material layer; removing the patterned sacrificial material layer and using the spacer as an etch mask to etch the substrate to pattern the substrate in the memory cell region, the peripheral circuit region, and the third region; Forming a portion of the substrate patterned in both the memory cell region and the peripheral circuit region on the substrate to expose the portion of the substrate patterned in the third region; using the mask as an etch Masking to etch the substrate in the third region to remove portions of the patterned substrate in the third region, and thereby forming a plurality of first active regions of the substrate in the memory cell region and forming a substrate in the peripheral circuit region a plurality of second active regions; forming a first gate extending across the first active region and forming a second gate extending across the second active region.

According to the inventive concept, there is also provided a representative embodiment of a semiconductor device including: a substrate extending in a first region, a second region, and a third region between the first region and the second region; a first active region of the substrate extending upward, extending in a first direction crossing the first to third regions, and spaced apart from each other in a second direction crossing the first direction; a second active area that is convex upwardly, extends in the first direction, and is spaced apart from each other in the second direction, and a distance between the neighbors in the first active pattern is different from that in the second direction a distance between adjacent ones of the two active patterns; a first gate structure crossing the first active pattern; and a second gate structure crossing the second active pattern. The third zone is defined by a groove in the substrate between the first zone and the second zone. The sidewall surface of the first active pattern is aligned along the second direction at a boundary between the first region and the third region, and the sidewall surface of the second active pattern is along the second direction in the second region and the third region Alignment between the boundaries.

Representative embodiments of the inventive concept will now be described more fully hereinafter with reference to the accompanying drawings. However, the representative embodiments of the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. The embodiments are provided so that the disclosure will be thorough and complete, and The concept of a sexual embodiment is fully conveyed to those of ordinary skill in the art. In the drawings, the layers and the thickness of the regions are enlarged for clarity. Like reference numerals indicate similar elements in the drawings, and thus descriptions thereof will be omitted.

It will be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or the intervening element can be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, the intervening element is absent. Similar numbers always indicate similar components. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (for example, "between" and "directly between", "nearby" to "directly adjacent", "in "Up" to "directly on...").

It will be understood that, although the terms "first," "second," etc. may be used to describe various elements, components, regions, layers, and / or sections, such elements, components, regions, layers and/or regions Segments should not be limited by these terms. The terms are used to distinguish one element, component, region, layer, The first element, component, region, layer or section discussed below may be referred to as a second element, component, region, layer or section, without departing from the teachings of the representative embodiments.

For ease of description, spatially relative terms such as "under", "below", "lower", "above", "upper", and the like may be used herein to describe The relationship of one element or feature illustrated in the figures to another element or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations in addition to the orientation depicted in the figures when the device is used or operated. For example, elements that are described as "under other elements or features" or "under other elements or features" will be "above". Therefore, the exemplary term "below" can encompass both orientations "above" and "below". The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments, and is not intended to As used herein, the sing " It will be further understood that the terms "comprises" and "comprises" and "includes", when used herein, are used to refer to the <RTI ID=0.0> </ RTI> </ RTI> <RTIgt; The presence or addition of integers, steps, operations, components, components, and/or groups thereof.

Representative embodiments of the inventive concept are described herein with reference to cross-sectional illustrations of schematic illustrations of the idealized embodiments (and intermediate structures) of representative embodiments. Thus, variations in the shapes of the illustrations are contemplated as a result of, for example, manufacturing techniques and/or tolerances. Thus, a representative embodiment of the inventive concept should not be construed as limited to the particular region shapes described herein, but rather to include a shape variation resulting from, for example, manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration on its edges rather than a binary change from the implanted region to the non-implanted region. Likewise, a buried region formed by implantation can cause some implantation in the region between the buried region and the surface where the implantation takes place. The area illustrated in the figures is, therefore, in the nature of the embodiments, and is not intended to limit the scope of the representative embodiments.

As understood by the entities of the present invention, devices in accordance with various embodiments described herein and methods of forming devices can be embodied in a microelectronic device such as an integrated circuit, wherein a plurality of devices in accordance with various embodiments described herein Integrated into the same microelectronic device. Thus, the cross-sectional views illustrated herein can be replicated in two different directions in a microelectronic device without the need for orthogonality. Accordingly, a plan view of a microelectronic device embodying devices in accordance with various embodiments described herein can include multiple devices in an array and/or two-dimensional pattern based on the functionality of the microelectronic device.

Depending on the functionality of the microelectronic device, devices in accordance with various embodiments described herein may be interspersed among other devices. Moreover, microelectronic devices in accordance with various embodiments described herein can be replicated in a third party that can be orthogonal to two different directions to provide a three-dimensional integrated circuit.

Accordingly, the cross-sectional views illustrated herein provide support for a plurality of devices in accordance with various embodiments described herein in two different directions in plan view and/or in three different directions in a perspective view. . For example, when a single active region is illustrated in a cross-sectional view of a device/structure, the device/structure may include multiple active regions and a transistor structure thereon (as required by the state, or as a memory cell structure, gate structure) Etc.), as will be illustrated by the plan view of the device/structure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning meaning meaning It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meaning consistent with their meaning in the context of the related art, and will not be interpreted in terms of idealized or overly formalized unless This is clearly defined in this way. For example, the term "pattern" may refer to a single feature or element formed by a patterning process as will be apparent from the context or may refer to the entire feature or series of elements. Also, the term "size" will be understood broadly to refer to the surface area or footprint of a particular feature or element.

A representative embodiment of a method of fabricating a semiconductor device in accordance with the inventive concept will now be described in detail with reference to FIGS. 1A through 8B.

Referring first to Figures 1A and 1 B, a substrate 100 can be provided that spans the first through third regions R1 through R3 of the device. The first zone R1 may be spaced apart from the second zone R2 and the third zone R3 may be interposed between the first zone R1 and the second zone R2. The substrate 100 may be formed of or comprise a semiconductor material. For example, the substrate 100 can be a semiconductor wafer or include an epitaxial layer. As an example, substrate 100 can comprise a single crystal, polycrystalline or amorphous layer of tantalum, niobium or tantalum-ruthenium.

In an exemplary embodiment, the first region R1 may be a cell array region that provides a memory cell transistor for storing data. For example, SRAM (Static With Access Memory) cells, each of which contains six or eight transistors, may be provided in the first region R1. However, representative embodiments of the inventive concept are not limited thereto. The second region R2 can be part of a peripheral circuit region that provides peripheral circuitry. For example, a row decoder or sense amplifier can be provided in the second region R2. A peripheral circuit transistor electrically connected to the memory cell transistor of the first region R1 may be formed in the second region R2. The third region R3 may serve as a buffer that separates the transistors of the first region R1 and the second region R2 from each other, and when operating the transistors of the first region R1 and the second region R2, due to the third region R3, It is possible to prevent the transistors of the first region R1 and the second region R2 from disturbing or disturbing each other.

The hard mask 125 and the sacrificial layer 130 may be sequentially formed on the substrate 100. In an exemplary embodiment, the hard mask 125 can include a lower mask layer 110 on the substrate 100 and an upper mask layer 120 on the lower mask layer 110. The lower mask layer 110 may be formed of a material having an etch selectivity with respect to the substrate 100. As an example, the lower mask layer 110 may include at least one of cerium oxide, cerium nitride, and cerium oxynitride. The upper mask layer 120 may be formed of a material having an etch selectivity with respect to the lower mask layer 110. As an example, the upper mask layer 120 may be formed of polycrystalline germanium or comprise polycrystalline germanium. The sacrificial layer 130 may be formed of a material having an etch selectivity with respect to the upper mask layer 120. As an example, the sacrificial layer 130 may be formed of or comprise a spin-on hard mask (SOH) layer or an amorphous carbon layer (ACL). In the present embodiment, although the hard mask 125 is illustrated as a stack of two layers, a representative embodiment of the inventive concept may not be limited thereto. For example, in other representative embodiments, the hard mask 125 can include three layers. Although not shown, an etch stop layer may be formed on the sacrificial layer 130 for interposing between the upper mask layer 120 and the sacrificial layer 130. The etch stop layer may be formed of, for example, a SiON layer or a SiON layer.

A photolithography process can be performed to form a photoresist pattern on the sacrificial layer 130. In a representative embodiment, the photoresist pattern may include a first photoresist pattern 142 formed in the first region R1 and a second photoresist pattern 144 formed in the second region R2. The formation of the first photoresist pattern 142 and the second photoresist pattern 144 may include coating the sacrificial layer 130 with a resist material to form a photoresist layer and performing an exposure and development process on the photoresist layer. Although not shown, an anti-reflective layer (not shown) may be formed on the sacrificial layer 130 before the photoresist layer is formed. The anti-reflective layer can include, for example, an organic anti-reflective coating (ARC). The first photoresist pattern 142 and the second photoresist pattern 144 may be formed substantially at the same time.

In an exemplary embodiment, the first photoresist pattern 142 and the second photoresist pattern 144 may be repeatedly disposed on the substrate 100 to have a line and gap configuration. For example, each of the first photoresist patterns 142 may be a line pattern having a first width W1 that extends parallel to the first direction D1 and is measured in the second direction D2. Here, the first direction D1 and the second direction D2 are not parallel to each other (for example, may be perpendicular to each other). Further, the first photoresist patterns 142 may be spaced apart from each other by a distance greater than the first width W1 in the second direction D2. Hereinafter, the second width W2 will represent the distance between the first photoresist patterns 142. Similarly, each of the second photoresist patterns 144 may be a line pattern having a third width W3 extending parallel to the first direction D1 and measured in the second direction D2. The second photoresist patterns 144 may be spaced apart from each other by a distance greater than the third width W3 in the second direction D2. Hereinafter, the fourth width W4 will represent the distance between the second photoresist patterns 144. Here, the first width W1 may be different from the third width W3 (eg, W1 < W3), and the second width W2 may be different from the fourth width W4 (eg, W2 < W4). In other words, the first photoresist pattern 142 may be formed to have a pitch different from that of the second photoresist pattern 144. Although the first photoresist pattern 142 and the second photoresist pattern 144 are illustrated as having a uniform pitch, representative embodiments of the inventive concept may not be limited thereto.

According to a representative embodiment of the inventive concept, the distance dp between the first photoresist pattern 142 and the second photoresist pattern 144 may be smaller than the exposure process for forming the first photoresist pattern 142 and the second photoresist pattern 144. The wavelength (λ) of the light used in (i.e., dp < λ). In this case, due to the difficulty in controlling an optical phenomenon such as an optical proximity effect, the end portions of the first photoresist pattern 142 and the second photoresist pattern 144 may not have the precise shape illustrated in FIG. 1A, that is, The shape is different from the main portions of the photoresist patterns 142 and 144.

In some cases of the representative embodiment, the first photoresist pattern 142 and the second photoresist pattern 144 are formed to be spaced apart from each other in the first direction D1. For example, the first photoresist pattern 142 and the second photoresist pattern 144 may have end portions in the third region R3, and the pair of opposite end portions of the first photoresist pattern 142 and the second photoresist pattern 144 may be The distance dp is spaced apart from each other in the first direction D1. However, due to the optical phenomenon mentioned above, the end portion of the first photoresist pattern 142 may have a width greater than or less than the first width W1, and the end portion of the second photoresist pattern 144 may have greater or lesser The width of the third width W3. In addition, the distance between the first photoresist pattern 142 and the second photoresist pattern 144 may not be uniform. In this case, the distance dp may be defined as a maximum distance value between the first photoresist pattern 142 adjacent to each other in the first direction D1 and the end portion of the second photoresist pattern 144 in the first direction D1.

In other cases of the representative embodiment, as illustrated in FIGS. 9A and 9B, the first photoresist pattern 142 and the second photoresist pattern 144 are connected to each other. In particular, when the first photoresist pattern 142 and the second photoresist pattern 144 having different pitches are formed adjacent to each other, an optical proximity effect may occur. As a result, the connection photoresist pattern 146 may be formed between the first photoresist pattern 142 and the end portions of the second photoresist pattern 144 to connect the first photoresist pattern 142 and the second photoresist pattern 144 to each other. That is, the optical proximity effect may cause an unintended connection between the end portions of the first photoresist pattern 142 and the second photoresist pattern 144, and the unintended connection pattern may constitute the connection photoresist pattern 146. Moreover, although the connection resist pattern 146 is illustrated as abutting the other (ie, all of the first photoresist pattern 142 and the second photoresist pattern 144) to form a single body with this, the connection photoresist pattern 146 may take other forms. . For example, each of the connection photoresist patterns 146 may connect only one of the first photoresist patterns 142 and each of the second photoresist patterns 144 to each other.

The shape of the sacrificial pattern, the spacer, the pattern of the hard mask, and the shape of the preliminary active pattern to be formed in the subsequent process may depend on the shape of the photoresist pattern, but according to a representative embodiment of the inventive concept, the shape of the photoresist pattern may be Does not bring the final shape difference of the active pattern. Further, the manufacturing steps to be performed to form the active pattern may be performed in the same manner without depending on the shape of the photoresist pattern. Hereinafter, for the sake of simplicity, the following description will refer to an example of the present embodiment in which the first and second photoresist patterns have the shapes illustrated in FIGS. 1A and 1B.

Referring to FIGS. 2A and 2B, the sacrificial layer 130 exposed by the first photoresist pattern 142 and the second photoresist pattern 144 may be patterned to form a first sacrificial pattern 132 and a second sacrificial pattern 134. Patterning of the sacrificial layer 130 may be performed using, for example, an anisotropic dry etch process in which the first photoresist pattern 142 and the second photoresist pattern 144 are used as an etch mask. Therefore, when viewed in a plan view, the first sacrificial patterns 132 may be formed to have shapes substantially the same as the shapes of the first photoresist patterns 142 and the second sacrificial patterns 134 may be formed to have substantially the same as the second The shapes of the shapes of the photoresist patterns 144. In other words, similar to the case of the first photoresist pattern 142 and the second photoresist pattern 144, the first sacrificial pattern 132 and the second sacrificial pattern 134 may be repeatedly disposed on the substrate 100 to have a line and gap configuration. The first sacrificial patterns 132 may be formed to have a width and an interval or a pitch substantially equal to the widths and intervals or pitches of the corresponding first photoresist patterns 142. Similarly, the second sacrificial patterns 134 may be formed to have a width and an interval or a pitch substantially equal to the widths and intervals or pitches of the corresponding second photoresist patterns 144. That is, the first sacrificial pattern 132 may be formed to have a first width W1 and a pair of adjacent first sacrificial patterns 132 may be spaced apart from each other by a second width W2. The second sacrificial pattern 134 may be formed to have a third width W3 and a pair of adjacent second sacrificial patterns 134 may be spaced apart from each other by a fourth width W4.

Subsequently, a first spacer 152 may be formed to cover a sidewall surface of the first sacrificial pattern 132 and a second spacer 154 may be formed to cover a sidewall surface of the second sacrificial pattern 134. In an exemplary embodiment, the forming of the sidewall surface spacers (ie, the first spacers 152 and the second spacers 154) may include forming a spacer layer on the substrate 100 to conformally cover the first sacrificial patterns 132 and the first The sacrificial pattern 134 is patterned and an anisotropic etch process (eg, without any other mask pattern) is performed on the spacer layer to expose the upper mask layer 120. Therefore, the first spacer 152 and the second spacer 154 may be formed to surround the first sacrificial pattern 132 and the second sacrificial pattern 134 as a whole. The separator layer may be formed of, for example, cerium oxide or contain cerium oxide. The spacer layer can be formed by an atomic layer deposition (ALD) process. When measured in the second direction D2, the distance between the neighbors in the first spacer 152 may be defined as the fifth width W5 and the distance between the neighbors in the second spacer 154 may be defined as the Six width W6. That is, the fifth width W5 may refer to the shortest distance between the side wall surfaces of the first spacers 152 facing each other in the second direction D2, and the sixth width W6 may refer to the second surface facing each other in the second direction D2 The shortest distance between the sidewall surfaces of the spacers 154. In an example of a representative embodiment, the fifth width W5 is substantially equal to the first width W1 and the sixth width W6 is substantially equal to the third width W3. Therefore, the fifth width W5 may depend on the first width W1, the second width W2, and the thickness of the separation layer. Similarly, the sixth width W6 may depend on the third width W3, the fourth width W4, and the thickness of the separation layer.

Referring to FIGS. 3A and 3B, the first sacrificial pattern 132 and the second sacrificial pattern 134 may be removed. In an exemplary embodiment, the first sacrificial pattern 132 and the second sacrificial pattern 134 may be removed by, for example, an ashing and/or stripping process.

Subsequently, the upper mask layer 120 may be etched by an etching process in which the first spacer 152 and the second spacer 154 are used as an etch mask, and as a result, the first upper mask pattern 122 and the second upper mask pattern 124 may be Formed on the lower mask layer 110. The first upper mask pattern 122 and the second upper mask pattern 124 may be respectively formed into shapes having substantially the same shape as the first spacer 152 and the second spacer 154 when viewed in a plan view. Meanwhile, although FIG. 3A illustrates only one of the end portions of each of the first upper mask pattern 122 and the second upper mask pattern 124, the opposite end portions may be formed to have substantially the same as illustrated The shape of the person. This case means that each of the first upper mask patterns 122 may have a closed loop shape including a pair of line patterns elongated in the second direction D2 and connected to each other. In an exemplary embodiment, the distance between the inner sidewall surfaces of each of the first upper shroud patterns 122 may be substantially the same as the first width W1 of a corresponding one of the first sacrificial patterns 132. Further, the distance between the first upper mask patterns 122 adjacent to each other in the second direction D2 may be substantially the same as the fifth width W5.

Similarly, each of the second upper mask patterns 124 may include a pair of line patterns elongated and connected to each other in the second direction D2 and thereby having a closed loop shape. In an example of a representative embodiment, the distance between the inner sidewall surfaces of each of the second upper shroud patterns 124 may be substantially the same as the third width W3 of a corresponding one of the second sacrificial patterns 134. Further, the distance between the second upper mask patterns 124 adjacent to each other in the second direction D2 may be substantially the same as the sixth width W6. In some embodiments, an etch process for forming the first upper mask pattern 122 and the second upper mask pattern 124 may leave a first on the first upper mask pattern 122 and the second upper mask pattern 124. Spacer 152 and second spacer 154.

Referring to FIG. 4A and FIG. 4B, the lower mask layer 110 may be etched by an etching process to form a first lower mask pattern 112 and a second lower mask pattern 114, in which the first upper mask pattern 122 and The second upper mask pattern 124 serves as an etch mask. The first lower mask pattern 112 and the second lower mask pattern 114 may be respectively formed to have shapes substantially the same as the first upper mask pattern 122 and the second upper mask pattern 124 when viewed in a plan view. The first upper mask pattern 122 and the first lower mask pattern 112 may constitute the first hard mask pattern 127 and the second upper mask pattern 124 and the second lower mask pattern 114 may constitute the second hard mask pattern 129 . In an exemplary embodiment, the first spacer 152 and the second spacer 154 may be removed during or prior to an etching process for forming the first lower mask pattern 112 and the second lower mask pattern 114.

Referring to FIGS. 5A and 5B, an upper portion of the substrate 100 may be etched by an etching process to form a first trench T1 defining a first preliminary active pattern AP1a and a second preliminary active pattern AP2a, the first hard mask in the process. The cover pattern 127 and the second hard mask pattern 129 are used as an etch mask. The first preliminary active pattern AP1a may be formed in the first region R1, and the second preliminary active pattern AP2a may be formed in the second region R2. The first preliminary active pattern AP1a and the second preliminary active pattern AP2a are convex upward from the substrate surface 100. The first upper mask pattern 122 and the second upper mask pattern 124 and/or the first lower mask pattern 112 and the second lower portion may be removed after the first preliminary active pattern AP1a and the second preliminary active pattern AP2a have been formed. Any remaining portion of the mask pattern 114.

The first preliminary active pattern AP1a may have a shape substantially the same as the first upper mask pattern 122 and the first lower mask pattern 112 when viewed in a plan view. For example, each of the first preliminary active patterns AP1a may include a pair of first line patterns L1 extending parallel to the first direction D1 and a first connection pattern C1 connecting the ends of the first line patterns L1 to each other. The first line pattern L1 and a portion of the first connection pattern C1 may be located in the third region R3. The distance between the pair of first line patterns L1 may be substantially equal to the first width W1 of the first sacrificial patterns 132. Further, the distance between the first preliminary active patterns AP1a adjacent to each other in the second direction D2 may be substantially equal to the fifth width W5. In an example of a representative embodiment, the first width W1 is substantially equal to the fifth width W5.

Similarly, the second preliminary active pattern AP2a may have a shape substantially the same as the second upper mask pattern 124 and the second lower mask pattern 114 when viewed in a plan view. For example, each of the second preliminary active patterns AP2a may include a pair of second line patterns L2 extending parallel to the first direction D1 and a second connection pattern C2 connecting the ends of the second line patterns L2 to each other. A portion of the second line pattern L2 and the second connection pattern C2 may be located in the third region R3. The distance between the pair of second line patterns L2 may be substantially equal to the third width W3 of the second sacrificial patterns 132. Further, the distance between the second preliminary active patterns AP2a adjacent to each other in the second direction D2 may be substantially equal to the sixth width W6. In an example of a representative embodiment, the third width W3 is substantially equal to the sixth width W6.

Referring to FIGS. 6A and 6B, a first mask pattern 160 may be formed on the substrate 100. The first mask pattern 160 may be formed to expose the entire area of the third region R3. In other words, the first mask pattern 160 does not overlap the third region R3 when viewed in a plan view. Therefore, in this example, the first mask pattern 160 may be formed to expose a portion of the first preliminary active pattern AP1a (eg, a portion of the first line pattern L1 and the first connection pattern C1) and a second preliminary active pattern AP2a A portion (for example, a portion of the second line pattern L2 and the second connection pattern C2). The first mask pattern 160 may be formed of, for example, an SOH material or comprise an SOH material. The first mask pattern 160 may also expose the opposite end portions of the first preliminary active pattern AP1a and the second preliminary active pattern AP2a (not shown).

Referring to FIGS. 7A and 7B, an etching process using the first mask pattern 160 as an etch mask may be performed to form the second trench T2. The second trench T2 may be formed to have a depth greater than a depth of the first trench T1. In other words, the second trench T2 may have a bottom surface lower than the bottom surface of the first trench T1. In some embodiments, an etching process may be performed to remove portions of the first preliminary active pattern AP1a in the third region R3 (eg, portions of the first line pattern L1 and the first connection pattern C1) and a second preliminary A portion of the active pattern AP2a (eg, a portion of the second line pattern L2 and a second connection pattern C2). As a result, the first active pattern AP1b and the second active pattern AP2b are formed by the first preliminary active pattern AP1a and the second preliminary active pattern AP2a, respectively. Hereinafter, a series of steps for removing portions of the first preliminary active pattern AP1a and the second preliminary active pattern AP2a will be referred to as a "fin cutting process."

The first active patterns AP1b may each have a linear structure extending longitudinally in the first direction D1 and may be spaced apart from each other in the second direction D2. Similarly, the second active patterns AP2b may each have a linear structure extending longitudinally in the first direction D1 and may be spaced apart from each other in the second direction D2. When measured in the second direction D2, the distance between the first active patterns AP1b may correspond to the first width W1 and the fifth width W5 of the first preliminary active pattern AP1a. In a case where the first width W1 and the fifth width W5 are substantially equal to each other, the distance between the first active patterns AP1b in the second direction D2 may be uniform (for example, the first distance d1). When measured in the second direction D2, the distance between the second active patterns AP2b may correspond to the third width W3 and the sixth width W6 of the second preliminary active pattern AP2a. In a situation where the third width W3 and the sixth width W6 are substantially equal to each other, the distance between the second active patterns AP2b in the second direction D2 may be uniform (eg, the second distance d2). In the present embodiment, the first distance d1 is different from the second distance d2. For example, the second distance d2 may be greater than the first distance d1.

The first mask pattern 160 may be removed after the second trench T2 has been formed. The first mask pattern 160 can be removed by, for example, an ashing and/or stripping process. In some examples of representative embodiments, an unnecessary portion of the first active pattern AP1b (hereinafter the first unnecessary portion AP1b') is removed. For example, the removal of the first unnecessary portion AP1b' may include forming a mask pattern (not shown) exposing the first unnecessary portion AP1b' and using the mask pattern as an etch mask to etch the first unnecessary Part of AP1b'.

Next, the device isolation pattern ST may be formed in the first trench T1 and the second trench T2. For example, the formation of the device isolation pattern ST may include forming a device isolation layer on the substrate 100 to fill the first trench T1 and the second trench T2 and planarizing the device isolation layer to expose the substrate 100. The upper portion of the device isolation pattern ST may be etched to expose the upper portions of the first active pattern AP1b and the second active pattern AP2b. Hereinafter, the exposed upper portion of the first active pattern AP1b and the second active pattern AP2b (that is, the upper portion of the first active pattern AP1b and the second active pattern AP2b that are convex upward with respect to the device isolation pattern ST) will They are called "first active fin AF1 and second active fin AF2", respectively.

Due to the process described above, the first active pattern AP1b may have an end surface aligned along the second direction D2 at the boundary of the first region R1 and the third region R3. Also, the top surface of the substrate 100 in the first region R1 may be in contact with the sidewall surface of the substrate defining the side of the second trench T2 at the boundary of the first region R1 and the third region R3. Similarly, the second active pattern AP2b may have an end surface aligned along the second direction D2 at the boundary of the second region R2 and the third region R3. Also, the top surface of the substrate 100 in the second region R2 may be in contact with the sidewall surface of the substrate defining the side of the second trench T2 at the boundary between the second region R2 and the third region R3. In other words, the width of the third region R3 (the size of the third region R3 in the first direction D1) may be the distance 'dap' between the opposite end surfaces of the first active pattern AP1b and the second active pattern AP2b. Here, the distance dap may be substantially equal to the width of the second trench T2. In other words, the width of the second trench T2 may be equal to the width of the third region R3. Further, although the second trench T2 is illustrated as having a vertical side in the drawing, the second trench T2 may have a profile that gradually becomes downward. Therefore, the maximum width of the second trench T2 can be regarded as the width of the second trench T2. The third region R3 can be designed to be as narrow as possible while still substantially preventing electrical interference or disturbance between the transistors (i.e., FETs) of the first region R1 and the second region R2.

More specifically, in the case where the first active pattern and the second active pattern of the semiconductor device have different pitches from each other, due to the resolution limitation of the photolithography process for forming the active pattern, in general, An active pattern and a second active pattern will typically have to be spaced apart from each other by a distance greater than that required to provide a reliable device. This situation leads to additional consumption of wafer area overhead. In contrast, in a representative embodiment according to the inventive concept, groups of the first active pattern AP1b and the second active pattern AP2b may be formed as close as possible to each other without being limited by the method for forming a pattern. The resolution that can be achieved in the photolithography process used. Although pattern defects in the first and second photoresist patterns (for example, formation of the connection patterns 146 as described with reference to FIGS. 9A and 9B) may be brought in the first preliminary active pattern AP1a and the second preliminary active pattern AP2a Similar or partial defects, but such defects of the first preliminary active pattern AP1a and the second preliminary active pattern AP2a may be removed by the fin cutting process of FIGS. 7A and 7B. As a result, it is possible to form transistors in the first region R1 and the second region R2, which will operate without electrical interference therebetween while minimizing separation of the transistors formed in the first region R1 and formation The area of the third region R3 of the transistor in the second region R2. In other words, it is possible to provide transistors at different pitches in a minimum amount of area of the wafer.

8A and 8B illustrate the steps of completing the formation of a transistor in the first region R1 and the second region R2.

Referring to the figures, the first gate structure GS1 and the second gate structure GS2 may be formed on the substrate 100 to intersect the first active pattern AP1b and the second active pattern AP2b, respectively. Each of the first gate structures GS1 may include a first gate dielectric pattern GD1 and a first gate electrode GE1 sequentially stacked on the substrate 100. Each of the second gate structures GS2 may include a second gate dielectric pattern GD2 and a second gate electrode GE2 sequentially stacked on the substrate 100. In an example of a representative embodiment, the forming of the first gate structure GS1 and the second gate structure GS2 includes forming a first interlayer insulating layer 170 having an opening and sequentially forming a gate dielectric layer and a gate in the opening Electrode layer. In another example of the representative embodiment, the forming of the first gate structure GS1 and the second gate structure GS2 includes sequentially forming a gate dielectric layer and a gate electrode layer on the substrate 100 and then patterning the gate Dielectric layer and gate electrode layer. In this example, the first interlayer insulating layer 170 may be formed after the first gate structure GS1 and the second gate structure GS2 have been formed. The first gate dielectric pattern GD1 and the second gate dielectric pattern GD2 may be at least one of a hafnium oxide layer, a hafnium oxynitride layer, and a high-k dielectric material having a dielectric constant higher than a dielectric constant of the hafnium oxide layer. The material is formed or contained. The first gate electrode GE1 and the second gate electrode GE2 may include at least one material selected from the group consisting of: a doped semiconductor material, a metal, and a conductive metal nitride. The first interlayer insulating layer 170 may include, for example, at least one of a hafnium oxide layer, a tantalum nitride layer, and a hafnium oxynitride layer. Although not shown, a gate spacer may be formed on both sides of each of the first gate structure GS1 and the second gate structure GS2. Also, it should be noted that during the formation of the first gate structure GS1 and the second gate structure GS2, the dummy pattern (that is, the dummy gate structure) does not have to be formed in the third region R3.

a first source/drain region may be formed in the first active pattern AP1b and at both sides of each of the first gate structures GS1, and a second source/drain region may be formed in the second active pattern AP2b and At both sides of each second gate structure GS2. The first gate structure GS1 and the first source/drain regions may constitute a memory cell transistor of the cell array described with reference to FIGS. 1A and 1B. The region of the first effective fin AF1 disposed under the first gate structure GS1 may serve as a channel region of the memory cell transistor. Similarly, the second gate structure GS2 and the second source/drain region may constitute a peripheral circuit transistor of the peripheral circuit described with reference to FIGS. 1A and 1B. The region of the second effective fin AF2 disposed under the second gate structure GS2 may serve as a channel region of the peripheral circuit transistor.

Subsequently, a first contact CT1 and a second contact CT2 may be formed to apply voltages to the first and second source/drain regions, respectively. The first contact CT1 and the second contact CT2 may be formed to penetrate the second interlayer insulating layer 180 that may be provided to cover the top surfaces of the first gate structure GS1 and the second gate structure GS2. The second interlayer insulating layer 180 may include, for example, at least one of a hafnium oxide layer, a tantalum nitride layer, and a hafnium oxynitride layer.

In the apparatus of FIGS. 8A and 8B formed by a representative embodiment, as mentioned above, the first region R1 may be a cell array region in which a plurality of memory cell transistors for storing data are disposed. For example, SRAM cells, each of which contains six or eight transistors, are disposed in the first zone R1. The second zone R2 can be part of a peripheral circuit zone in which the peripheral circuitry is placed. For example, a row decoder or sense amplifier is disposed in the second region R2. A peripheral circuit transistor electrically connected to the memory cell transistor of the first region R1 is disposed in the second region R2. The third region R3 serves as a buffer for separating the transistors of the first region R1 and the second region R2 from each other, and when operating the transistors of the first region R1 and the second region R2, the third region R3 prevents the first region R1 And the transistors of the second region R2 are disturbed or interfere with each other. However, the third zone R3 can be relatively narrow. Further, the dummy pattern is not interposed between the substrate 100 and the first interlayer insulating layer 170 in the third region R3.

Figure 10 illustrates an example of an electronic system incorporating a semiconductor device fabricated in accordance with the concepts of the present invention.

Referring to FIG. 10, electronic system 1100 can include a controller 1110, an input/output (I/O) unit 1120, a memory device 1130, an interface 1140, and a busbar 1150 that acts as a data communication path. The controller 1110, the input and output unit 1120, the memory device 1130, and/or the interface 1140 may be connected or coupled to each other via the bus bar 1150.

Controller 1110 can comprise, for example, a microprocessor, a digital signal processor, a microcontroller, or any other logic device having a substance similar to that of a microprocessor, digital signal processor, or microcontroller. The input output unit 1120 can include at least one of a keypad, a keyboard, and a display device. The memory device 1130 can be configured to store data and/or commands. The interface unit 1140 can transmit electrical data to or receive electrical data from the communication network. The interface unit 1140 can operate in a wired or wireless manner. For example, interface unit 1140 can include an antenna for wireless communication or a transceiver for wired communication. Although not shown in the drawings, electronic system 1100 can further include a fast DRAM device and/or a fast SRAM device that acts as a cache for improving the operation of controller 1110. Semiconductor devices fabricated in accordance with the teachings of the present invention may be provided in or provided as part of controller 1110 and/or I/O unit 1120.

The electronic system 1100 can be electronically owned by a personal digital assistant (PDA), a portable computer, a network tablet, a wireless telephone, a mobile phone, a digital music player or a memory card, or any other type of product that can wirelessly transmit/receive data. Product utilization. Other examples of products to which the electronic system 1100 of FIG. 10 may be applied include MP3 players, navigators (GPS), solid state drives (SSDs), automobiles, and home electrical equipment.

FIG. 11 illustrates one such example of an electronic product in which the electronic system 1100 of FIG. 10 can be utilized. That is, as depicted in FIG. 11, the electronic system 1100 of FIG. 10 can be a mobile phone 1200.

Finally, embodiments and examples of the inventive concept have been described in detail above. However, the inventive concept may be embodied in many different forms and should not be construed as limited to the embodiments described above. Rather, the embodiments are described so that this disclosure will be thorough and complete, and the invention may be fully conveyed by those skilled in the art. Therefore, the true spirit and scope of the inventive concept is not limited to the embodiments and examples described above but is limited to the scope of the following claims.

100‧‧‧Substrate/substrate surface
110‧‧‧Lower mask layer
112‧‧‧First lower mask pattern
114‧‧‧Second lower mask pattern
120‧‧‧Upper mask layer
122‧‧‧First upper mask pattern
124‧‧‧Second upper mask pattern
125‧‧‧hard mask
127‧‧‧First hard mask pattern
129‧‧‧Second hard mask pattern
130‧‧‧ Sacrifice layer
132‧‧‧First Sacrifice Pattern
134‧‧‧Second sacrificial pattern
142‧‧‧First photoresist pattern
144‧‧‧second photoresist pattern
146‧‧‧Connected photoresist pattern
152‧‧‧First spacer
154‧‧‧Second spacer
160‧‧‧First mask pattern
170‧‧‧First interlayer insulation
180‧‧‧Second interlayer insulation
1100‧‧‧Electronic system
1110‧‧‧ Controller
1120‧‧‧Input/Output (I/O) unit
1130‧‧‧ memory device
1140‧‧ interface
1150‧‧ ‧ busbar
1200‧‧‧Mobile Phone
AF1‧‧‧ first effective fin
AF2‧‧‧ second effective fin
AP1a‧‧‧ first preliminary active pattern
AP1b‧‧‧first active pattern
AP1b'‧‧‧ first unnecessary part
AP2a‧‧‧Second preliminary active pattern
AP2b‧‧‧second active pattern
C1‧‧‧ first connection pattern
C2‧‧‧Second connection pattern
CT1‧‧‧ first contact
CT2‧‧‧second contact
D1‧‧‧first distance
D2‧‧‧Second distance
Dp, dap‧‧ distance
D1‧‧‧ first direction
D2‧‧‧ second direction
GD1‧‧‧first gate dielectric pattern
GD2‧‧‧Second gate dielectric pattern
GE1‧‧‧first gate electrode
GE2‧‧‧second gate electrode
GS1‧‧‧first gate structure
GS2‧‧‧second gate structure
Lines I-I', II-II', III-III', IV-IV', V-V', VI-VI'‧‧
L1‧‧‧ first line pattern
L2‧‧‧ second line pattern
R1‧‧‧ first district
R2‧‧‧Second District
R3‧‧‧ Third District
ST‧‧‧ device isolation pattern
T1‧‧‧ first trench
T2‧‧‧ second trench
W1‧‧‧ first width
W2‧‧‧ second width
W3‧‧‧ third width
W4‧‧‧ fourth width
W5‧‧‧ fifth width
W6‧‧‧ sixth width

The concept of the invention, as well as its objects, features and advantages, will be more clearly understood from the following detailed description. Non-limiting (i.e., representative) embodiments are illustrated with the accompanying drawings. 1A, 2A, 3A, 4A, 5A, 6A, 7A, and 8A illustrate a method of fabricating a semiconductor device in accordance with a representative embodiment of the inventive concept, and each of the figures is a device during its manufacturing process Floor plan. 1B, 2B, 3B, 4B, 5B, 6B, 7B, and 8B are each taken along lines I-I', II-II', and III-III' of Figs. 1A through 8A, respectively. A composite cross-sectional view. 9A is a plan view of first and second photoresist patterns that may be formed in a representative embodiment of a method of fabricating a semiconductor device in accordance with the concepts of the present invention. Fig. 9B is a cross-sectional view taken along line IV-IV', V-V', and VI-VI' of Fig. 9A. 10 is a schematic block diagram of an example of an electronic system including a semiconductor device fabricated in accordance with the concepts of the present invention. Figure 11 is a perspective view of a mobile phone to which an electronic system can be applied. It should be noted that the figures are intended to illustrate the general characteristics of the methods, structures, and/or materials utilized in certain representative embodiments and in addition to the written description provided below. However, the drawings are not to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiments, and should not be construed as limiting or limiting the values or properties covered by the representative embodiments. range. For example, the relative thickness and positioning of molecules, layers, regions, and/or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features.

180‧‧‧Second interlayer insulation

AP1b‧‧‧first active pattern

AP2b‧‧‧second active pattern

CT1‧‧‧ first contact

CT2‧‧‧second contact

D1‧‧‧first distance

D2‧‧‧Second distance

D1‧‧‧ first direction

D2‧‧‧ second direction

GS1‧‧‧first gate structure

GS2‧‧‧second gate structure

I-I’, II-II', III-III’‧‧‧ lines

R1‧‧‧ first district

R2‧‧‧Second District

R3‧‧‧ Third District

Claims (25)

A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first region and the second region, the method comprising: providing across the first region a substrate of the second region and the third region; forming a first preliminary active pattern and a second preliminary active pattern on the substrate such that the first preliminary active pattern and the second preliminary active pattern are convex from the substrate The first preliminary active pattern extends from the first region to the third region to overlap the substrate in the third region, and the second preliminary active pattern is from the second region Extending to the third region to also overlap the substrate in the third region; forming a mask on the substrate in the first region and the second region instead of the third region a pattern whereby the substrate is exposed to the third region; performing a first etching process, the first etching process including using the mask pattern as an etch mask to etch the first preliminary active pattern And the second preliminary active pattern to divide Forming a first active pattern and a second active pattern from the first preliminary active pattern and the second preliminary active pattern; and forming a gate structure on the substrate, the gate structure including the first a first gate structure in which the active patterns intersect and a second gate structure crossing the second active pattern, wherein the first active pattern extends longitudinally in the first direction and intersects with the first direction Separating from each other in two directions, the second active patterns extending in the first direction and spaced apart from each other in the second direction, the first direction spanning the first region, the second region, and The third zone extends, and in the second direction, a distance between neighbors in the first active pattern is different from a distance between neighbors in the second active pattern. The method of manufacturing a semiconductor device according to claim 1, wherein the forming of each of the first preliminary active patterns includes forming a pair of first line patterns each extending longitudinally in the first direction And forming a first connection pattern connecting the adjacent ends of the first line pattern to each other in the third region, and forming each of the second preliminary active patterns includes forming each in the A pair of second line patterns extending longitudinally in one direction, and a second connection pattern forming a second connection pattern connecting the adjacent ends of the second line pattern to each other in the third region. The method of fabricating a semiconductor device according to claim 2, wherein the first etching process removes the first connection pattern and the second connection pattern. The method of manufacturing a semiconductor device according to claim 2, wherein a distance between the pair of first line patterns in the second direction is different from a distance between the pair of second line patterns. The method of manufacturing a semiconductor device according to claim 4, wherein the first preliminary active pattern and the second preliminary active pattern are formed such that adjacent ones of the first preliminary active patterns are in between The distance in the second direction is substantially equal to the distance between the first line patterns, and the distance between the neighbors in the second preliminary active pattern in the second direction is substantially equal to Said distance between the second line patterns. The method of manufacturing a semiconductor device according to claim 1, wherein the forming of the first preliminary active pattern and the second preliminary active pattern comprises: being included in the first region and the second region Forming a hard mask on the substrate; forming a first sacrificial pattern on the hard mask in the first region and forming a second sacrificial pattern on the hard mask in the second region; Forming a first spacer and a second spacer on sidewall surfaces of the first sacrificial pattern and the second sacrificial pattern; removing the first sacrificial pattern and the second sacrificial pattern; etching by the a spacer and the hard mask exposed by the second spacer to form a first hard mask pattern and a second hard mask pattern in the first region and the second region, respectively; The first hard mask pattern and the second hard mask pattern are used as an etch mask to etch an upper portion of the substrate to form a first surface defining the first preliminary active pattern and the second preliminary active pattern One Groove. The method of manufacturing a semiconductor device according to claim 6, wherein the forming of the first sacrificial pattern and the second sacrificial pattern comprises: forming a sacrificial layer on the hard mask; Forming a first photoresist pattern and a second photoresist pattern on the sacrificial layer in a region and the second region; and using the first photoresist pattern and the second photoresist pattern as an etch mask The sacrificial layer is etched. The method of fabricating a semiconductor device according to claim 7, wherein the forming of the first photoresist pattern and the second photoresist pattern comprises exposing a photoresist layer on the sacrificial layer to a given a wavelength of light that develops the exposed photoresist layer, the first photoresist pattern includes a plurality of first linear photoresist patterns at a first pitch, and the second photoresist pattern includes a plurality of second linear resist patterns spaced apart from each other by the first linear resist pattern in the first direction by a first distance, the second pitch being different from the first pitch And the first distance is less than the given wavelength of the light used to form the photoresist pattern. The method of fabricating a semiconductor device according to claim 6, wherein the first etching process forms a second trench in the third region, and the second trench in the third region a bottom portion disposed at a lower level than a bottom portion of the first trench, and a widest portion of the second trench having a third region and the first region and the third region, respectively a side at a boundary with the second zone. A method of fabricating a semiconductor device, comprising: patterning a substrate to form a first trench defining a first preliminary active pattern and a second preliminary active pattern, the first preliminary active pattern extending longitudinally in a first direction and in The first direction intersects with each other in a second direction, the second preliminary active pattern extending longitudinally in the first direction and spaced apart from the first preliminary active pattern in the first direction and Separating from each other in the second direction, a distance between the neighbors in the first preliminary active pattern in the second direction is different from a distance between neighbors in the second preliminary active pattern a distance in the second direction; forming a mask pattern exposing the first preliminary active pattern and the end portion of the second preliminary active pattern on the substrate, the end portion of the first preliminary active pattern Collectively spaced apart from the end portion of the second preliminary active pattern on the first surface; performing an etching process, wherein the mask pattern is used as an etch mask, the etching system Removing the first preliminary active pattern and the end portions of the second preliminary active pattern and forming a first active pattern and a second active pattern therefrom, respectively; and forming the first active on the substrate a first gate structure crossing the pattern and a second gate structure crossing the second active pattern, wherein the etching process forms a second trench, the second trench having a lower than the first a bottom at a level of the bottom of the trench, and such that a width of the second trench in the first direction is equal to a set between all of the first active patterns and a set of all of the second active patterns The distance in the first direction. The method of manufacturing a semiconductor device according to claim 10, wherein the forming of each of the first preliminary active patterns includes forming a pair of first line patterns and a first connection pattern, the first line a pattern extending longitudinally in the first direction, the first connection pattern connecting adjacent end portions of the first line pattern, and forming each of the second preliminary active patterns includes forming a pair of second a line pattern and a second connection pattern, the second line pattern extending longitudinally in the first direction, the second connection pattern connecting adjacent end portions of the second line pattern, and the first connection pattern and The second connection patterns respectively constitute the end portions of the first preliminary active pattern and the second preliminary active pattern. The method of manufacturing a semiconductor device according to claim 11, wherein the first preliminary active pattern and the second preliminary active pattern are formed such that adjacent ones of the first preliminary active patterns are in between The distance in the second direction is substantially equal to the distance between the first line patterns, and the distance between the neighbors in the second preliminary active pattern in the second direction is substantially equal to the number The distance between the two line patterns. The method of manufacturing a semiconductor device according to claim 10, wherein the forming of the first trench comprises: sequentially forming a lower mask layer and an upper mask layer on the substrate; Forming a first sacrificial pattern and forming a second sacrificial pattern on the second region; forming a first spacer and a second spacer on sidewall surfaces of the first sacrificial pattern and the second sacrificial pattern, respectively; The first spacer and the second spacer are used as an etch mask to etch the upper mask layer to form a first upper mask pattern and a second upper portion on the first region and the second region, respectively a mask pattern; the first upper mask pattern and the second upper mask pattern are used as an etch mask to etch the lower mask layer to be on the first region and the second region, respectively Forming a first lower mask pattern and a second lower mask pattern; and etching the first lower mask pattern and the second lower mask pattern as an etch mask to etch an upper portion of the substrate. The method of manufacturing a semiconductor device according to claim 13, wherein the forming of the first sacrificial pattern and the second sacrificial pattern comprises: forming a sacrificial layer on the upper mask layer; The layer performs a photolithography process to form a first photoresist pattern on the first region and a second photoresist pattern on the second region, the photolithography process including exposing the photoresist layer to having An exposure process of a predetermined wavelength of light; and etching the sacrificial layer by using the first photoresist pattern and the second photoresist pattern as an etch mask. The method of manufacturing a semiconductor device according to claim 14, wherein the forming of the first photoresist pattern comprises forming longitudinally extending in the first direction and spaced apart from each other in the second direction. a first linear resist pattern of the distance, the forming of the second photoresist pattern including forming a length extending longitudinally in the first direction and spaced apart from each other by the first distance in the second direction a second linear resist pattern of two distances, and a set of all of the second linear resist patterns is spaced apart from the set of all of the first photoresist patterns by a distance in the first direction, the distance being less than The wavelength of light in the exposure process. The method of fabricating a semiconductor device according to claim 10, wherein the first gate structure is used as a portion of a memory cell transistor, and the second gate structure is used as a portion of a peripheral circuit transistor. . A method of fabricating a semiconductor device, comprising: forming a sacrificial layer on a substrate; performing a photolithography process to form a patterned photoresist layer on the sacrificial layer, the patterned photoresist layer comprising a first photoresist a pattern and a second photoresist pattern, wherein at least one of the first photoresist patterns extends from a memory cell region to be formed into a memory cell to a portion adjacent to the memory cell region and a peripheral circuit region where a peripheral circuit is to be formed a third region, and at least one of the second photoresist patterns extending from the peripheral circuit region to the third region; using the patterned photoresist layer as an etch mask to etch the sacrificial layer Forming a patterned sacrificial material layer in the memory cell region, the peripheral circuit region, and the third region; forming a sidewall spacer along a side surface of the patterned sacrificial material layer; removing The patterned sacrificial material layer and the spacer is used as an etch mask to etch the substrate to pattern the substrate in the memory cell region, the peripheral circuit region, and the third region In the office Forming a mask on the substrate, the mask covering a portion of the substrate that is patterned in both the memory cell region and the peripheral circuit region while exposing the substrate in the third region a patterned portion; the mask is used as an etch mask to etch the substrate in the third region to remove portions of the substrate that are patterned in the third region, and thereby Forming a plurality of first active regions of the substrate in the memory cell region and forming a plurality of second active regions of the substrate in the peripheral circuit region; forming an extension across the first active region a first gate; and a second gate extending across the second active region. The method of fabricating a semiconductor device according to claim 17, wherein the spacer is used as an etch mask to etch the substrate in the memory cell region and the peripheral circuit region Forming a first trench in the substrate, and the etching of the substrate in the third region forms a second trench in the substrate in the third region, the second trench having a larger than The depth of the depth of the first trench. The method of fabricating a semiconductor device according to claim 18, further comprising forming a filling of the second trench in the first trench and the second trench and only partially filling the first trench An isolation layer of the insulating material of the trench such that an active pattern of the substrate protrudes upward from the isolation layer in each of the memory cell region and the peripheral circuit region, and wherein the first gate A pole and the second gate are formed on the isolation layer. The method of fabricating a semiconductor device according to claim 17, further comprising forming a lower hard mask layer on the substrate and forming an upper hard mask on the lower hard mask layer before forming the sacrificial layer a cap layer, and using the spacer as an etch mask to etch the substrate includes using the spacer as an etch mask to etch the upper hard mask layer to form an upper mask pattern, The upper mask pattern is used as an etch mask to etch the lower hard mask layer to form a lower mask pattern, and the upper mask pattern and the lower mask pattern are used as an etch mask to etch the Substrate. The method of fabricating a semiconductor device according to claim 17, wherein the photolithography process comprises an exposure process of exposing the photoresist layer to light having a given wavelength, in the first direction, extending to the a distance between a set of all of the first photoresist patterns of the third region and a set of all of the second photoresist patterns extending to the third region is less than the given wavelength, the first direction being Extending between the memory cell region and the peripheral circuit region directly across one direction of the third region. A semiconductor device comprising: a substrate having a first region, a second region, and a third region between the first region and the second region; a first active pattern from the first of the substrate a region protruding upward, extending in a first direction crossing the first region to the third region and spaced apart from each other in a second direction crossing the first direction; a second active pattern, Projecting upward from the second region of the substrate, extending in the first direction and spaced apart from each other in the second direction, when measured in the second direction, the first a distance between neighbors in an active pattern is different from a distance between neighbors in the second active pattern; a first gate structure crossing the first active pattern; and a second gate a pole structure that intersects the second active pattern, wherein the third region is defined by a trench, the trench being provided on the substrate and between the first region and the second region, a sidewall surface of the first active pattern along the second direction in the first region and the first The boundaries between the three regions are aligned, and the sidewall surfaces of the second active pattern are aligned along the second direction at the boundary between the second region and the third region. The semiconductor device of claim 22, wherein a maximum width of the trench is substantially equal to the first active pattern and the second active pattern when measured in the first direction The distance between the side wall surfaces. The semiconductor device of claim 22, wherein a top surface of the first region of the substrate meets the boundary of the first region and the third region when viewed in a cross-sectional view a sidewall of the trench at the location, and a top surface of the second region of the substrate meets an opposite sidewall of the trench at the boundary of the second region and the third region. The semiconductor device of claim 22, wherein the first gate structure is part of a memory cell transistor and the second gate structure is part of a peripheral circuit transistor.